DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
Information disclosure statement filed 1 July 2024 has been fully considered.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the subject matter of claims 10 and 18, “a gate line arranged in at least one active area among the plurality of active areas,” and, “a gate line arranged in the at least one logic active area,” respectively must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: SEMICONDUCTOR MEMORY DEVICE COMPRISING DEVICE SEPARATION TRENCHES.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 10 and 18-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 10 and 18 recite the limitations, “a gate line arranged in at least one active area among the plurality of active areas,” and, “a gate line arranged in the at least one logic active area.” It is unclear how the gate line is arranged in the active area, and how the gate line is distinct from the word line and bit line. For the purposes of applying art, the claimed gate line will be interpreted as a portion of one or both of the claimed word line and bit line.
Claims 19 and 20 are rejected for merely containing the flaws of the parent claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Noh et al. (US Patent Application Publication 2020/0381436, hereinafter Noh ‘436).
With respect to claim 1, Noh ‘436 teaches (e.g. FIGs. 1, 2B, 2C, and 6D) a semiconductor memory device as claimed, comprising:
a substrate (102) having a plurality of active areas (AC) defined by a device separation trench (104T) ([0023, 0027]);
a device separation material layer (104) that fills the device separation trench (104T) and that is formed of a first material ([0027]);
a word line trench (WT) that crosses the plurality of active areas (AC) and the device separation material layer (104) and that extends in a first horizontal direction ([0029]);
a gate dielectric layer (120) covering an inner wall of the word line trench (WT) ([0029]); and
a word line (WL) that fills a portion of the word line trench (WT) on the gate dielectric layer (120) ([0034]),
wherein the device separation material layer (104) comprises a doped layer (DB) inside the device separation material layer, the doped layer including a second material different from the first material ([0038]).
With respect to claim 2, Noh ‘436 teaches wherein the first material comprises silicon oxide ([0027]), and the second material comprises a material of silicon (Si), germanium (Ge), argon (Ar), or a combination thereof ([0038]).
With respect to claim 3, Noh ‘436 teaches wherein the second material forms the doped layer (DB) as a result of an ion implantation into the device separation material layer (104) ([0038]).
The expression, “as a result of an ion implantation,” is taken to be a product-by-process limitation and is given limited patentable weight. Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. In re Thorpe, 111 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). See MPEP 2113.
With respect to claim 4, Noh ‘436 teaches wherein the second material is implanted into the device separation material layer (104) with an energy not greater than about 2.5 keV ([0085]).
With respect to claim 5, Noh ‘436 teaches wherein a concentration of the second material implanted into the device separation material layer is in a range of about 0.1*1016 atom/cm2 to about 0.2*1016 atom/cm2 ([0085]).
With respect to claim 6, Noh ‘436 teaches wherein the first material does not comprise silicon nitride (when selected from silicon oxide) ([0027]).
With respect to claim 7, Noh ‘436 teaches wherein an upper surface of the doped layer (DB) is coplanar with an upper surface of the device separation material layer (104) in a vertical direction ([0027, 0038]).
With respect to claim 8, Noh ‘436 teaches wherein a lower surface of the doped layer (DB) is at a higher level than a lower surface of the device separation material layer (104) in a vertical direction ([0027, 0038]).
With respect to claim 9, Noh ‘436 teaches wherein: at all vertical levels in an area in which the doped layer (DB) is formed, a horizontal cross-sectional area of the doped layer is within a horizontal cross-sectional area of the device separation material layer (104) ([0027, 0038]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Noh ‘436 as applied to claim 1 above, and further in view of Wang et al. (US Patent Application Publication 2017/0330882, hereinafter Wang ‘882).
With respect to claim 10, Noh ‘436 teaches the device as described in claim 1 above, including the additional limitation further comprising: a plurality of bit lines (BL and 138) respectively arranged on the plurality of active areas (AC) and extending in a second horizontal direction orthogonal to the first horizontal direction; a gate line (a portion of one of BL or WL functioning as a gate line) arranged in at least one active area among the plurality of active areas; a plurality of landing pads (LP) that fill an upper side portion of a space between the plurality of bit lines and that respectively extend onto the plurality of bit lines; and a plurality of capacitor structures (“capacitors” [0025]) including a plurality of lower electrodes (“bottom electrodes” [0025]) respectively in contact with the plurality of landing pads ([0025, 0051, 0057]).
Thus, Noh ‘436 is shown to teach all the features of the claim with the exception of wherein the plurality of capacitor structures include an upper electrode and a capacitor dielectric layer arranged between the upper electrode and the plurality of lower electrodes.
However, Wang ‘882 teaches (FIG. 29) a capacitor structure (900) including an upper electrode (906) and a capacitor dielectric layer (904) arranged between the upper electrode and a plurality of lower electrodes (902) ([0086]) to form a capacitor of a memory device such as a DRAM ([0046]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the plurality of capacitor structures of Noh ‘436 including an upper electrode and a capacitor dielectric layer arranged between the upper electrode and the plurality of lower electrodes as taught by Wang ‘882 to form a capacitor of a memory device such as a DRAM.
Claims 11-17 are rejected under 35 U.S.C. 103 as being unpatentable over Noh ‘436 in view of Seong et al. (US Patent Application Publication 2021/0082924, hereinafter Seong ‘924).
With respect to claim 11, Noh ‘436 teaches (e.g. FIGs. 1, 2B, 2C, and 6D) a semiconductor memory device substantially as claimed, comprising:
a substrate (102) including a cell array area (10) ([0023, 0027]);
a plurality of active areas (AC) defined by a device separation trench (104T) in the cell array area (10) ([0023, 0027]);
a device separation material layer (104) that fills the device separation trench (104T) ([0027]);
a word line trench (WT) that crosses the plurality of active areas (AC) and the device separation material layer (104) and that extends in a first horizontal direction ([0029]);
a gate dielectric layer (120) covering an inner wall of the word line trench (WT) ([0029]); and
a word line (WL) that fills a portion of the word line trench (WT) on the gate dielectric layer (120) ([0034]),
wherein the device separation material layer (104) comprises a recess area (area inside undoped portions of 104) formed in a vertical direction that is perpendicular to the substrate (102) ([0027]), and
the recess area (area inside undoped portions of 104) is filled with an ion implantation layer (DB) ([0038]).
Thus, Noh ‘436 is shown to teach all the features of the claim with the exception of wherein the substrate includes a periphery circuit area.
However, Seong ‘924 teaches (FIG. 4) a memory comprising a substrate (110) including a periphery circuit area (PR) for hosting elements such as logic, decoders, sense amplifiers, and buffers for said memory ([0014, 0017]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the substrate of Noh ‘436 including a periphery circuit area as taught by Seong ‘924 for hosting elements such as logic, decoders, sense amplifiers, and buffers for said memory.
With respect to claim 12, Noh ‘436 teaches wherein the ion implantation layer (DB) comprises a material of silicon (Si), germanium (Ge), argon (Ar), or a combination thereof ([0038]).
With respect to claim 13, Noh ‘436 teaches wherein a concentration of elements included in the ion implantation layer (DB) is in a range of about 0.1*1016 atom/cm2 to about 0.2*1016 atom/cm2 ([0085]).
With respect to claim 14, Noh ‘436 teaches wherein: a width of a horizontal cross-sectional area of the recess area (area inside undoped portions of 104) is not greater than a width of a horizontal cross-sectional area of the device separation material layer (104), and an upper surface of the recess area is coplanar with an upper surface of the device separation material layer ([0027]).
With respect to claim 15, Noh ‘436 teaches wherein a width of the recess area (area inside undoped portions of 104) in the vertical direction is less than a width of the device separation material layer (104) in the vertical direction ([0027]).
With respect to claim 16, Noh ‘436 teaches wherein the device separation material layer (104) comprises silicon oxide but not silicon nitride (when selected from silicon oxide) ([0027]).
With respect to claim 17, Noh ‘436 teaches wherein the recess area (area inside undoped portions of 104) is physically spaced apart from the substrate (102) ([0027]).
Claims 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Noh ‘436 in view of Seong ‘924 and Wang ‘882.
With respect to claim 18, Noh ‘436 teaches (e.g. FIGs. 1, 2B, 2C, and 6D) a semiconductor memory device substantially as claimed, comprising:
a substrate (102) having a cell array area (10) including a plurality of active areas (AC) defined by a device separation trench (104T) ([0023, 0027]);
a device separation material layer (104) that fills the device separation trench (104T) in the cell array area (10) ([0027]);
a plurality of word lines (WL) respectively crossing the plurality of active areas (AC) and extending in a first horizontal direction ([0034]);
a plurality of bit lines (BL and 138) respectively arranged in the plurality of active areas (AC) and extending in a second horizontal direction that is orthogonal to the first horizontal direction ([0051]);
a plurality of buried contacts (140P) that fill a lower side portion of a space between the plurality of bit lines (BL and 138) and that are respectively connected to the plurality of active areas (AC) ([0049]);
a plurality of landing pads (LP) that fill an upper side portion between the plurality of bit lines (BL and 138) and that respectively extend onto the plurality of bit lines ([0057]); and
a plurality of capacitor structures (“capacitors”) including a plurality of lower electrodes (“bottom electrodes”) respectively in contact with the plurality of landing pads (LP) ([0025]),
wherein the device separation material layer (104) comprises an ion implantation layer (DB) that extends into the device separation material layer to a first depth from an upper surface of the device separation material layer toward the substrate (102) ([0038]), and
wherein a horizontal cross-section of the ion implantation layer (DB) is within a horizontal cross-section of the device separation material layer (104), and the first depth is less than a thickness of the device separation material layer in a vertical direction ([0038]).
Thus, Noh ‘436 is shown to teach all the features of the claim with the exception of:
wherein the substrate has a periphery circuit area in which at least one logic active area is defined, and an interface area between the cell array area and the periphery circuit area;
a gate line arranged in the at least one logic active area; and
wherein the plurality of capacitor structures include an upper electrode and a capacitor dielectric layer arranged between the upper electrode and the plurality of lower electrodes.
However, Seong ‘924 teaches (FIG. 4) a memory comprising a substrate (110) including a periphery circuit area (PR) and an interface area (DM) between a cell array area (CR) and said periphery circuit area, wherein said periphery circuit area has a gate line (GLP) arranged in an at least one logic active area thereof for hosting elements such as logic, decoders, sense amplifiers, and buffers for said memory ([0014, 0017]).
Further, Wang ‘882 teaches (FIG. 29) a capacitor structure (900) including an upper electrode (906) and a capacitor dielectric layer (904) arranged between the upper electrode and a plurality of lower electrode (902) ([0086]) to form a capacitor of a memory device such as a DRAM ([0046]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the substrate of Noh ‘436 having a periphery circuit area in which at least one logic active area is defined, and an interface area between the cell array area and the periphery circuit area, a gate line arranged in the at least one logic active area as taught by Seong ‘924 for hosting elements such as logic, decoders, sense amplifiers, and buffers for said memory; and to have formed the plurality of capacitor structures of Noh ‘436 including an upper electrode and a capacitor dielectric layer arranged between the upper electrode and the plurality of lower electrodes as taught by Wang ‘882 to form a capacitor of a memory device such as a DRAM.
With respect to claim 19, Noh ‘436 teaches wherein the ion implantation layer (DB) comprises a material of silicon (Si), germanium (Ge), argon (Ar), or a combination thereof, and wherein a doping concentration of the material is in a range of about 0.1*1016 atom/cm2 to about 0.2*1016 atom/cm2 ([0038, 0085]).
With respect to claim 20, Noh ‘436 teaches wherein the device separation material layer (104) comprises silicon oxide but not silicon nitride (when selected from silicon oxide) ([0027]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Christopher M. Roland whose telephone number is (571)270-1271. The examiner can normally be reached Monday-Friday, 10:00AM-7:00PM Eastern.
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/C.M.R./Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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