DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 7-12, 14-18 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kang (US 2021/0099172).
In regards to claim 1, Kang discloses of an apparatus, comprising: a first external pin (for example see pads in Figs 1-3, 5) communicatively coupled to a first circuit (see Figs 1-3, 5); a second external pin (for example see pads in Figs 1-3, 5) communicatively coupled to a second circuit (see Figs 1-3, 5); and a calibration circuit (for example see 114, 124, 210, 300 in Figs 1-3) configured to: generate a first calibration signal (for example COM1) for calibrating a first termination resistance of the first circuit; and generate a second calibration signal (for example COM2) for calibrating a second termination resistance of the second circuit, wherein the second calibration signal is generated independently of the first calibration signal (see Figs 1-3, 5 and Paragraphs 0018-0057).
In regards to claim 2, Kang discloses of the apparatus of claim 1, wherein the first circuit comprises one of a pull-up driver and a pull-down driver (see Fig 2) having the first termination resistance and the other of the pull-up driver and the pull-down driver having a third termination resistance, and wherein the calibration circuit is configured to generate a third calibration signal for calibrating the third termination resistance, and wherein the second calibration signal is generated independently of the third calibration signal (see Figs 1-3, 5 and Paragraphs 0018-0057).
In regards to claim 3, Kang discloses of the apparatus of claim 1, wherein the second circuit comprises a termination driver having the second termination resistance (see Figs 1-3, 5).
In regards to claim 4, Kang discloses of the apparatus of claim 1, wherein the calibration circuit is in a memory chip and the calibration circuit comprises: a first pull-up driver (321-1) and a pull-down driver (321-2) used to generate the first calibration signal via a first comparator (see 322); and a second pull-up driver (311) used to generate the second calibration signal via a second comparator (see 312) based on a precision resistor (ZQ) arranged outside of the memory chip (see Figs 2-3).
In regards to claim 7, Kang discloses of the apparatus of claim 1, wherein the calibration circuit comprises a comparator (see 312, 322 in Fig 3) configured to generate the first calibration signal and the second calibration signal (see Figs 1-3, 5).
In regards to claim 8, Kang discloses of the apparatus of claim 1, wherein the first calibration signal (COM1) is generated based on a first set of characteristics (related to VREF1) associated with the first circuit and the second calibration signal (COM2) is generated based on a second set of characteristics (reflated to VREF2) associated with the second circuit (see Figs 1-3, 5).
In regards to claim 9, Kang discloses of a method, comprising: generating a first calibration signal (for example COM2) for calibrating a first termination resistance of a first circuit communicatively coupled to a first external pin (see pads in Figs 1-3, 5); and generating a second calibration signal (for example COM1) for calibrating a second termination resistance of a second circuit communicatively coupled to a second external pin (see pads in Figs 1-3, 5), wherein the second calibration signal is generated independently of the first calibration signal (see Figs 1-3, 5 and Paragraphs 0018-0057).
In regards to claim 10, Kang discloses of the method of claim 9, comprising: generating a third calibration signal for calibrating a third termination resistance, wherein the first circuit comprises one of a pull-up driver and a pull-down driver (see Fig 2) having the first termination resistance and the other of the pull-up driver and the pull-down driver having the third termination resistance, and wherein the second calibration signal is generated independently of the third calibration signal (see Figs 1-3, 5).
In regards to claim 11, Kang discloses of the method of claim 10, wherein the second circuit comprises a termination driver having the second termination resistance (see Figs 1-3, 5).
In regards to claim 12, Kang discloses of the method of claim 9, wherein generating the first calibration signal comprises generating the first calibration signal by using a first pull-up driver and a pull-down driver via a first comparator (for example 322), and generating the second calibration signal comprises generating the second calibration signal by using a second pull-up driver via a second comparator (for example 312) based on a precision resistor (ZQ, see Fig 3).
In regards to claim 14, Kang discloses of the method of claim 9, wherein generating the first calibration signal and generating the second calibration signal comprise generating the first calibration signal and the second calibration signal by a comparator (see 312, 322 in Fig 3).
In regards to claim 15, Kang discloses of the method of claim 9, wherein generating the first calibration signal comprises generating the first calibration signal (COM2) based on a first set of characteristics associated with the first circuit (for example in relation with VREF2), and wherein generating the second calibration signal (COM1) comprises generating the second calibration signal based on a second set of characteristics associated with the second circuit (for example in relation with VREF1, see Fig 3).
In regards to claim 16, Kang discloses of a calibration circuit, comprising: a first comparator (for example see 312) configured to generate a first calibration signal (COM1) for calibrating a first termination resistance of a first circuit communicatively coupled to a first external pin (see pads in Figs 1-3, 5); and a second comparator (for example see 322) configured to generate a second calibration signal (COM2) for calibrating a second termination resistance of a second circuit communicatively coupled to a second external pin (see pads in Figs 1-3, 5), wherein the second calibration signal is generated independently of the first calibration signal (for example see Figs 1-3, 5).
In regards to claim 17, Kang discloses of the calibration circuit of claim 16, wherein the first circuit comprises one of a pull-up driver and a pull-down driver having the first termination resistance (for example in response to signals PCA<1:n>) and the other of the pull-up driver and the pull-down driver having a third termination resistance (see Fig 5, for example in response to signals PCB<1:n>), and wherein the calibration circuit is configured to generate a third calibration signal for calibrating the third termination resistance, and wherein the second calibration signal is generated independently of the third calibration signal (see Figs 21-3, 5; for example second calibration signal related to NCA, NCB, which is independent).
In regards to claim 18, Kang discloses of the calibration circuit of claim 16, wherein the second circuit comprises a termination driver having the second termination resistance (for example see Figs 1-3, 5).
In regards to claim 20, Kang discloses of the calibration circuit of claim 16, wherein the first calibration signal is generated by the first comparator (312) using a first reference signal (VREF1) generated based on a first set of characteristics associated with the first circuit, and the second calibration signal is generated by the second comparator (322) using a second reference signal (VREF2) generated based on a second set of characteristics associated with the second circuit (see Fig 3).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5-6, 13 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Kang (US 2021/0099172).
In regards to claims 5, 13 and 19, Kang discloses of the apparatus, method and calibration circuit of respective claims 1, 9 and 16 as found within the explanations above.
However, Kang does not explicitly disclose of wherein the calibration circuit is configured to generate the first calibration signal and the second calibration signal simultaneously in a time period.
One having ordinary skill in the art would readily recognize the combination of calibrating multiple portions of an integrated circuit within a period of time can optimize the characteristics of that device.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to generate calibration signals simultaneously for optimizing transmission efficiency and characteristics by increasing operation and transmission speeds and reducing power consumption of the circuit device.
In regards to claim 6, Kang discloses of the apparatus of claim 5, wherein the calibration circuit comprises: a first comparator (312) configured to generate the first calibration signal based on a first reference signal (VREF1); and a second comparator (322) configured to generate the second calibration signal based on a second reference signal (VREF2, see Fig 3).
Conclusion
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/JASON M CRAWFORD/Primary Examiner, Art Unit 2844