DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the claimed capacitive couplings must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 10-12 and 15-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Krauss (US 2012/0013391).
In regards to claim 1, Krauss discloses of an apparatus comprising: a complementary metal-oxide-semiconductor (CMOS) pass gate (110) circuit including a first n-channel transistor (112) and a first p-channel transistor (111); a control circuit (delivering control signal INPUT) to generate control signals to activate the CMOS pass gate circuit (110); and a bootstrap circuit (120) electrically connected between the CMOS pass gate circuit (110) and the control circuit (delivering control signal INPUT), said bootstrap circuit (120) to increase a first drive gain of the first n-channel transistor (112) and a second drive gain of the first p-channel transistor (111, see Fig 1 and Paragraphs 0009-0023).
In regards to claim 2, Krauss discloses of the apparatus of claim 1, wherein said bootstrap circuit comprises a second n-channel transistor (124) and a second p-channel transistor (123), said second n-channel transistor (124) electrically connected between the control circuit (delivering control signal INPUT) and the first n-channel transistor (112), said second p-channel transistor (123) electrically connected between the control circuit (delivering control signal INPUT) and the first p-channel transistor (111), said second n-channel transistor (124) to receive a first complementary control signal (complementary inverted output from 127) of the control signals (INPUT) and convey a first drive voltage corresponding to the first complementary control signal to the first n-channel transistor (112), said first drive voltage to activate the first n-channel transistor (112) and increase the first drive gain, said second p-channel transistor (123) to receive a second complementary control signal of the control signals (INPUT) and convey a second drive voltage corresponding to the second complementary control signal to the first p-channel transistor (111), said second drive voltage to activate the first p-channel transistor (111) and increase the second drive gain (see Fig 1 and Paragraphs 0009-0023).
In regards to claim 3, Krauss discloses of the apparatus of claim 2, wherein said control circuit including an output having a first signal path electrically connected to the second p-channel transistor (123) and a second signal path electrically connected to the second n-channel transistor (124), said second signal path including an inverter (127), said inverter to invert a control signal (INPUT) of the control signals to generate the first complementary control signal (see Fig 1 and Paragraphs 0009-0023).
In regards to claim 4, Krauss discloses of the apparatus of claim 2, wherein said control signals include the first complementary control signal and the second complementary control signal, said control circuit includes a first output electrically connected to the second n-channel transistor (124) and a second output electrically connected to the second p-channel transistor (123), said first output to convey the first complementary control signal (complementary INPUT output from inverter 127) to the second n-channel transistor (124), said second output to convey the second complementary control signal (INPUT) to the second p-channel transistor (123, see Fig 1 and Paragraphs 0009-0023).
In regards to claim 5, Krauss discloses of the apparatus of claim 2, comprising an input terminal (108) electrically connected to the CMOS pass gate circuit (110), said input terminal (108) to convey an input signal to the CMOS pass gate circuit (110), said input signal to alternate between a high voltage level and a low voltage level, said high voltage level being greater than said low voltage level, respective ones of said first p-channel transistor (111), first n-channel transistor (112), second p-channel transistor (123), and second n-channel transistor (124) including a respective gate terminal, a respective source terminal, and a respective drain terminal (see Fig 1 and Paragraphs 0009-0023).
In regards to claim 10, Krauss discloses of a circuit arrangement comprising: a complementary metal-oxide-semiconductor (CMOS) pass gate circuit (110); and a bootstrap circuit (120) electrically connected to the CMOS pass gate circuit (110), said bootstrap circuit (120) to increase a drive gain of the CMOS pass gate circuit (110, see Fig 1 and Paragraphs 0009-0023).
In regards to claim 11, Krauss discloses of the circuit arrangement of claim 10, wherein said CMOS pass gate circuit (110) comprises a first n-channel transistor (112) and a first p-channel transistor (111), said bootstrap circuit (120) comprises a second n-channel transistor (124) electrically connected to the first n-channel transistor (112) and a second p-channel transistor (123) electrically connected to the first p-channel transistor (111), said second n-channel transistor (124) to convey a first drive voltage to the first n-channel transistor (112), said second p-channel transistor (123) to convey a second drive voltage to the first p-channel transistor (111, see Fig 1 and Paragraphs 0009-0023).
In regards to claim 12, Krauss discloses of the circuit arrangement of claim 11, respective ones of said first p-channel transistor (111), first n-channel transistor (112), second p-channel transistor (123), and second n-channel transistor (124) including a respective gate terminal, a respective source terminal, and a respective drain terminal (see Fig 1 and Paragraphs 0009-0023).
In regards to claim 15, Krauss discloses of the circuit arrangement of claim 12, comprising a control circuit (130), an input terminal (108), said gate terminal of the first p-channel transistor (111) electrically connected to the source terminal of the second p-channel transistor (123), said gate terminal of the first n-channel transistor (112) electrically connected to the source terminal of the second n-channel transistor (124), said source terminals of the first p-channel transistor (111) and the first n-channel transistor (112) electrically connected to the input terminal (108), said gate terminals of the second p-channel transistor (123) and the second n-channel transistor (124) electrically connected to one or more power supplies (VDD, VSS associated with the control signal INPUT), said drain terminals of the second p-channel transistor (123) and the second n-channel transistor (124) electrically connected to the control circuit (130, see Fig 1 and Paragraphs 0009-0023).
In regards to claim 16, Krauss discloses of a method comprising: activating, by one or more power supplies, a bootstrap circuit (120); generating, by a control circuit (delivering control signal INPUT), one or more control signals; activating, by the bootstrap circuit (120), a complementary metal-oxide-semiconductor (CMOS) pass gate circuit (110) based on the one or more control signals (see Fig 1); receiving, by the CMOS pass gate circuit (110), an input signal (at 108); and increasing, by the bootstrap circuit (120), a drive gain of the CMOS pass gate circuit (110, see Fig 1 and Paragraphs 0009-0023).
In regards to claim 17, Krauss discloses of the method of claim 16, comprising receiving, by a first n-channel transistor (112) of the CMOS pass gate circuit (110), a first drive voltage corresponding to a first complementary control signals of the one or more control signals from the bootstrap circuit (120), receiving, by a first p-channel transistor (111) of the CMOS pass gate circuit (110), a second drive voltage corresponding to a second complementary control signal of the one or more control signals from the bootstrap circuit (120, see Fig 1 and Paragraphs 0009-0023).
Allowable Subject Matter
Claims 6-9, 13-14 and 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
In regards to claim 6, the prior art does not disclose of the apparatus of claim 5, comprising a first capacitive coupling formed between the gate and source terminals of the first n-channel transistor, said first capacitive coupling generated by the first drive voltage, a second capacitive coupling formed between the gate and source terminals of the first p-channel transistor, said second capacitive coupling generated by the second drive voltage, nor would it have been obvious to one of ordinary skill in the art to do so. Claims 7-9 are also objected to as being dependent on claim 6.
In regards to claim 13, the prior art does not disclose of the circuit arrangement of claim 12, comprising an input terminal to receive an input signal, said input terminal electrically connected to the respective source terminals of the first n-channel transistor and the first p-channel transistor, a first capacitive coupling between the gate and source terminals of the first n-channel transistor, said first capacitive coupling generated by the first drive voltage, a second capacitive coupling between the gate and source terminals of the first p-channel transistor, said second capacitive coupling generated by the second drive voltage, nor would it have been obvious to one of ordinary skill in the art to do so. Claim 14 is also objected to as being dependent on claim 13.
In regards to claim 18, the prior art does not disclose of the method of claim 17, comprising generating, in response to receiving the first drive voltage at the first n-channel transistor, a first capacitive coupling between a gate terminal and a source terminal of the first n-channel transistor, generating, in response to receiving the second drive voltage at the first p-channel transistor, a second capacitive coupling between a gate terminal and a source terminal of the first p-channel transistor, nor would it have been obvious to one of ordinary skill in the art to do so. Claims 19 and 20 are also objected to as being dependent on claim 18.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jason M Crawford whose telephone number is (571)272-6004. The examiner can normally be reached Mon-Fri 6:00am-3:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander Taningco can be reached at 571-272-8048. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JASON M CRAWFORD/Primary Examiner, Art Unit 2844