DETAILED ACTION
This Office Action is sent in response to Applicant’s Communication received 07/01/24 for application number 18/760,801. The Office hereby acknowledges receipt of the following and placed of record in file: Specification, Drawings, Abstract, Oath/Declaration, IDS, and Claims.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claims 2-7 and 11-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Takahashi et al., US 2019/0394341 A1, in view of the ARMv8 Processor Power Management (ARM Power Management) document listed in the IDS, and further in view of Elwakeel, US 2019/0065973 A1.
Regarding Claim 1, Takahashi discloses a method of managing sleep mode comprising: implementing a SLEEP ON EXIT feature of an ARM processor to enter sleep mode after all interrupts are serviced and no tasks are ready to execute; and disabling the SLEEP ON EXIT feature when a task is determined to be ready to execute [proceeding to sleep if all the jobs are completed; otherwise, continue to execute the jobs (i.e. sleep disabled), Fig. 8].
However, Takahashi does not explicitly teach a real time operating system (RTOS) environment comprising: operating an ARM processor in both handler mode and thread mode.
In the analogous art of ARM processor management, ARM Power Management teaches operating an ARM processor in both handler mode and thread mode [if the SLEEPONEXIT bit of the SCR is set to 1 when the processor completes the execution of all queued exception handlers, it returns to Thread mode and immediately enters into sleep mode (i.e. the system is in handler mode when executing exception handlers, and thread mode when finished), section 1.3.3, pg. 1-12].
It would have been obvious to one of ordinary skill in the art, having the teachings of Takahashi and ARM Power Management before him before the effective filing date of the claimed invention, to incorporate the modes of the processor as taught by ARM Power Management, into the method as disclosed by Takahashi, to provide power savings by only requiring the processor to run when an exception occurs [ARM Power Management, pg. 1-12].
However, the combination of references does not explicitly teach an ARM processor executing in a real time operating system (RTOS) environment.
In the analogous art of ARM processor power management, Elwakeel teaches an ARM processor executing in a real time operating system (RTOS) environment [the ARM Processor runs RTOS to ensure robustness of the firmware and handle very complex tasks, par 139].
It would have been obvious to one of ordinary skill in the art, having the teachings of Takahashi, ARM Power Management, and Elwakeel before him before the effective filing date of the claimed invention, to incorporate running an RTOS as taught by Elwakeel, into the method as disclosed by Takahashi and ARM Power Management, to ensure a robust firmware and execution of complex tasks [Elwakeel, par 139].
Regarding Claim 10, Takahashi discloses a device [image forming apparatus 100, Fig. 2], comprising: a processor; and a memory device in communication with the processor [CPU 101, ROM 102, RAM 103, storage device 110].
The remainder of Claim 10 recites limitations similar to those of Claim 1, and is rejected accordingly.
Claims 8, 9, 17, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Takahashi, ARM Power Management, and Elwakeel, and further in view of Huang et al., US 2007/0162772 A1.
Regarding Claim 8, Takahashi, ARM Power Management, and Elwakeel disclose the method of Claim 1. However, the combination of references does not explicitly teach wherein sleep mode is always entered from handler mode.
In the analogous art of device management, Huang teaches wherein sleep mode is always entered from handler mode [ after the central processing unit executes the interrupt service routine, the chip sends a second control signal to the central processing unit for driving the central processing unit entering a snooping sleep state and enabling the arbiter allowing transmission of the bus master request, then the bus master request is snooped by the central processing unit (i.e. executing the interrupt service routine would necessarily be in the interrupt handler mode, which is when sleep mode is entered), par 10].
It would have been obvious to one of ordinary skill in the art, having the teachings of Takahashi, ARM Power Management, Elwakeel, and Huang before him before the effective filing date of the claimed invention, to incorporate the transition to sleep from handler mode as taught by Huang, into the method as disclosed by Takahashi, ARM Power Management, and Elwakeel, to ensure efficient power consumption [Huang, par 8].
Regarding Claim 9, Takahashi, ARM Power Management, Elwakeel, and Huang disclose the method of Claim 8. Huang further teaches wherein sleep mode is entered form an interrupt service routine [after the central processing unit executes the interrupt service routine, the chip sends a second control signal to the central processing unit for driving the central processing unit entering a snooping sleep state and enabling the arbiter allowing transmission of the bus master request, then the bus master request is snooped by the central processing unit, par 10].
Regarding Claims 17 and 18, Takahashi, ARM Power Management, and Elwakeel disclose the device of Claim 10. Claims 17 and 18 recite limitations similar to those of Claim 8 and 9, respectively, and are rejected accordingly.
Conclusion
Applicant is reminded that in amending a response to a rejection of claims, the patentable novelty must be clearly shown in view of the state of the art disclosed by the references cited and the objections made. Applicant must also show how the amendments avoid such references and objections. See 37 CFR §1.111(c).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL J YEN whose telephone number is (571)270-5047. The examiner can normally be reached M-F 8-5 PT.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew J Jung can be reached at (571) 270-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Paul Yen/Primary Examiner, Art Unit 2175
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