DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
This Office Action responds to reply filed on 12/29/25 regarding application 18/760841 that was initially filed on 7/1/24. Claims 1-20 are pending.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
1. Claims 1 - 6, 8, 10 - 15, 17, 19, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al., US 2016/0353110 A1 (hereinafter Zhang) in view of Shibata et al., US 2006/0233525 A1 (hereinafter Shibata).
As for claim 1, Zhang discloses a method ([0037], e.g., microprocessors and computer-readable medium) for decoding CABAC ([0057], e.g., CABAC) encoded media, comprising: outputting a decoded binary string ([0153], e.g., entropy decodes, note that at the end of the entropy decoding loop, a final binary strings are output) from two or more previously decoded elements ([0153], e.g., entropy decodes, note multiple partially decoded elements) at an end state for a decoding loop; parsing ([0153], e.g., syntax and transform coefficients, note that the parse operation implied) a syntax ([0153], e.g., syntax and transform coefficients, note the syntax elements for the coefficients) of the decoded binary string; and generating a decoded symbol ([0153], e.g., transform coefficients) based on the parsed syntax.
Zhang does not explicitly disclose, but Shibata teaches outputting on a first processing thread ([0088], e.g., a plurality of threads, note a first thread); parsing on a second processing thread ([0088], e.g., a plurality of threads, note a second thread) in parallel ([0088], e.g., in parallel) to the first processing thread, and the first processing thread decoding the binary string independent of the second processing thread; and generating on the second processing thread ([0088], e.g., a plurality of threads, note a second thread).
Therefore, given the teachings as a whole, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the references of Zhang and Shibata before him/her to modify the advanced arithmetic coder of Zhang with the teaching of encoding apparatus and method, and decoding apparatus and method of Shibata with a motivation to improve performance of the application and/or reduce design time due to the benefits of threads such as resource sharing and simple application programming by using different threads for different tasks.
As for claim 2, most of limitations of this claim have been noted in the rejection of Claim 1. In addition, Zhang further discloses determining a next context probability ([0059], e.g., update) for a next encoded binary element independent of generating the decoded symbol including advancing a state ([0057], e.g., state) of a finite state machine ([0058], e.g., state machine and [0061], e.g., 128 states) configured to provide a context for determination of the next context probability based on the decoded binary string.
As for claim 3, most of limitations of this claim have been noted in the rejection of Claim 2. In addition, Zhang further discloses the decoding loop including looking up the next context probability in a lookup table ([0062], e.g., lookup table) using the previously decoded elements and the state of the finite state machine.
As for claim 4, most of limitations of this claim have been noted in the rejection of Claim 1.
Zhang does not explicitly teach, but Shibata teaches running the decoding loop on the first processing thread ([0088], e.g., a plurality of threads, note a first thread).
Therefore, given the teachings as a whole, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the references of Zhang and Shibata before him/her to modify the advanced arithmetic coder of Zhang with the teaching of encoding apparatus and method, and decoding apparatus and method of Shibata with a motivation to improve performance of the application and/or reduce design time due to the benefits of threads such as resource sharing and simple application programming by using different threads for different tasks.
As for claim 5, most of limitations of this claim have been noted in the rejection of Claim 1.
Zhang does not explicitly teach, but Shibata teaches the decoding loop processed on a first processor core ([0088], e.g., cores).
Therefore, given the teachings as a whole, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the references of Zhang and Shibata before him/her to modify the advanced arithmetic coder of Zhang with the teaching of encoding apparatus and method, and decoding apparatus and method of Shibata with a motivation to improve performance of the application and/or reduce design time due to the benefits of threads such as resource sharing and simple application programming by using different threads for different tasks.
As for claim 6, most of limitations of this claim have been noted in the rejection of Claim 5.
Zhang does not explicitly teach, but Shibata teaches the first processing thread is running on the first processing core ([0088], e.g., cores) and the second processing thread is running on a second processor core ([0088], e.g., cores).
Therefore, given the teachings as a whole, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the references of Zhang and Shibata before him/her to modify the advanced arithmetic coder of Zhang with the teaching of encoding apparatus and method, and decoding apparatus and method of Shibata with a motivation to improve performance of the application and/or reduce design time due to the benefits of threads such as resource sharing and simple application programming by using different threads for different tasks.
As for claim 8, most of limitations of this claim have been noted in the rejection of Claim 1. In addition, Zhang further discloses decoding a binary string for encoded discrete cosine transform coefficients ([0153], e.g., transform coefficients), motion vectors or block prediction modes.
As for claim 10, most of limitations of this claim have been noted in the rejection of Claim 1. In addition, Zhang further discloses running a decoding loop including: decoding an encoded element ([0059], e.g., bin n) from a sequence of encoded elements ([0068], e.g., bins) to generate a decoded element using a context probability ([0059], e.g., probability) and determining a next context probability ([0059], e.g., update) for a next encoded element in the sequence from the decoded binary element .
As for claim 11, the claim recites a system for decoding CABAC encoded media of the method of claim 1, and is similarly analyzed.
As for claim 12, the claim recites a system for decoding CABAC encoded media of the method of claim 2, and is similarly analyzed.
As for claim 13, the claim recites a system for decoding CABAC encoded media of the method of claim 3, and is similarly analyzed.
As for claim 14, most of limitations of this claim have been noted in the rejection of Claim 11.
Zhang does not explicitly teach, but Shibata teaches running the decoding loop on the first processing thread ([0088], e.g., a plurality of threads, note a first thread) and running the first processing thread on a first processing core of the processor ([0088], e.g., cores).
Therefore, given the teachings as a whole, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the references of Zhang and Shibata before him/her to modify the advanced arithmetic coder of Zhang with the teaching of encoding apparatus and method, and decoding apparatus and method of Shibata with a motivation to improve performance of the application and/or reduce design time due to the benefits of threads such as resource sharing and simple application programming by using different threads for different tasks.
As for claim 15, most of limitations of this claim have been noted in the rejection of Claim 14.
Zhang does not explicitly teach, but Shibata teaches running the second processing thread on a second processing core of the processor ([0088], e.g., cores).
Therefore, given the teachings as a whole, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the references of Zhang and Shibata before him/her to modify the advanced arithmetic coder of Zhang with the teaching of encoding apparatus and method, and decoding apparatus and method of Shibata with a motivation to improve performance of the application and/or reduce design time due to the benefits of threads such as resource sharing and simple application programming by using different threads for different tasks.
As for claim 17, the claim recites a system for decoding CABAC encoded media of the method of claim 8, and is similarly analyzed.
As for claim 19, most of limitations of this claim have been noted in the rejection of Claim 1. In addition, Zhang further discloses running a decoding loop including: decoding an encoded element ([0059], e.g., bin n) from a sequence of encoded elements ([0068], e.g., bins) to generate a decoded element using a context probability ([0059], e.g., probability) and determining a next context probability ([0059], e.g., update) for a next encoded element in the sequence from the decoded binary element.
As for claim 20, the claim recites a non-transitory computer readable medium having computer readable instruction embodied thereon of the method of claim 1, and is similarly analyzed.
2. Claims 7 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang in view of Shibata, and further in view of Ananthakrishanan et al., US 2020/0272513 A1 (hereinafter Ananthakrishanan).
As for claim 7, most of limitations of this claim have been noted in the rejection of Claim 1.
Zhang as modified by Shibata does not explicitly teach, but Ananthakrishanan teaches the second processing thread is running on a graphics processing unit ([0101], e.g., GPU).
Therefore, given the teachings as a whole, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the references of Zhang, Shibata, and Ananthakrishanan before him/her to modify the advanced arithmetic coder of Zhang with the teaching of thread scheduling using processing engine information of Ananthakrishanan with a motivation to improve performance of the application by using the hareware core in a processor for threads.
As for claim 16, the claim recites a system for decoding CABAC encoded media of the method of claim 7, and is similarly analyzed.
3. Claims 9 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang in view of Shibata, and further in view of Galles, US 2020/0267098 A1 (hereinafter Galles).
As for claim 9, most of limitations of this claim have been noted in the rejection of Claim 1.
Zhang as modified by Shibata does not explicitly teach, but Galles teaches running a plurality syntax parsers in parallel ([0049], e.g., parsers operating in parallel).
Therefore, given the teachings as a whole, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the references of Zhang, Shibata, and Galles before him/her to modify the advanced arithmetic coder of Zhang with the teaching of variable-length packet hearder vectors of Galles with a motivation to increase performance by using the multiple parsers operating at the same time.
As for claim 18, the claim recites a system for decoding CABAC encoded media of the method of claim 9, and is similarly analyzed.
Response to Arguments
Applicant's arguments, filed 12/29/25, have been considered but are moot because the arguments do not apply to any of the citations being used in the current rejection.
Citation of Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
1. US 2003/0108099 discloses picture encoding method and apparatus, picture decoding method and apparatus and furnishing medium.
2. US 2005/0053294 discloses techniques and tools for progressive and interlaced video coding and decoding.
3. US 2006/0126962 discloses methods and systems for reducing blocking artifacts with reduced complexity for spatially-scalable video coding.
Conclusion
Applicant 's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/JOSEPH SUH/
Primary Examiner, Art Unit 2485