Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
2. This office action is in response to communication filed on 07/01/2024. Claims 1-20 are pending on this application.
Claim Objections
3. Claim 8 is objected to because of the following informalities: line 3 of the claim, the subject matter “the digital filter circuit over-samples the output data” should be changed to - - the digital filter circuit over-samples the input data - - as described in Fig. 1 and Fig. 2 of application.
Fig. 1 and Fig. 2 of application described digital filter circuit 124 over-sampling the input data SIDA
Appropriate correction is required.
Claim Rejections - 35 USC § 112
4. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
5. Claims 9, 13 and 19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 9 recites the limitation "the delta" in Claim 1. There is insufficient antecedent basis for this limitation in the claim.
Claim 13 is recites the limitation "the number of bits" in Claim 12. There is insufficient antecedent basis for this limitation in the claim.
Claim 19 is recites the limitation "the number of bits" in Claim 16. There is insufficient antecedent basis for this limitation in the claim
Claim Rejections - 35 USC § 102
6. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
5. Claims 1-3, 7-8, 10, and 16-18 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ramirez U.S. patent No. 5,627,536.
Fig. 4 of Ramirez disclose a delta-sigma ADC 40-4.
Fig. 2 of Ramirez discloses a diagram circuit delta sigma ADC
Regarding claim 1. Fig. 4 of Ramirez discloses an analog-to-digital converter (ADC) circuit (delta-sigma modulator 40-4), comprising: a receiver circuit (10-4) receiving a first analog input (first analog input 504) and a second analog input (second analog input 50-4) and using (using of 10-4) the first analog input (first analog input 50-4) or the second analog input (second analog input 50-4) as an output signal (115-4) according to a control signal (Control Signal); and a delta-sigma ADC (40-4) converting the output signal (42-4) to generate output data (115-4) and comprising: a differential amplifier (50-2 in Fig. 2) amplifying (50-2 in Fig. 2) a difference between the output signal (30-2 in Fig. 2) and a reference signal (60-2 in Fig. 2) to generate an amplified signal (70-2 in Fig. 2); an integrator (80-2 in Fig. 2; Col. 1 lines 56-57) accumulating the amplified signal (output of 50-2 in Fig. 2) to generate an integrated signal (90-2) ; a quantizer (100-2 in Fig. 2) quantizing the integrated signal (90-2 in Fig. 2) to generate input data (110-2 in Fig. 2); a digital-to-analog converter (DAC) circuit (130-2 in Fig. 2) converting the input data (110-2 in Fig. 2) to generate the reference signal (60-2 in Fig. 2); and a digital filter circuit over-sampling (60-4, 90-4, 20-4, 150-4; Col. 4 lines 15-16) the input data (115-4 in Fig. 4 is a 1102 signal in Fig. 2) according to the control signal (Control Signal) to generate the output data (155-4).
Regarding claim 2. The ADC circuit as claimed in claim 1, Fig. 4 further discloses wherein: in response to the control signal (CONTROL SIGNAL) matching a predetermined state (state to select first analog signal 50-4); the receiver circuit (10-4) uses the first analog input (first analog input 50-4) as the output signal (42-4); the digital filter circuit over-samples (60-4, 90-4, 20-4, 150-4; Col. 4 lines 15-16) the input data (115-4) to generate a plurality of first sampled results (first 46-4) and stores the first sampled results (first 46-4) in a first register circuit (first 150-4); and the digital filter circuit (60-4) generates the output data (155-4) according to the first sampled results (first 46-4), in response to the control signal (CONTROL SIGNAL) not matching the predetermined state (state of CONTROL SINGNAL not matching to select first analog signal 50-4) : the receiver circuit (10-4) uses the second analog input (select the second analog input signal 50-2) as the output signal (42-4); the digital filter circuit over-samples (60-4, 90-4, 20-4, 150-4; Col. 4 lines 15-16) the input data (115-4) to generate a plurality of second sampled results (second 46-4) and stores the second sampled results (second 46-4) in a second register circuit (second 150-4) ; and the digital filter circuit (60-4, 90-4, 20-4, 150-4) generates the output data (155-4) according to the second sampled results (second 46-4).
Regarding claim 3. The ADC circuit as claimed in claim 2, Fig. 4 further discloses wherein the second sampled results (second 46-4) are stored in the second register circuit (second 150-4) while the digital filter circuit (60-4, 90-4, 20-4, 150-4) generates the output data (155-4) according to the first sampled results (first 46-4).
Regarding claim 7. The ADC circuit as claimed in claim 1, Fig. 4 further comprising: a first channel receiving the first analog input (first channel of 10-4 for receiving the first analog input 50-4) generated by a first sensing circuit (sensing circuit is inherent to generated first analog input 50-4; because without sensing circuit no analog signal is generated) and providing the first analog input (first analog input 50-4) to the receiver circuit (10-4); a second channel receiving the second analog input (second channel of 10-4 for receiving the second analog input 50-4) generated by a second sensing circuit (sensing circuit is inherent to generated first analog input 50-4; because without sensing circuit no analog signal is generated) and providing the second analog input (second analog input 50-4) to the receiver circuit (10-4) .
Regarding claim 8. The ADC circuit as claimed in claim 7, Fig. 4 further discloses wherein: in response to the receiver circuit (10-4) using the first analog input (first analog input 50-4) as the output signal (42-4), the digital filter circuit over-samples (60-4; Coll 4 lines 15-16) the input data (115-4) to generate a plurality of first sampled results (first 46-4) and stores the first sampled results (first 46-4) in a first register circuit (first 150-4), in response to the receiver circuit (10-4) using the second analog input (second analog input 50-4) as the output signal (42-4), the digital filter circuit over-samples (60-4; Coll 4 lines 15-16) the input data (115-4) to generate a plurality of second sampled results (second 46-4) and stores the second sampled results (46-4) in a second register circuit (second 150-4) , and the first register circuit (first 150-4) is independent of the second register circuit (second 150-4) .
Regarding claim 10. The ADC circuit as claimed in claim 1, further comprising: a control circuit (circuit to generated CONTROL SIGNAL) directing the control signal (CONTROL SIGNAL) to change between a first state (first state of the CONTROL SIGNAL to selection the first analog signal 50-4) and a second state (second state of the CONTROL SIGNAL to selection the second analog signal 50-4).
Regarding claim 16. Fig. 4 of Ramirez discloses a control method for an ADC circuit (40-4), comprising: receiving a first analog input (first analog input 50-4) from a first sensing circuit (first sensing circuit is inherent to generated first analog input signal 50-4; because without sensing circuit no analog signal is generated) receiving a second analog input (second analog input signal 50-4) from a second sensing circuit (first sensing circuit is inherent to generated first analog input signal 50-4; because without sensing circuit no analog signal is generated); using the first analog input (first analog input 50-4) or the second analog input (second analog input 50-4) as an output signal (42-4) according to a control signal (CONROL SIGNAL); converting (delta-sigma modulator 40-4) the output signal (42-4) to generate output data (155-4) , wherein the output signal (42-4) is an analog signal (analog signal of 42-4) , and the output data (155-4) is digital data (155-4 is a digital signal; in response to the first analog input (first analog input 50-4) being used as the output signal (42-4) : over-sampling (Col. 4 lines 15-16) the output signal (42-4) to generate a plurality of first sampled results (first 46-4) ; storing the first sampled results (first 46-4) in a first register circuit (first 150-4) ; generating the output data (155-4) according to the first sampled results (first 46-4); in response to the second analog input (second analog input 50-4) being used as the output signal (42-4): over-sampling (Col. 4 lines 15-16) the output signal (155-4) to generate a plurality of second sampled results (second 46-4) ; storing the second sampled results (second 46-4) in a second register circuit (second 150-4) ; generating the output data (155-4) according to the second sampled results (second 46-4).
Regarding claim 17. The control method as claimed in claim 16, Fig. 4 further discloses wherein the first sampled results (first 46-4) are maintained in the first register circuit (first 150-4) while the second sampled results (second 46-4) are stored in the second register circuit (second 150-4).
Regarding claim 18. The control method as claimed in claim 16, Fig. 4 further discloses wherein the first analog input (first analog input 50-4) and the second analog input (second 50-4) are successively and alternately (multiplexer 10-4) used as the output signal (42-4).
Regarding claim 20. The control method as claimed in claim 16, Fig. 4 further disclose s wherein the step of generating the output data (155-4) according to the first sampled results (first 46-4) comprises: using one of the first sampled results (one of first 46-4) as the output data (155-4).
Claim Rejections - 35 USC § 103
8. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
9. Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Ramirez applied to claim 1 above in view of Amar et al. U.S. patent No. 6,426,713.
Fig. 4 of Ramirez applied to claim 1 above do not discloses programmable gain amplifier coupled between the receiver circuit (10-4) and the delta-sigma ADC (40-4) to amplify the output signal (42-4).
Fig. 1.2 of Amar et al. discloses a programmable gain amplifier (110.2, 110.1) coupled between a receiver circuit (100) and a delta-sigma ADC (120) to amplify (110.2, 110.1) an output signal (output of 100) of the receive circuit (100).
Ramirez and Amar et al. are common subject matter of multi analog channels for delta-sigma ADC; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate Amar et al. into Ramirez for the purpose of low distortion amplifier without large power consumption (Col. 4 lines 66-67 of Amar et al.).
10. Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Ramirez applied to claim 16 above in view of Norsworthy U.S. patent No. 5,420,584.
Ramirez applied to claim 16 above does not disclose wherein the number of bits of output data is less than the number of bits of one of the first sampled results.
Fig. 1 of Norsworthy discloses an analog-to digital converter circuit (90; Col. 38-39) comprising: a number of bits (17 bits) of an output data (output of barrel Shifter 34) is less than a number of bits of one of a first sampled results (20 bits of samples output of Filter 720; Col. 35-40).
Ramirez and Norsworthy are common subject matter of multi analog channels for delta-sigma ADC; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate Norsworthy into Ramirez for the purpose of providing useful in communication systems and equipment employing have the advantage of selecting the most significant bits from a multiple bit sample such that a limited-width bus can be employed without regard to the number of bits of data available. (Col. 7 lines 32-37 of Norsworthy).
Allowable Subject Matter
11. Claim 4 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior arts do not teach: wherein the digital filter circuit comprises: an integrator circuit comprising a plurality of integrators which are connected in series and store both the first sampled results and the second sampled results; a comb filter circuit comprising a plurality of comb filters which are connected in series and store both the first sampled results and the second sampled results; and a frequency reduction circuit coupled between the integrator circuit and the comb filter circuit.
12. Claims 5-6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior arts do not teach: an integrator circuit comprising: a first integrator comprising: a first adder adding the input data and a first register value to generate a first calculation value; a first selector circuit selecting the first calculation value as a first output value or a second output value according to the control signal; a first register storing the first output value; a second register storing the second output value; a second selector circuit selecting the first output value stored in the first register or the second output value stored in the second register as the first register value according to the control signal; a second integrator connected to the first integrator in series and comprising: a second adder adding the first calculation value and a second register value to generate a second calculation value; a third selector circuit selecting the second calculation value as a third output value or a fourth output value according to the control signal; a third register storing the third output value; a fourth register storing the fourth output value; a fourth selector circuit selecting the third output value stored in the third register or the fourth output value stored in the fourth register as the second register value according to the control signal; a frequency reduction circuit down-sampling the second calculation value to generate a processed value; a comb filter circuit comprising: a first comb filter comprising: a first subtractor subtracting a third register value from the processed value to generate a third calculation value; a fifth selector circuit selecting the processed value as a fifth output value or a sixth output value according to the control signal; a fifth register storing the fifth output value; a sixth register storing the sixth output value; a sixth selector circuit selecting the fifth output value stored in the fifth register or the sixth output value stored in the sixth register as the third register value according to the control signal; a second comb filter comprising: a second subtractor subtracting a fourth register value from the third calculation value to generate a fourth calculation value; a seventh selector circuit selecting the third calculation value as a seventh output value or an eighth output value according to the control signal; a seventh register storing the seventh output value; an eighth register storing the eighth output value; an eighth selector circuit selecting the seventh output value stored in the seventh register or the eighth output value stored in the eighth register as the fourth register value according to the control signal.
13. Claims 11-12 and 14-15 are allowed.
With respect to claim 11, in addition to other elements in the claim, prior art considered individual or combination does not teach: a second integrator connected to the first integrator in series and comprising: a second adder adding the first calculation value and a second register value to generate a second calculation value; a third selector circuit selecting the second calculation value as a third output value or a fourth output value according to the control signal; a third register storing the third output value; a fourth register storing the fourth output value; a fourth selector circuit selecting the third output value stored in the third register or the fourth output value stored in the fourth register as the second register value according to the control signal; a frequency reduction circuit down-sampling the second calculation value to generate a processed value; a comb filter circuit comprising: a first comb filter comprising: a first subtractor subtracting a third register value from the processed value to generate a third calculation value; a fifth selector circuit selecting the processed value as a fifth output value or a sixth output value according to the control signal; a fifth register storing the fifth output value; a sixth register storing the sixth output value; a sixth selector circuit selecting the fifth output value stored in the fifth register or the sixth output value stored in the sixth register as the third register value according to the control signal; a second comb filter comprising: a second subtractor subtracting a fourth register value from the third calculation value to generate a fourth calculation value; a seventh selector circuit selecting the third calculation value as a seventh output value or an eighth output value according to the control signal; a seventh register storing the seventh output value; an eighth register storing the eighth output value; an eighth selector circuit selecting the seventh output value stored in the seventh register or the eighth output value stored in the eighth register as the fourth register value according to the control signal.
Contact Information
14. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Linh Van Nguyen whose telephone number is (571) 272-1810. The examiner can normally be reached from 8:30 – 5:00 Monday-Friday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mr. Dameon E. Levi can be reached at (571) 272-2105. The fax phone numbers for the organization where this application or proceeding is assigned are (571-273-8300) for regular communications and (571-273-8300) for After Final communications.
12/19/2025
/LINH V NGUYEN/Primary Examiner, Art Unit 2845