DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/19/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Amendment
Claims 1-20 have been cancelled. Claims 21-39 have been added. Claims 21-39 are currently pending.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 21-24, 26-33, and 35-39 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 2, 10, 13-15, 20, 22, 25, and 28 of U.S. Patent No. 12,026,120. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1, 2, 10, 13-15, 20, 22, 25, and 28 of US Patent 12,026,120 disclose all of the features of claims 21-24, 26-33, and 35-39 of the Instant Application.
As per claims 21-24, 26-33, and 35-39,
Instant Application
US Patent 12,026,120 (US Application 17/845,717)
Claim 21: A die operable to access multiple communication protocols, the die comprising: at least one processing core; a set of serial interconnection lanes; a first communication subsystem including a controller, a protocol coding sublayer (PCS) for interchanging data in a first communication protocol, and a data interface coupled to the at least one core; a second communication subsystem including a controller, a PCS for interchanging data in a second communication protocol, and a data interface coupled to the at least one core; a mode input to select at least one of the first or second communication protocol based on an external device in communication with the set of serial interconnection lanes; and a data router having an input coupled to the PCS of the first communication subsystem and an input coupled to the PCS of the second communication subsystem, an output coupled to the set of serial interconnection lanes, and a selection input coupled to the mode input to allocate at least some of the lanes of the set of serial interconnection lanes for the selected protocol.
Claim 1: A die operable to access multiple communication protocols, the die comprising: at least one processing core; a set of serial interconnection lanes; a first communication subsystem including a first controller, a protocol coding sublayer (PCS) for interchanging data in a first communication protocol, and a data interface coupled to the at least one core; a second communication subsystem including a second controller, a PCS for interchanging data in a second communication protocol, and a data interface coupled to the at least one core; a third communication subsystem including a third controller, a PCS for interchanging data in a third communication protocol, and a data interface coupled the at least one core; a mode input configured to accept a plurality of different mode configurations and to select at least one of the first, second or third communication protocol, wherein a first mode configuration of the plurality of different mode configurations allocates some of the serial interconnection lanes to the data interface of the first subsystem communicating via the first protocol directed by the first controller, wherein the first mode configuration allocates some of the serial interconnection lanes to the data interface of the third communication subsystem communicating via the third protocol directed by the third controller, and wherein the first mode configuration powers down the second controller; and a data router having an input coupled to the PCS of the first communication subsystem and an input coupled to the PCS of the second communication subsystem, an output coupled to the set of serial interconnection lanes, and a selection input coupled to the mode input to allocate at least some of the lanes of the set of serial interconnection lanes for the selected protocol.
Claim 13: The die of claim 1, wherein the selected set of interconnection lanes forms an interface to communicate the data signals of the first or second communication protocols to an external device.
Note: Claim 1 of US Patent 12,026,120 teaches the underlined and italicized limitations of instant claim 1, while claim 13 of US Patent 12,026,120 teaches the bolded limitations of instant claim 1.
Claim 22: The die of claim 21, wherein the serial interconnection lanes are Serializer/Deserializer (SERDES) interconnections, and the first and second communication protocols are one of Interlaken, PCIe, Ethernet, Quick Path Interconnect (QPI), Infiniti Fabric high speed serial connection, NV Link chip to chip communication, or Universal Chiplet Interconnect Express (UCIE) 2.5/3D.
Claim 2: The die of claim 1, wherein the first, second, and third communication protocols are one of Interlaken, PCIe, Ethernet, Quick Path Interconnect (QPI), Infiniti Fabric high speed serial connection, NV Link chip to chip communication, or Universal Chiplet Interconnect Express (UCIE) 2.5/3D.
Claim 23: The die of claim 21, further comprising a third communication subsystem including a controller, a PCS subsystem for exchanging data in a third communication protocol, and a data interface coupled to the at least one core, wherein the mode input is further configured to select the third communication protocol based on the external device in communication with the set of the serial interconnection lanes.
Claim 1: A die operable to access multiple communication protocols, the die comprising: at least one processing core; a set of serial interconnection lanes; a first communication subsystem including a first controller, a protocol coding sublayer (PCS) for interchanging data in a first communication protocol, and a data interface coupled to the at least one core; a second communication subsystem including a second controller, a PCS for interchanging data in a second communication protocol, and a data interface coupled to the at least one core; a third communication subsystem including a third controller, a PCS for interchanging data in a third communication protocol, and a data interface coupled the at least one core; a mode input configured to accept a plurality of different mode configurations and to select at least one of the first, second or third communication protocol, wherein a first mode configuration of the plurality of different mode configurations allocates some of the serial interconnection lanes to the data interface of the first subsystem communicating via the first protocol directed by the first controller, wherein the first mode configuration allocates some of the serial interconnection lanes to the data interface of the third communication subsystem communicating via the third protocol directed by the third controller, and wherein the first mode configuration powers down the second controller; and a data router having an input coupled to the PCS of the first communication subsystem and an input coupled to the PCS of the second communication subsystem, an output coupled to the set of serial interconnection lanes, and a selection input coupled to the mode input to allocate at least some of the lanes of the set of serial interconnection lanes for the selected protocol.
Claim 24: The die of claim 21, wherein the mode interface allows adjustment of variable speeds for data on the serial interconnection lanes based on the external device in communication with the set of the serial interconnection lanes.
Claim 10: The die of claim 1, wherein the first mode configuration selects either a high speed version of the first protocol or a low speed version of the first protocol.
Claim 25: The die of claim 21, wherein the mode interface allows adjustment of variable bandwidths for data on the serial interconnection lanes based on the external device in communication with the set of the serial interconnection lanes.
Claims 1 + 13 do not teach the limitations of claim 25. These limitations are however taught by Remein. See below for combination.
Claim 26: The die of claim 21, further comprising a reach mode input allowing a reach configuration to set the selected PCS of the first communication subsystem or the PCS of the second communication subsystem based on the proximity of the external device in communication with the set of the serial interconnection lanes.
Claim 14: The die of claim 1, further comprising a reach mode input allowing a reach configuration to set the selected PCS of the first communication subsystem or the PCS of the second communication subsystem.
Claim 27: The die of claim 21, wherein the mode input is configured to accept a plurality of different mode configurations of the first and second communication subsystems, and wherein the mode input selects one of the plurality of different mode configurations based on the external device.
Claim 13: The die of claim 1, wherein the selected set of interconnection lanes forms an interface to communicate the data signals of the first or second communication protocols to an external device.
Claim 28: The die of claim 27, wherein a first mode includes a low speed version or a high speed version of the first protocol.
Claim 10: The die of claim 1, wherein the first mode configuration selects either a high speed version of the first protocol or a low speed version of the first protocol.
Claim 29: The die of claim 21, wherein the external device is one of another chip, a peripheral device, or an FPGA.
Claim 13: The die of claim 1, wherein the selected set of interconnection lanes forms an interface to communicate the data signals of the first or second communication protocols to an external device.
Claim 30: A chip having a plurality of dies, each of the dies comprising: at least one processing core; a set of serial interconnection lanes; a first communication subsystem including a controller, a protocol coding sublayer (PCS) for interchanging data in a first communication protocol, and a data interface coupled to the at least one core; a second communication subsystem including a controller, a PCS for interchanging data in a second communication protocol, and a data interface coupled to the at least one core; a mode input to select at least one of the first or second communication protocol based on an external device in communication with the set of serial interconnection lanes; and a data router having an input coupled to the PCS of the first communication subsystem and an input coupled to the PCS of the second communication subsystem, an output coupled to the set of serial interconnection lanes, and a selection input coupled to the mode input to allocate at least some of the lanes of the set of serial interconnection lanes for the selected protocol.
Claim 15: A chip having a plurality of dies, each of the dies comprising: at least one processing core; a set of serial interconnection lanes; a first communication subsystem including a controller, a protocol coding sublayer (PCS) for interchanging data in a first communication protocol, and a data interface coupled to the at least one core; a second communication subsystem including a controller, a PCS for interchanging data in a second communication protocol, and a data interface coupled to the at least one core; a third communication subsystem including a third controller, a PCS for interchanging data in a third communication protocol, and a data interface coupled the at least one core; a mode input configured to accept a plurality of different mode configurations and to select at least one of the first, second or third communication protocol, wherein a first mode configuration of the plurality of different mode configurations allocates some of serial interconnection lanes to the data interface of the first subsystem communicating via the first protocol directed by the first controller and allocates some of the serial interconnection lanes to the data interface of the third communication subsystem communicating via the third communication protocol; and a data router having an input coupled to the PCS of the first communication subsystem and an input coupled to the PCS of the second communication subsystem, an output coupled to the set of serial interconnection lanes, and a selection input coupled to the mode input to allocate at least some of the lanes of the set of serial interconnection lanes for the selected protocol.
Claim 13: The die of claim 1, wherein the selected set of interconnection lanes forms an interface to communicate the data signals of the first or second communication protocols to an external device.
Claim 31: The chip of claim 30, wherein the serial interconnection lanes are Serializer/Deserializer (SERDES) interconnections, and the first and second communication protocols are one of Interlaken, PCIe, Ethernet, Quick Path Interconnect (QPI), Infiniti Fabric high speed serial connection, NV Link chip to chip communication, or Universal Chiplet Interconnect Express (UCIE) 2.5/3D.
Claim 22: The chip of claim 15, wherein the serial interconnection lanes are Serializer/Deserializer (SERDES) interconnections.
Claim 2: The die of claim 1, wherein the first, second, and third communication protocols are one of Interlaken, PCIe, Ethernet, Quick Path Interconnect (QPI), Infiniti Fabric high speed serial connection, NV Link chip to chip communication, or Universal Chiplet Interconnect Express (UCIE) 2.5/3D.
Claim 32: The chip of claim 30, wherein each of the dies further comprise a third communication subsystem including a controller, a PCS subsystem for exchanging data in a third communication protocol, and a data interface coupled to the at least one core, wherein the mode input is further configured to select the third communication protocol based on the external device in communication with the set of the serial interconnection lanes.
Claim 15: A chip having a plurality of dies, each of the dies comprising: at least one processing core; a set of serial interconnection lanes; a first communication subsystem including a controller, a protocol coding sublayer (PCS) for interchanging data in a first communication protocol, and a data interface coupled to the at least one core; a second communication subsystem including a controller, a PCS for interchanging data in a second communication protocol, and a data interface coupled to the at least one core; a third communication subsystem including a third controller, a PCS for interchanging data in a third communication protocol, and a data interface coupled the at least one core; a mode input configured to accept a plurality of different mode configurations and to select at least one of the first, second or third communication protocol, wherein a first mode configuration of the plurality of different mode configurations allocates some of serial interconnection lanes to the data interface of the first subsystem communicating via the first protocol directed by the first controller and allocates some of the serial interconnection lanes to the data interface of the third communication subsystem communicating via the third communication protocol; and a data router having an input coupled to the PCS of the first communication subsystem and an input coupled to the PCS of the second communication subsystem, an output coupled to the set of serial interconnection lanes, and a selection input coupled to the mode input to allocate at least some of the lanes of the set of serial interconnection lanes for the selected protocol.
Claim 33: The chip of claim 30, wherein the mode interface allows adjustment of variable speeds for data on the serial interconnection lanes based on the external device in communication with the set of the serial interconnection lanes.
Claim 25: The chip of claim 15, wherein the first mode configuration selects either a high speed version of the first protocol or a low speed version of the first protocol.
Claim 34: The chip of claim 30, wherein the mode interface allows adjustment of variable bandwidths for data on the serial interconnection lanes based on the external device in communication with the set of the serial interconnection lanes.
Claims 15 + 13 do not teach the limitations of claim 34. These limitations are however taught by Remein. See below for combination.
Claim 35: The chip of claim 30, wherein each of the dies further comprise a reach mode input allowing a reach configuration to set the selected PCS of the first communication subsystem or the PCS of the second communication subsystem based on the proximity of the external device in communication with the set of the serial interconnection lanes.
Claim 28: The chip of claim 15, further comprising a reach mode input allowing a reach configuration to set the selected PCS of the first communication subsystem or the PCS of the second communication subsystem.
Claim 36: The chip of claim 30, wherein the mode input is configured to accept a plurality of different mode configurations of the first and second communication subsystems, and wherein the mode input selects one of the plurality of different mode configurations based on the external device.
Claim 13: The die of claim 1, wherein the selected set of interconnection lanes forms an interface to communicate the data signals of the first or second communication protocols to an external device.
Claim 37: The chip of claim 36, wherein a first mode includes a low speed version or a high speed version of the first protocol.
Claim 25: The chip of claim 15, wherein the first mode configuration selects either a high speed version of the first protocol or a low speed version of the first protocol.
Claim 38: The chip of claim 30, wherein the external device is one of another chip, a peripheral device, or an FPGA.
Claim 13: The die of claim 1, wherein the selected set of interconnection lanes forms an interface to communicate the data signals of the first or second communication protocols to an external device.
Claim 39: A method of allocating a set of serial interconnection lanes on a die having at least one processing core between a first and a second communication protocol, the die including: a first communication subsystem including a controller, a protocol coding sublayer (PCS) for interchanging data in a first communication protocol, and a data interface coupled to the at least one core; a second communication subsystem including a controller, a PCS for interchanging data in a second communication protocol, and a data interface coupled to the at least one core, the method comprising: establishing communication with an external device in communication with the set of serial interconnection lanes; inputting a mode configuration signal selecting from a plurality of different mode configurations to a data router based on the external device, the data router having an input coupled to the PCS of the first communication subsystem, and an input coupled to the PCS of the second communication subsystem, and an output coupled to the set of serial interconnection lanes; allocating at least some of the lanes of the set of serial interconnection lanes for the selected protocol according to a first mode configuration of the plurality of different mode configurations, wherein the first mode configuration allocates some of serial interconnection lanes to the data interface of the first subsystem communicating via the first protocol directed by the first controller or the data interface of the second subsystem communicating via the second protocol directed by the second controller; and exchanging data via either the controller of the first subsystem or the controller of the second subsystem through the allocated lanes of the set of serial interconnection lanes with the processing core.
Claim 20: A method of allocating a set of serial interconnection lanes on a die having at least one processing core between a first, a second, and a third communication protocol, the die including a first communication subsystem including a controller, a protocol coding sublayer (PCS) for interchanging data in a first communication protocol, and a data interface coupled to the at least one core; a second communication subsystem including a controller, a PCS for interchanging data in a second communication protocol, and a data interface coupled to the at least one core, and a third communication subsystem including a controller, a PCS for interchanging data in the third communication protocol, and a data interface coupled to the at least one core, the method comprising: inputting a mode configuration signal selecting from a plurality of different mode configurations to a data router having an input coupled to the PCS of the first communication subsystem, and an input coupled to the PCS of the second communication subsystem, an input coupled to the PCS of the third communication subsystem, and an output coupled to the set of serial interconnection lanes; allocating at least some of the lanes of the set of serial interconnection lanes for the selected protocol according to a first mode configuration of the plurality of different mode configurations, wherein the first mode configuration allocates some of serial interconnection lanes to the data interface of the first subsystem communicating via the first protocol directed by the first controller, and wherein the first mode configuration allocates some of the serial interconnection lanes to the data interface of the third communication subsystem communicating via the third protocol directed by the third controller, and wherein the first mode configuration powers down the second controller; and exchanging data via either the controller of the first subsystem or the controller of the second subsystem or the controller of the third subsystem through the allocated lanes of the set of serial interconnection lanes with the processing core.
Claim 13: The die of claim 1, wherein the selected set of interconnection lanes forms an interface to communicate the data signals of the first or second communication protocols to an external device.
Regarding instant claim 1, claim 1 of US Patent 12,026,120 teaches first and second subsystems with a PCS, controller, first/second communication protocols, and a data interface coupled to a core, a mode input to select at least one of the first or second communication protocol; and a data router coupled to the first and second PCS to select one of the first and second protocols, which claim 1 of the Instant Application also discloses. Claim 1 of US Patent 12,026,120 does not disclose “a mode input to select at least one of the first or second communication protocol based on an external device in communication with the set of serial interconnection lanes” of instant claim 1, however claim 13 of US Patent 12,026,120 which is dependent on claim 1 of US Patent 12,026,120 does teach these limitations.
Independent claim 30 of the Instant Application is similar to claim 1 of Instant Application and thus is rejected under similar rationale over claims 13 and 15 of US Patent 12,026,120. While claim 13 of US Patent 12,026,120 is directed to a chip and claim 15 of US Patent 12,026,120 is directed to a die comprising multiple chips, the chip of claim 13 of US Patent 12,026,120 is part of the same embodiment as the die of claim 15 of US Patent 12,026,120 and it would have been obvious to incorporate selecting a mode of communication of the chip of claim 13 of US Patent 12,026,120 with the die of claim 15 of US Patent 12,026,120 in order to create compatibility with external devices that utilize a wide variety of heterogeneous protocols with considerations to optimal user-defined performance metrics.
Independent claim 39 of the Instant Application is similar to claim 1 of Instant Application and thus is rejected under similar rationale over claims 13 and 20 of US Patent 12,026,120. While claim 13 of US Patent 12,026,120 is directed to a chip and claim 20 of US Patent 12,026,120 is directed towards a method, it would have been obvious that the method of claim 20 of US Patent 12,026,120 would be implemented on a chip in order to have a mass-manufacturable and power/thermal efficient form factor.
Dependent claims 22-24, 26-29, 31-33, and 35-38 of Instant Application are rejected over claims 1, 2, 10, 13-15, 20, 22, 25, and 28 of US Patent 12,026,120. See Table Above.
Claims 25 and 34 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 13, and 15 of U.S. Patent 12,026,120 in view of Remein (US 2017/0070295).
Regarding instant claim 25, instant claim 1 is rejected over claims 1 and 13 of US patent 12,026,120. However, instant claim 25 discloses the die further comprising “wherein the mode interface allows adjustment of variable bandwidths for data on the serial interconnection lanes based on the external device in communication with the set of the serial interconnection lanes”, which claims 1 and 13 of US Patent 12,026,120 does not teach.
The limitations are however known in the art as shown in Remein (US 2017/0070295). Remein teaches the die comprising wherein the mode interface allows adjustment of variable bandwidths for data on the serial interconnection lanes based on the external device in communication with the set of the serial interconnection lanes (Fig. 3, Serial Ethernet PHY 300 performs bandwidth allocation and polling thus adjusting bandwidth based on external device communicating on medium 355; Paragraph 0046, MAC Control 310 protocol may perform bandwidth allocation, bandwidth polling, auto-discovery, ranging, data encapsulation).
It would have been obvious to one of ordinary skill in the art to modify the die of claims 1 + 13 of US Patent 12,026,120 to incorporate the teachings of Remein and enable bandwidth negotiation for communicating to the external device in order to provide sufficient bandwidth for users, thus satisfying user service level objectives and performance metrics (See Remein: Paragraphs 0005 to 0007).
Instant claim 34 is similar to instant claim 25 and thus is rejected under similar rationale by claims 13 + 15 of US Patent 12,026,120 in view of Remein.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 21-24, 27-29, and 39 are rejected under 35 U.S.C. 103 as being unpatentable over Shumarayev (US 7,403,035) in view of Soma (US 11,388,270).
Regarding claim 21, Shumarayev teaches a die (Fig. 4, PLD 10 is an integrated circuit die; Col. 3, Lines 4-7, integrated circuit ("IC") fabrication technology) tends to increase the degree to which transceiver circuit components can be integrated (e.g., placed closer to one another on the PLD) operable to access multiple communication protocols (Col. 6, Lines 35-37, PCS circuitry such as 200/330/350 in FIG. 4 is typically designed to support multiple, commonly employed communication standards or protocols), the die comprising: at least one processing core (Fig. 4, PLD core 90; Col. 6, Line 39, programmable logic array (i.e., PLD core 90)); a set of serial interconnection lanes (Fig. 4, Serializer inputs/outputs serial information via lanes 312 and 328; Col. 4, Lines 57-59, serializer circuitry 324 for converting parallel data to serial form, output driver circuitry 326, and differential serial output pins 328); a first communication subsystem (Fig. 4, CH0 subsystem; Col. 4, Lines 45-47, circuitry 100 includes four channels of actual transceiver circuitry CH0, CH1, CH2, and CH3) including a controller (Fig. 4, CDR 316 controls the clock/data used by the channel; Col. 4, Lines 52-53, clock and data recovery ("CDR") circuitry 316 for recovering clock and data information from the input signal), a protocol coding sublayer (PCS) for interchanging data in a communication protocol (Fig. 4, PCS circuitry 330 supports a protocol; Col. 6, Lines 35-37, PCS circuitry such as 200/330/350 in FIG. 4 is typically designed to support multiple, commonly employed communication standards or protocols), and a data interface coupled to the at least one core (Fig. 4, PCS 330 is coupled to PLD core 90 via a data interface; Col. 4, Lines 65-67, PCS circuitry 330 passes parallel data in either or both directions between the associated PMA transceiver circuitry and PLD core circuitry 90); a second communication subsystem (Fig. 4, CH3 subsystem) including a controller (Fig. 4, CDR of CH3), a PCS for interchanging data in a communication protocol (Fig. 4, PCS 200 supports a protocol; Col. 6, Lines 35-37, PCS circuitry such as 200/330/350 in FIG. 4 is typically designed to support multiple, commonly employed communication standards or protocols), and a data interface coupled to the at least one core (Fig. 4, PCS 200 is coupled to PLD 90 via a data interface); a mode input to select at least one of the communication protocol (Fig. 8, Configuration memory element 622 inputs a signal to mux 620 to control the mux to output PCS signal in the communication protocol; Col. 6, Line 65-Col 7, Line 1, mux 620 is controlled (e.g., by configuration memory element 622 on the PLD) to apply either the output of PLD core 90 or the output of the transmitter side of PCS 330 to serializer 324); and a data router (Fig. 8, Mux 620) having an input coupled to the PCS of the first communication subsystem (Fig. 8, Mux 620 is coupled to PCS 330), an output coupled to the set of serial interconnection lanes (Fig. 8, Mux 620 is coupled to output serial lanes of 324), and a selection input coupled to the mode input to allocate at least some of the lanes of the set of serial interconnection lanes for the selected protocol (Fig. 8, Mux 620 selector input pin (i.e. a selection input) takes in the signal from 622 (i.e. the mode input) which causes the mux 620 to apply the selected lanes for output (i.e. allocate the lanes for output); See Col. 6, Line 65-Col 7, Line 1, mux 620 is controlled (e.g., by configuration memory element 622 on the PLD) to apply either the output of PLD core 90 or the output of the transmitter side of PCS 330 to serializer 324).
Shumarayev does not explicitly teach the die comprising a protocol coding sublayer (PCS) for interchanging data in a first communication protocol; a second communication subsystem including a controller, a PCS for interchanging data in a second communication protocol; a mode input to select at least one of the first or second communication protocol based on an external device in communication with the set of serial interconnection lanes; and a data router having an input coupled to the PCS of the first communication subsystem and an input coupled to the PCS of the second communication subsystem.
Soma teaches the die comprising a protocol coding sublayer (PCS) for interchanging data in a first communication protocol (Fig. 8, PCS circuit 806 uses a first protocol; Col. 18, Lines 23-24, each PCS circuit is configured to implement a different communication protocol); a PCS for interchanging data in a second communication protocol (Fig. 8, PCS circuit 808 uses a second protocol; See Col. 18, Lines 23-24); a mode input (Fig. 8, Control logic 810) to select at least one of the first or second communication protocol (Col. 15, Line 67-Col. 16, Line 3, Control logic 810 is capable of controlling whether PCS circuit 806 or PCS circuit 808 is connected to MGTs 802 via SERDES/Multiplexer 804) based on an external device in communication with the set of serial interconnection lanes (Fig. 1, Medium 106 is the external device and the PHY 100 (i.e. the same as PHY 800 in Figure 8) containing PMD 122 selects the PCS and protocol based on the medium device 106; Col. 4, Lines 53-57, PMD circuit 122 is reconfigured to operate at different data rates in order to determine whether a link partner (e.g., another device to which PHY 100 is connected via medium 106) is compatible with a given communication protocol); and a data router (Fig. 8, Mux 804) having an input coupled to the PCS of the first communication subsystem and an input coupled to the PCS of the second communication subsystem (Fig. 8, Mux 804 is coupled to both PCS circuits 806 and 808; Col. 15, Lines 65-67, SERDES/Multiplexer 804 is coupled to PCS circuits 806 and 808).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have Shumarayev’s die incorporate the teachings of Soma and enable the switches of Shumarayev to switch between different PCS circuits that support different communication protocols.
One of ordinary skill in the art would be motivated to make the modifications in order to increase compatibility with devices that utilize a wide range of protocols while reducing the amount of IC resources required to support the protocols (See Soma: Col. 3, Lines 1-8).
Regarding claim 22, Shumarayev in view of Soma teaches the die of claim 21. Shumarayrev teaches the die comprising wherein the serial interconnection lanes are Serial/Deserializer (SERDES) interconnections (Fig. 4, Serializer inputs/outputs serial information via lanes 312 and 328 which are SERDES through 318/324; Col. 4, Lines 57-59, serializer circuitry 324 for converting parallel data to serial form, output driver circuitry 326, and differential serial output pins 328).
Soma teaches the die comprising wherein the first and second communication protocols are one of Interlaken, PCIe, Ethernet, Quick Path Interconnect (QPI), Infiniti Fabric high speed serial connection, NV Link chip to chip communication, or Universal Chiplet Interconnect Express (UCIE) 2.5/3D (Col. 9, Lines 1-3, PHY architecture described within this disclosure is capable of supporting data rates from 100 Mbps to 25 Gbps Ethernet protocols).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have Shumarayev’s die incorporate the teachings of Soma and enable the switches of Shumarayev to switch between different PCS circuits that support different communication protocols such as Ethernet protocol.
One of ordinary skill in the art would be motivated to make the modifications in order to increase compatibility with devices that utilize a wide range of protocols while reducing the amount of IC resources required to support the protocols (See Soma: Col. 3, Lines 1-8).
Regarding claim 23, Shumarayev in view of Soma teaches the die of claim 21. Shumarayev teaches the die further comprising a third communication subsystem (Fig. 4, CH1 is a third subsystem) including a controller (Fig. 4, CDR of CH1), a PCS subsystem for exchanging data in a communication protocol (Fig. 4, PCS of CH1 uses a protocol to transmit data), and a data interface coupled to the at least one core (Fig. 4, PCS of CH1 is coupled to PLD core 90), wherein the mode input is further configured to select the communication protocol (Fig. 8, Configuration memory element 622 inputs a signal to mux 620 to control the mux to output PCS signal in the communication protocol; Col. 6, Line 65-Col 7, Line 1, mux 620 is controlled (e.g., by configuration memory element 622 on the PLD) to apply either the output of PLD core 90 or the output of the transmitter side of PCS 330 to serializer 324).
Soma teaches the die comprising a PCS subsystem for exchanging data in a third communication protocol (Col. 18, Lines 23-24, each PCS circuit is configured to implement a different communication protocol); wherein the mode input is further configured to select the communication protocol based on the external device in communication with the set of serial interconnection lanes (Fig. 1, Medium 106 is the external device and the PHY 100 (i.e. the same as PHY 800 in Figure 8) containing PMD 122 selects the PCS and protocol based on the medium device 106; Col. 4, Lines 53-57, PMD circuit 122 is reconfigured to operate at different data rates in order to determine whether a link partner (e.g., another device to which PHY 100 is connected via medium 106) is compatible with a given communication protocol).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have Shumarayev/Soma’s die incorporate further teachings of Soma and include a third communication protocol to be used on the third PCS subsystem of Shumarayev.
One of ordinary skill in the art would be motivated to make the modifications in order to increase compatibility with devices that utilize a wide range of protocols while reducing the amount of IC resources required to support the protocols (See Soma: Col. 3, Lines 1-8).
Regarding claim 24, Shumarayev in view of Soma teaches the die of claim 21.
Soma teaches the die comprising wherein the mode interface allows adjustment of variable speeds for data on the serial interconnection lanes based on the external device in communication with the set of the serial interconnection lanes (Fig. 1, Link partner via medium 106 enables the auto-negotiation for the variable speeds; Col. 3 Lines 65-67 to Col. 4, Lines 1-11, PHY 100 is implemented with a parallel detection architecture that is operable over different data rates (e.g., speeds). PHY 100 is capable of performing auto-negotiation supporting different data rates… PHY 100 is referred to as a “local device”. The device with which the local device is attempting to establish an Ethernet communication link is called the “link partner”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have Shumarayev’s die incorporate the teachings of Soma and enable the switches of Shumarayev to switch between different PCS circuits that support different communication protocols with varying speeds.
One of ordinary skill in the art would be motivated to make the modifications in order to increase compatibility with devices that utilize a wide range of protocols while reducing the amount of IC resources required to support the protocols (See Soma: Col. 3, Lines 1-8).
Regarding claim 27, Shumarayev in view of Soma teaches the die of claim 21. Shumarayev teaches the die comprising wherein the mode input is configured to accept a plurality of different mode configurations of the first and second communication subsystems, (Fig. 8, Mode selects a mux to output data in different modes; Col. 6, Line 65-Col 7, Line 1, mux 620 is controlled (e.g., by configuration memory element 622 on the PLD) to apply either the output of PLD core 90 or the output of the transmitter side of PCS 330 to serializer 324).
Soma teaches the die comprising wherein the mode input selects one of the plurality of different mode configurations based on the external device (Fig. 1, Link partner via medium 106 enables the auto-negotiation for the variable speeds; Col. 3 Lines 65-67 to Col. 4, Lines 1-11, PHY 100 is implemented with a parallel detection architecture that is operable over different data rates (e.g., speeds). PHY 100 is capable of performing auto-negotiation supporting different data rates… PHY 100 is referred to as a “local device”. The device with which the local device is attempting to establish an Ethernet communication link is called the “link partner”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have Shumarayev’s die incorporate the teachings of Soma and enable the switches of Shumarayev to switch between different PCS circuits that support different communication protocols with varying speeds.
One of ordinary skill in the art would be motivated to make the modifications in order to increase compatibility with devices that utilize a wide range of protocols while reducing the amount of IC resources required to support the protocols (See Soma: Col. 3, Lines 1-8).
Regarding claim 28, Shumarayev in view of Soma teaches the die of claim 27. Shumarayev teaches the die comprising wherein a first mode includes a low speed version or a high speed version of the first protocol (Col. 4, Lines 37-39, Transceiver circuitry 100 is typically used to send and/or receive one or more high-speed serial data signals).
Regarding claim 29, Shumarayev in view of Soma teaches the die of claim 21.
Soma teaches the die comprising wherein the external device is one of another chip, a peripheral device, or an FPGA (Fig. 1, Link partner 106 includes an Ethernet partner device which has a chip; Col. 11, Lines 50-53, link partner may be a legacy 10BASE-KR, 25GBASE-CR/CR-S, or 25GBASE-KR/KR—S type of device with such a PHY that supports CL73 auto-negotiation and parallel detection).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have Shumarayev/Soma’s die incorporate further teachings of Soma and include an Ethernet external link partner with a chip.
One of ordinary skill in the art would be motivated to make the modifications in order to increase compatibility with devices that utilize a wide range of protocols while reducing the amount of IC resources required to support the protocols (See Soma: Col. 3, Lines 1-8).
Regarding claim 39, Shumarayev teaches a method of allocating a set of serial interconnection lanes (Fig. 4, Serializer outputs serial information via lanes 328; Col. 4, Lines 57-59, serializer circuitry 324 for converting parallel data to serial form, output driver circuitry 326, and differential serial output pins 328) on a die (Fig. 4, PLD 10 is an integrated circuit die; Col. 3, Lines 4-7, integrated circuit ("IC") fabrication technology) tends to increase the degree to which transceiver circuit components can be integrated (e.g., placed closer to one another on the PLD) heaving at least one processing core (Fig. 4, PLD core 90; Col. 6, Line 39, programmable logic array (i.e., PLD core 90)) between communication protocol (Col. 6, Lines 35-37, PCS circuitry such as 200/330/350 in FIG. 4 is typically designed to support multiple, commonly employed communication standards or protocols), the die including a first communication subsystem (Fig. 4, CH0 subsystem; Col. 4, Lines 45-47, circuitry 100 includes four channels of actual transceiver circuitry CH0, CH1, CH2, and CH3) including a controller (Fig. 4, CDR 316 controls the clock/data used by the channel; Col. 4, Lines 52-53, clock and data recovery ("CDR") circuitry 316 for recovering clock and data information from the input signal), a protocol coding sublayer (PCS) for interchanging data in a communication protocol (Fig. 4, PCS circuitry 330 supports a protocol; Col. 6, Lines 35-37, PCS circuitry such as 200/330/350 in FIG. 4 is typically designed to support multiple, commonly employed communication standards or protocols), and a data interface coupled to the at least one core (Fig. 4, PCS 330 is coupled to PLD core 90 via a data interface; Col. 4, Lines 65-67, PCS circuitry 330 passes parallel data in either or both directions between the associated PMA transceiver circuitry and PLD core circuitry 90); and a second communication subsystem (Fig. 4, CH3 subsystem) including a controller (Fig. 4, CDR of CH3), a PCS for interchanging data in a communication protocol (Fig. 4, PCS 200 supports a protocol; Col. 6, Lines 35-37, PCS circuitry such as 200/330/350 in FIG. 4 is typically designed to support multiple, commonly employed communication standards or protocols), and a data interface coupled to the at least one core (Fig. 4, PCS 200 is coupled to PLD 90 via a data interface); the method comprising: inputting a mode configuration signal (Fig. 8, Configuration memory element 622 inputs a signal to mux 620 to control the mux to output PCS signal in the communication protocol; Col. 6, Line 65-Col 7, Line 1, mux 620 is controlled (e.g., by configuration memory element 622 on the PLD) to apply either the output of PLD core 90 or the output of the transmitter side of PCS 330 to serializer 324) to a data router(Fig. 8, Mux 620) having an input coupled to the PCS of the first communication subsystem (Fig. 8, Mux 620 is coupled to PCS 330), and an output coupled to the set of serial interconnection lanes (Fig. 8, Mux 620 is coupled to output serial lanes of 324), allocating at least some of the lanes of the set of serial interconnection lanes for the selected protocol (Fig. 8, Mux 620 input pin takes in the signal from 622; See Col. 6, Line 65-Col 7, Line 1); and exchanging data via either the controller of the first subsystem or the controller of the second subsystem through the allocated lanes of the set of serial interconnection lanes with the processing core (Fig. 4, CDR is used to exchange data via the allocated serial lanes).
Shumarayev does not explicitly teach the method comprising a protocol coding sublayer (PCS) for interchanging data in a first communication protocol; a second communication subsystem including a controller, a PCS for interchanging data in a second communication protocol; inputting a mode configuration signal to a data router based on the external device, the data router having an input coupled to the PCS of the first communication subsystem and an input coupled to the PCS of the second communication subsystem.
Soma teaches the method comprising first and second communication protocols (Col. 18, Lines 23-24, each PCS circuit is configured to implement a different communication protocol); a protocol coding sublayer (PCS) for interchanging data in a first communication protocol (Fig. 8, PCS circuit 806 uses a first protocol); a PCS for interchanging data in a second communication protocol (Fig. 8, PCS circuit 808 uses a second protocol); inputting a mode configuration signal (Col. 15, Line 67-Col. 16, Line 3, Control logic 810 is capable of controlling whether PCS circuit 806 or PCS circuit 808 is connected to MGTs 802 via SERDES/Multiplexer 804) to a data router (Fig. 8, Mux 804) based on the external device (Fig. 1, Medium 106 is the external device and the PHY 100 (i.e. the same as PHY 800 in Figure 8) containing PMD 122 selects the PCS and protocol based on the medium device 106; Col. 4, Lines 53-57, PMD circuit 122 is reconfigured to operate at different data rates in order to determine whether a link partner (e.g., another device to which PHY 100 is connected via medium 106