DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Claims 21, 30, and 39 have been amended. Claims 21-39 are currently pending.
Response to Arguments
Applicant’s arguments, see Applicant’s Remarks, filed 04/03/2026, with respect to newly amended claims 21, 30, and 39 have been fully considered and are persuasive. The 35 U.S.C. 103 rejection of claims 21-39 has been withdrawn.
The Examiner notes the applicant’s requests that the Double Patenting rejections be held in abeyance response. However, “A complete response to a nonstatutory double patenting (NSDP) rejection is either a reply by applicant showing that the claims subject to the rejection are patentably distinct from the reference claims or the filing of a terminal disclaimer in accordance with 37 CFR 1.321 in the pending application(s) with a reply to the Office action (see MPEP § 1490 for a discussion of terminal disclaimers). Such a response is required even when the nonstatutory double patenting rejection is provisional.” (MPEP 804)
See Double Patenting Rejection Below.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 21-24, 26-33, and 35-39 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 2, 10, 13-15, 20, 22, 25, and 28 of U.S. Patent No. 12,026,120. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1, 2, 10, 13-15, 20, 22, 25, and 28 of US Patent 12,026,120 disclose all of the features of claims 21-24, 26-33, and 35-39 of the Instant Application.
As per claims 21-24, 26-33, and 35-39,
Instant Application
US Patent 12,026,120 (US Application 17/845,717)
Claim 21: A die operable to access multiple communication protocols, the die comprising: at least one processing core; a set of serial interconnection lanes; a first communication subsystem including a controller, a protocol coding sublayer (PCS) for interchanging data in a first communication protocol, and a data interface coupled to the at least one core; a second communication subsystem including a controller, a PCS for interchanging data in a second communication protocol, and a data interface coupled to the at least one core; a mode input to select at least one of the first or second communication protocol based on an external device in communication with the set of serial interconnection lanes, wherein the mode input is configured to receive an external mode configuration signal identifying a type of the external device and specifying a selected communication protocol for the type of the external device; and a data router having an input coupled to the PCS of the first communication subsystem and an input coupled to the PCS of the second communication subsystem, an output coupled to the set of serial interconnection lanes, and a selection input coupled to the mode input to allocate at least some of the lanes of the set of serial interconnection lanes for the selected protocol.
Claim 1: A die operable to access multiple communication protocols, the die comprising: at least one processing core; a set of serial interconnection lanes; a first communication subsystem including a first controller, a protocol coding sublayer (PCS) for interchanging data in a first communication protocol, and a data interface coupled to the at least one core; a second communication subsystem including a second controller, a PCS for interchanging data in a second communication protocol, and a data interface coupled to the at least one core; a third communication subsystem including a third controller, a PCS for interchanging data in a third communication protocol, and a data interface coupled the at least one core; a mode input configured to accept a plurality of different mode configurations and to select at least one of the first, second or third communication protocol, wherein a first mode configuration of the plurality of different mode configurations allocates some of the serial interconnection lanes to the data interface of the first subsystem communicating via the first protocol directed by the first controller, wherein the first mode configuration allocates some of the serial interconnection lanes to the data interface of the third communication subsystem communicating via the third protocol directed by the third controller, and wherein the first mode configuration powers down the second controller; and a data router having an input coupled to the PCS of the first communication subsystem and an input coupled to the PCS of the second communication subsystem, an output coupled to the set of serial interconnection lanes, and a selection input coupled to the mode input to allocate at least some of the lanes of the set of serial interconnection lanes for the selected protocol.
Claim 13: The die of claim 1, wherein the selected set of interconnection lanes forms an interface to communicate the data signals of the first or second communication protocols to an external device.
Note: Claim 1 of US Patent 12,026,120 teaches the underlined and italicized limitations of instant claim 1, while claim 13 of US Patent 12,026,120 teaches the bolded limitations of instant claim 1.
Claim 22: The die of claim 21, wherein the serial interconnection lanes are Serializer/Deserializer (SERDES) interconnections, and the first and second communication protocols are one of Interlaken, PCIe, Ethernet, Quick Path Interconnect (QPI), Infiniti Fabric high speed serial connection, NV Link chip to chip communication, or Universal Chiplet Interconnect Express (UCIE) 2.5/3D.
Claim 2: The die of claim 1, wherein the first, second, and third communication protocols are one of Interlaken, PCIe, Ethernet, Quick Path Interconnect (QPI), Infiniti Fabric high speed serial connection, NV Link chip to chip communication, or Universal Chiplet Interconnect Express (UCIE) 2.5/3D.
Claim 23: The die of claim 21, further comprising a third communication subsystem including a controller, a PCS subsystem for exchanging data in a third communication protocol, and a data interface coupled to the at least one core, wherein the mode input is further configured to select the third communication protocol based on the external device in communication with the set of the serial interconnection lanes.
Claim 1: A die operable to access multiple communication protocols, the die comprising: at least one processing core; a set of serial interconnection lanes; a first communication subsystem including a first controller, a protocol coding sublayer (PCS) for interchanging data in a first communication protocol, and a data interface coupled to the at least one core; a second communication subsystem including a second controller, a PCS for interchanging data in a second communication protocol, and a data interface coupled to the at least one core; a third communication subsystem including a third controller, a PCS for interchanging data in a third communication protocol, and a data interface coupled the at least one core; a mode input configured to accept a plurality of different mode configurations and to select at least one of the first, second or third communication protocol, wherein a first mode configuration of the plurality of different mode configurations allocates some of the serial interconnection lanes to the data interface of the first subsystem communicating via the first protocol directed by the first controller, wherein the first mode configuration allocates some of the serial interconnection lanes to the data interface of the third communication subsystem communicating via the third protocol directed by the third controller, and wherein the first mode configuration powers down the second controller; and a data router having an input coupled to the PCS of the first communication subsystem and an input coupled to the PCS of the second communication subsystem, an output coupled to the set of serial interconnection lanes, and a selection input coupled to the mode input to allocate at least some of the lanes of the set of serial interconnection lanes for the selected protocol.
Claim 24: The die of claim 21, wherein the mode interface allows adjustment of variable speeds for data on the serial interconnection lanes based on the external device in communication with the set of the serial interconnection lanes.
Claim 10: The die of claim 1, wherein the first mode configuration selects either a high speed version of the first protocol or a low speed version of the first protocol.
Claim 25: The die of claim 21, wherein the mode interface allows adjustment of variable bandwidths for data on the serial interconnection lanes based on the external device in communication with the set of the serial interconnection lanes.
Claims 1 + 13 do not teach the limitations of claim 25. These limitations are however taught by Remein. See below for combination.
Claim 26: The die of claim 21, further comprising a reach mode input allowing a reach configuration to set the selected PCS of the first communication subsystem or the PCS of the second communication subsystem based on the proximity of the external device in communication with the set of the serial interconnection lanes.
Claim 14: The die of claim 1, further comprising a reach mode input allowing a reach configuration to set the selected PCS of the first communication subsystem or the PCS of the second communication subsystem.
Claim 27: The die of claim 21, wherein the mode input is configured to accept a plurality of different mode configurations of the first and second communication subsystems, and wherein the mode input selects one of the plurality of different mode configurations based on the external device.
Claim 13: The die of claim 1, wherein the selected set of interconnection lanes forms an interface to communicate the data signals of the first or second communication protocols to an external device.
Claim 28: The die of claim 27, wherein a first mode includes a low speed version or a high speed version of the first protocol.
Claim 10: The die of claim 1, wherein the first mode configuration selects either a high speed version of the first protocol or a low speed version of the first protocol.
Claim 29: The die of claim 21, wherein the external device is one of another chip, a peripheral device, or an FPGA.
Claim 13: The die of claim 1, wherein the selected set of interconnection lanes forms an interface to communicate the data signals of the first or second communication protocols to an external device.
Claim 30: A chip having a plurality of dies, each of the dies comprising: at least one processing core; a set of serial interconnection lanes; a first communication subsystem including a controller, a protocol coding sublayer (PCS) for interchanging data in a first communication protocol, and a data interface coupled to the at least one core; a second communication subsystem including a controller, a PCS for interchanging data in a second communication protocol, and a data interface coupled to the at least one core; a mode input to select at least one of the first or second communication protocol based on an external device in communication with the set of serial interconnection lanes, wherein the mode input is configured to receive an external mode configuration signal identifying a type of the external device and specifying a selected communication protocol for the type of the external device; and a data router having an input coupled to the PCS of the first communication subsystem and an input coupled to the PCS of the second communication subsystem, an output coupled to the set of serial interconnection lanes, and a selection input coupled to the mode input to allocate at least some of the lanes of the set of serial interconnection lanes for the selected protocol.
Claim 15: A chip having a plurality of dies, each of the dies comprising: at least one processing core; a set of serial interconnection lanes; a first communication subsystem including a controller, a protocol coding sublayer (PCS) for interchanging data in a first communication protocol, and a data interface coupled to the at least one core; a second communication subsystem including a controller, a PCS for interchanging data in a second communication protocol, and a data interface coupled to the at least one core; a third communication subsystem including a third controller, a PCS for interchanging data in a third communication protocol, and a data interface coupled the at least one core; a mode input configured to accept a plurality of different mode configurations and to select at least one of the first, second or third communication protocol, wherein a first mode configuration of the plurality of different mode configurations allocates some of serial interconnection lanes to the data interface of the first subsystem communicating via the first protocol directed by the first controller and allocates some of the serial interconnection lanes to the data interface of the third communication subsystem communicating via the third communication protocol; and a data router having an input coupled to the PCS of the first communication subsystem and an input coupled to the PCS of the second communication subsystem, an output coupled to the set of serial interconnection lanes, and a selection input coupled to the mode input to allocate at least some of the lanes of the set of serial interconnection lanes for the selected protocol.
Claim 13: The die of claim 1, wherein the selected set of interconnection lanes forms an interface to communicate the data signals of the first or second communication protocols to an external device.
Claim 31: The chip of claim 30, wherein the serial interconnection lanes are Serializer/Deserializer (SERDES) interconnections, and the first and second communication protocols are one of Interlaken, PCIe, Ethernet, Quick Path Interconnect (QPI), Infiniti Fabric high speed serial connection, NV Link chip to chip communication, or Universal Chiplet Interconnect Express (UCIE) 2.5/3D.
Claim 22: The chip of claim 15, wherein the serial interconnection lanes are Serializer/Deserializer (SERDES) interconnections.
Claim 2: The die of claim 1, wherein the first, second, and third communication protocols are one of Interlaken, PCIe, Ethernet, Quick Path Interconnect (QPI), Infiniti Fabric high speed serial connection, NV Link chip to chip communication, or Universal Chiplet Interconnect Express (UCIE) 2.5/3D.
Claim 32: The chip of claim 30, wherein each of the dies further comprise a third communication subsystem including a controller, a PCS subsystem for exchanging data in a third communication protocol, and a data interface coupled to the at least one core, wherein the mode input is further configured to select the third communication protocol based on the external device in communication with the set of the serial interconnection lanes.
Claim 15: A chip having a plurality of dies, each of the dies comprising: at least one processing core; a set of serial interconnection lanes; a first communication subsystem including a controller, a protocol coding sublayer (PCS) for interchanging data in a first communication protocol, and a data interface coupled to the at least one core; a second communication subsystem including a controller, a PCS for interchanging data in a second communication protocol, and a data interface coupled to the at least one core; a third communication subsystem including a third controller, a PCS for interchanging data in a third communication protocol, and a data interface coupled the at least one core; a mode input configured to accept a plurality of different mode configurations and to select at least one of the first, second or third communication protocol, wherein a first mode configuration of the plurality of different mode configurations allocates some of serial interconnection lanes to the data interface of the first subsystem communicating via the first protocol directed by the first controller and allocates some of the serial interconnection lanes to the data interface of the third communication subsystem communicating via the third communication protocol; and a data router having an input coupled to the PCS of the first communication subsystem and an input coupled to the PCS of the second communication subsystem, an output coupled to the set of serial interconnection lanes, and a selection input coupled to the mode input to allocate at least some of the lanes of the set of serial interconnection lanes for the selected protocol.
Claim 33: The chip of claim 30, wherein the mode interface allows adjustment of variable speeds for data on the serial interconnection lanes based on the external device in communication with the set of the serial interconnection lanes.
Claim 25: The chip of claim 15, wherein the first mode configuration selects either a high speed version of the first protocol or a low speed version of the first protocol.
Claim 34: The chip of claim 30, wherein the mode interface allows adjustment of variable bandwidths for data on the serial interconnection lanes based on the external device in communication with the set of the serial interconnection lanes.
Claims 15 + 13 do not teach the limitations of claim 34. These limitations are however taught by Remein. See below for combination.
Claim 35: The chip of claim 30, wherein each of the dies further comprise a reach mode input allowing a reach configuration to set the selected PCS of the first communication subsystem or the PCS of the second communication subsystem based on the proximity of the external device in communication with the set of the serial interconnection lanes.
Claim 28: The chip of claim 15, further comprising a reach mode input allowing a reach configuration to set the selected PCS of the first communication subsystem or the PCS of the second communication subsystem.
Claim 36: The chip of claim 30, wherein the mode input is configured to accept a plurality of different mode configurations of the first and second communication subsystems, and wherein the mode input selects one of the plurality of different mode configurations based on the external device.
Claim 13: The die of claim 1, wherein the selected set of interconnection lanes forms an interface to communicate the data signals of the first or second communication protocols to an external device.
Claim 37: The chip of claim 36, wherein a first mode includes a low speed version or a high speed version of the first protocol.
Claim 25: The chip of claim 15, wherein the first mode configuration selects either a high speed version of the first protocol or a low speed version of the first protocol.
Claim 38: The chip of claim 30, wherein the external device is one of another chip, a peripheral device, or an FPGA.
Claim 13: The die of claim 1, wherein the selected set of interconnection lanes forms an interface to communicate the data signals of the first or second communication protocols to an external device.
Claim 39: A method of allocating a set of serial interconnection lanes on a die having at least one processing core between a first and a second communication protocol, the die including: a first communication subsystem including a controller, a protocol coding sublayer (PCS) for interchanging data in a first communication protocol, and a data interface coupled to the at least one core; a second communication subsystem including a controller, a PCS for interchanging data in a second communication protocol, and a data interface coupled to the at least one core, the method comprising: establishing communication with an external device in communication with the set of serial interconnection lanes; receiving, at the mode input, a mode configuration signal from an external source, the mode configuration signal identifying a type of the external device and specifying a selected communication protocol from a plurality of different mode configurations; inputting a mode configuration signal selecting from a plurality of different mode configurations to a data router based on the external device, the data router having an input coupled to the PCS of the first communication subsystem, and an input coupled to the PCS of the second communication subsystem, and an output coupled to the set of serial interconnection lanes; allocating at least some of the lanes of the set of serial interconnection lanes for the selected protocol according to a first mode configuration of the plurality of different mode configurations, wherein the first mode configuration allocates some of serial interconnection lanes to the data interface of the first subsystem communicating via the first protocol directed by the first controller or the data interface of the second subsystem communicating via the second protocol directed by the second controller; and exchanging data via either the controller of the first subsystem or the controller of the second subsystem through the allocated lanes of the set of serial interconnection lanes with the processing core.
Claim 20: A method of allocating a set of serial interconnection lanes on a die having at least one processing core between a first, a second, and a third communication protocol, the die including a first communication subsystem including a controller, a protocol coding sublayer (PCS) for interchanging data in a first communication protocol, and a data interface coupled to the at least one core; a second communication subsystem including a controller, a PCS for interchanging data in a second communication protocol, and a data interface coupled to the at least one core, and a third communication subsystem including a controller, a PCS for interchanging data in the third communication protocol, and a data interface coupled to the at least one core, the method comprising: inputting a mode configuration signal selecting from a plurality of different mode configurations to a data router having an input coupled to the PCS of the first communication subsystem, and an input coupled to the PCS of the second communication subsystem, an input coupled to the PCS of the third communication subsystem, and an output coupled to the set of serial interconnection lanes; allocating at least some of the lanes of the set of serial interconnection lanes for the selected protocol according to a first mode configuration of the plurality of different mode configurations, wherein the first mode configuration allocates some of serial interconnection lanes to the data interface of the first subsystem communicating via the first protocol directed by the first controller, and wherein the first mode configuration allocates some of the serial interconnection lanes to the data interface of the third communication subsystem communicating via the third protocol directed by the third controller, and wherein the first mode configuration powers down the second controller; and exchanging data via either the controller of the first subsystem or the controller of the second subsystem or the controller of the third subsystem through the allocated lanes of the set of serial interconnection lanes with the processing core.
Claim 13: The die of claim 1, wherein the selected set of interconnection lanes forms an interface to communicate the data signals of the first or second communication protocols to an external device.
Regarding instant claim 1, claim 1 of US Patent 12,026,120 teaches first and second subsystems with a PCS, controller, first/second communication protocols, and a data interface coupled to a core, a mode input to select at least one of the first or second communication protocol; and a data router coupled to the first and second PCS to select one of the first and second protocols, which claim 1 of the Instant Application also discloses. Claim 1 of US Patent 12,026,120 does not disclose “a mode input to select at least one of the first or second communication protocol based on an external device in communication with the set of serial interconnection lanes, wherein the mode input is configured to receive an external mode configuration signal identifying a type of the external device and specifying a selected communication protocol for the type of the external device” of instant claim 1, however claim 13 of US Patent 12,026,120 which is dependent on claim 1 of US Patent 12,026,120 teaches receiving external data signals from an external device and allocating interconnection lanes based on first and second protocols. It would have been obvious to combine claim 13 of US Patent 12,026,120 with claim 1 of US Patent 12,026,120 and include selecting the first and second protocol based on signals to the mode input indicating the type of data signals used by the external device in order to yield the obvious result of creating compatibility with a wide-range of heterogeneous peripheral devices without having to implement multiple interfaces dedicated to only a single protocol, thus reducing manufacturing and design costs.
Independent claim 30 of the Instant Application is similar to claim 1 of Instant Application and thus is rejected under similar rationale over claims 13 and 15 of US Patent 12,026,120. While claim 13 of US Patent 12,026,120 is directed to a chip and claim 15 of US Patent 12,026,120 is directed to a die comprising multiple chips, the chip of claim 13 of US Patent 12,026,120 is part of the same embodiment as the die of claim 15 of US Patent 12,026,120 and it would have been obvious to incorporate selecting a mode of communication of the chip of claim 13 of US Patent 12,026,120 with the die of claim 15 of US Patent 12,026,120 in order to create compatibility with external devices that utilize a wide variety of heterogeneous protocols with considerations to optimal user-defined performance metrics.
Independent claim 39 of the Instant Application is similar to claim 1 of Instant Application and thus is rejected under similar rationale over claims 13 and 20 of US Patent 12,026,120. While claim 13 of US Patent 12,026,120 is directed to a chip and claim 20 of US Patent 12,026,120 is directed towards a method, it would have been obvious that the method of claim 20 of US Patent 12,026,120 would be implemented on a chip in order to have a mass-manufacturable and power/thermal efficient form factor.
Dependent claims 22-24, 26-29, 31-33, and 35-38 of Instant Application are rejected over claims 1, 2, 10, 13-15, 20, 22, 25, and 28 of US Patent 12,026,120. See Table Above.
Claims 25 and 34 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 13, and 15 of U.S. Patent 12,026,120 in view of Remein (US 2017/0070295).
Regarding instant claim 25, instant claim 1 is rejected over claims 1 and 13 of US patent 12,026,120. However, instant claim 25 discloses the die further comprising “wherein the mode interface allows adjustment of variable bandwidths for data on the serial interconnection lanes based on the external device in communication with the set of the serial interconnection lanes”, which claims 1 and 13 of US Patent 12,026,120 does not teach.
The limitations are however known in the art as shown in Remein (US 2017/0070295). Remein teaches the die comprising wherein the mode interface allows adjustment of variable bandwidths for data on the serial interconnection lanes based on the external device in communication with the set of the serial interconnection lanes (Fig. 3, Serial Ethernet PHY 300 performs bandwidth allocation and polling thus adjusting bandwidth based on external device communicating on medium 355; Paragraph 0046, MAC Control 310 protocol may perform bandwidth allocation, bandwidth polling, auto-discovery, ranging, data encapsulation).
It would have been obvious to one of ordinary skill in the art to modify the die of claims 1 + 13 of US Patent 12,026,120 to incorporate the teachings of Remein and enable bandwidth negotiation for communicating to the external device in order to provide sufficient bandwidth for users, thus satisfying user service level objectives and performance metrics (See Remein: Paragraphs 0005 to 0007).
Instant claim 34 is similar to instant claim 25 and thus is rejected under similar rationale by claims 13 + 15 of US Patent 12,026,120 in view of Remein.
Allowable Subject Matter
Claims 21-39 would be allowable if rewritten or amended to overcome the rejections under Double Patenting, set forth in this Office action.
The following is a statement of reasons for the indication of allowable subject matter: Regarding claim 21, none of the cited references either alone or in combination teaches a die operable to access multiple communication protocols, the die comprising: at least one processing core; a set of serial interconnection lanes; a first communication subsystem including a controller, a protocol coding sublayer (PCS) for interchanging data in a first communication protocol, and a data interface coupled to the at least one core; a second communication subsystem including a controller, a PCS for interchanging data in a second communication protocol, and a data interface coupled to the at least one core; a mode input to select at least one of the first or second communication protocol based on an external device in communication with the set of serial interconnection lanes, wherein the mode input is configured to receive an external mode configuration signal identifying a type of the external device and specifying a selected communication protocol for the type of the external device; and a data router having an input coupled to the PCS of the first communication subsystem and an input coupled to the PCS of the second communication subsystem, an output coupled to the set of serial interconnection lanes, and a selection input coupled to the mode input to allocate at least some of the lanes of the set of serial interconnection lanes for the selected protocol.
Regarding claim 30, a chip having a plurality of dies, each of the dies comprising: at least one processing core; a set of serial interconnection lanes; a first communication subsystem including a controller, a protocol coding sublayer (PCS) for interchanging data in a first communication protocol, and a data interface coupled to the at least one core; a second communication subsystem including a controller, a PCS for interchanging data in a second communication protocol, and a data interface coupled to the at least one core; a mode input to select at least one of the first or second communication protocol based on an external device in communication with the set of serial interconnection lanes, wherein the mode input is configured to receive an external mode configuration signal identifying a type of the external device and specifying a selected communication protocol for the type of the external device; and a data router having an input coupled to the PCS of the first communication subsystem and an input coupled to the PCS of the second communication subsystem, an output coupled to the set of serial interconnection lanes, and a selection input coupled to the mode input to allocate at least some of the lanes of the set of serial interconnection lanes for the selected protocol.
Regarding claim 39, none of the cited references either alone or in combination teaches a method of allocating a set of serial interconnection lanes on a die having at least one processing core between a first and a second communication protocol, the die including: a first communication subsystem including a controller, a protocol coding sublayer (PCS) for interchanging data in a first communication protocol, and a data interface coupled to the at least one core; a second communication subsystem including a controller, a PCS for interchanging data in a second communication protocol, and a data interface coupled to the at least one core, the method comprising: establishing communication with an external device in communication with the set of serial interconnection lanes; receiving, at the mode input, a mode configuration signal from an external source, the mode configuration signal identifying a type of the external device and specifying a selected communication protocol from a plurality of different mode configurations; inputting a mode configuration signal selecting from a plurality of different mode configurations to a data router based on the external device, the data router having an input coupled to the PCS of the first communication subsystem, and an input coupled to the PCS of the second communication subsystem, and an output coupled to the set of serial interconnection lanes; allocating at least some of the lanes of the set of serial interconnection lanes for the selected protocol according to a first mode configuration of the plurality of different mode configurations, wherein the first mode configuration allocates some of serial interconnection lanes to the data interface of the first subsystem communicating via the first protocol directed by the first controller or the data interface of the second subsystem communicating via the second protocol directed by the second controller; and exchanging data via either the controller of the first subsystem or the controller of the second subsystem through the allocated lanes of the set of serial interconnection lanes with the processing core.
Claims 22-29 and 31-38 are considered allowable subject matter because they are dependent on the allowable claims.
US PGPUB 2020/0280152 to Jeong discloses an electronic device that receives control information through a connector to an external device and switches the connector based on the detected device type. No mention of a die comprising: at least one processing core; a set of serial interconnection lanes; a first communication subsystem including a controller, a protocol coding sublayer (PCS) for interchanging data in a first communication protocol, and a data interface coupled to the at least one core; a second communication subsystem including a controller, a PCS for interchanging data in a second communication protocol, and a data interface coupled to the at least one core is present.
US PGPUB 2020/0226087 to Sun discloses detecting a type of USB protocol connected to a USB-C interface coupled to a SoC die and performing routing of signals based on the detected protocol. No mention of a first communication subsystem including a controller, a protocol coding sublayer (PCS) for interchanging data in a first communication protocol, and a data interface coupled to the at least one core; a second communication subsystem including a controller, a PCS for interchanging data in a second communication protocol, and a data interface coupled to the at least one core is present.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HARRY Z WANG whose telephone number is (571)270-1716. The examiner can normally be reached 9 am - 3 pm (Monday-Friday).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Henry Tsai can be reached at 571-272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/H.Z.W./Examiner, Art Unit 2184
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
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