Prosecution Insights
Last updated: October 26, 2026
Application No. 18/760,983

Display Device

Non-Final OA §102
Filed
Jul 01, 2024
Priority
Nov 21, 2023 — RE 10-2023-0162100
Examiner
QUINTO, KEVIN V
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
LG Display Co., Ltd.
OA Round
1 (Non-Final)
85%
Grant Probability
Favorable
1-2
OA Rounds
2m
Est. Remaining
87%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
738 granted / 867 resolved
+17.1% vs TC avg
Minimal +2% lift
Without
With
+1.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
18 currently pending
Career history
900
Total Applications
across all art units

Statute-Specific Performance

§101
0.6%
-39.4% vs TC avg
§103
49.3%
+9.3% vs TC avg
§102
31.7%
-8.3% vs TC avg
§112
15.4%
-24.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 867 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim 15 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Heo et al. (United States Patent Application Publication No. US 2022/0208867 A1, hereinafter “Heo”). In reference to claim 15, Heo discloses a device which meets the claim. Fig. 8 and 10 of Heo discloses a display device which comprises a substrate (110) including a pixel (SP1, SP2) with a plurality of sub-pixels (SP1, SP2). A first electrode (121) is in each of the plurality of sub-pixels (SP1, SP2). A bank (note unlabeled bank directly in contact and overlapping right side of 121 in fig. 8 and 10) is between adjacent sub-pixels (SP1, SP2) from the plurality of sub-pixels (SP1, SP2) on the first electrode (121). A common emission layer (EML) is on an upper surface of the first electrode (121) that is exposed by the bank (note unlabeled bank directly in contact and overlapping right side of 121 in fig. 8 and 10). The bank (note unlabeled bank directly in contact and overlapping right side of 121 in fig. 8 and 10) has an asymmetric shape and the common emission layer (EML) is separated from the bank (note unlabeled bank directly in contact and overlapping right side of 121 in fig. 8 and 10) with the asymmetric shape. Allowable Subject Matter Claims 1-14 are allowed. Claims 16-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: in the examiner’s opinion, it would not be obvious to implement a display device which comprises a substrate with a pixel that comprises a plurality of sub-pixels which has a first electrode in each of the plurality of sub-pixels such that the first electrode of a second sub-pixel among the plurality of sub-pixels is under the first electrode of a first sub-pixel in combination with a bank between adjacent sub-pixels from the plurality of sub-pixels such that a bank on the first electrode includes a plurality of side surfaces with different lengths between the plurality of side surfaces as required by the applicant in claim 1. In the examiner’s opinion, it would also not be obvious to implement a display device which comprises a substrate with a pixel that comprises a plurality of sub-pixels which has a first electrode in each of the plurality of sub-pixels, an asymmetrically shaped bank between adjacent sub-pixels from the plurality of sub-pixels, a common emission layer on an upper surface of the first electrode exposed by the bank such that the common emission layer is separated from the bank by its asymmetric shape in combination with the explicit overlapping structure of the bank between first electrodes of first and second sub-pixels specified by the applicant in claim 16. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to KEVIN QUINTO whose telephone number is (571)272-1920. The examiner can normally be reached Monday-Friday, 9-5:30. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KEVIN QUINTO/Examiner, Art Unit 2893 /Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
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Prosecution Timeline

Jul 01, 2024
Application Filed
Sep 16, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12772443
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
3y 6m to grant Granted Oct 20, 2026
Patent 12772431
SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE
3y 2m to grant Granted Oct 20, 2026
Patent 12772587
MICROLENS ARRAY AND MANUFACTURING METHOD THEREOF
3y 0m to grant Granted Oct 20, 2026
Patent 12757707
SEMICONDUCTOR DEVICE WITH POLYMER LINER AND METHOD FOR FABRICATING THE SAME
2y 11m to grant Granted Oct 06, 2026
Patent 12750995
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
3y 5m to grant Granted Sep 29, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
85%
Grant Probability
87%
With Interview (+1.7%)
2y 6m (~2m remaining)
Median Time to Grant
Low
PTA Risk
Based on 867 resolved cases by this examiner. Grant probability derived from career allowance rate.

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