Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement filed 7/1/2024 has been considered by the examiner.
Drawings
The drawings filed 7/1/2024 are approved by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-6, 8, 9 and 11-15 are rejected under 35 U.S.C. 103 as being unpatentable over Palubiak (United States Patent Application Publication No. 2020/0252564).
With respect to claim 1, Palubiak discloses: A photoelectric conversion apparatus comprising a pixel [ taught by figure 5 ] including: a photoelectric conversion unit configured to output a first signal in response to incidence of a photon, the photoelectric conversion unit including an avalanche diode configured to multiply a charge occurring from the incidence of the photon by avalanche multiplication [ taught by SPAD (24); the first signal being output from node VA ]; a counter configured to count the first signal output from the photoelectric conversion unit; and a signal processing circuit connected between the counter and the photoelectric conversion unit and configured to control output of a third signal based on the first signal and a second signal [ taught by the delay (110) wherein figure 6 show the input from node (VA) being interacted with second signals (vdn and vdp) to produce a third output signal (V out) ], wherein the signal processing circuit includes a first element having a first withstand voltage and a second element having a second withstand voltage [ figure 6 teaches transistors (152 and 154) wherein Vdn is set at a higher voltage (3.3V) than Vdp (0.0V) ] and is configured such that the first signal is input to the first element [ the node voltage (VA) is input to transistors (152 and 154) via transistors (150 and 156) ] and the second signal is
input to the second element [ met by Vdp being input to transistor (152) ], the second withstand voltage being a withstand voltage lower than the first withstand voltage [ Vdn is set at a higher voltage (3.3V) than Vdp (0.0V) ].
Figures 5 and 6 do not explicitly disclose a counter configured to count the first signal output from the photoelectric conversion unit.
Paragraph [ 0026 ] of Paluniak states, “…Each SPAD pixel may be coupled to an (analog) pulse counter or other readout circuits that generates a corresponding pixel voltage based on received photons…”.
Therefore, it would have been obvious for a person of ordinary skill in the art to have had a reasonable expectation of success in adding a counter to count the output of the disclosed pixels, when following the teaching of paragraph [ 0026 ].
The signal Vdp has a lower voltage than Vdn, thus teaching claim 3.
Paragraph [ 0048 ] states, “…Using the first bias setting, delay element 110 may exhibit a short hold-off period and a short output pulse…”; thus, teaching claim 4.
The delay element (110) includes an inverter (158), thus teaching claim 5.
The output of delay element (110) is responsive to Vdp, thus teaching claim 6.
Paragraph [ 0026 ] states, “…Each SPAD pixel may be coupled to an (analog) pulse counter or other readout circuits that generates a corresponding pixel voltage based on received photons. Each SPAD pixel 20 may additionally or instead be coupled to a time-of-flight to voltage converter circuit or other suitable readout circuits…”; thus, teaching claims 8 and 9.
Figure 4 teaches a quenching circuit (112) setting a voltage (VQ) near or below the SPAD breakdown voltage, thus being above Vdp (0.0V) to teach claim 11.
Figure 6 shows the transistors (150, 152, 154 and 156) coupled to common voltage leads (28 and 30); thus, teaching claim 12.
With regard to claim 13 as dependent on claim 8, paragraph [ 0020 ] teaches using the imaged data in a vehicle; thus, teaching an acquisition unit.
Claim 14 is taught by the TOF voltage converter circuit used to obtain a 3D image, as set forth by paragraph [ 0019 ].
Paragraph [ 0020 ] states, “…Imaging system 10 may be an imaging system on a vehicle (sometimes referred to as vehicular imaging system). Imaging system 10 may be used for LiDAR applications or any other suitable applications…”; thus, teaching claim 15 because LIDAR is a distance measuring system.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Palubiak (United States Patent Application Publication No. 2020/0252564), as applied to claim 1 above, and further in view of Laifenfeld (United States Patent Application Publication No. 2023/00166025) and Nisenzon (United States Patent Application Publication No. 2020/0257306).
Paragraph [ 0024 ] of Laifenfeld teaches it was known before the effective filing date of the present application to have used parallax shift when processing TOF signals at short range.
Figure 5 of Nisenzon teaches it was known before the effective filing date of the present application to have used image processing data to control vehicles.
Therefore, it would have been obvious for a person of ordinary skill in the art to have had a reasonable expectation of success in modifying the device of Palubiak to meet claim 16 because:
Paragraph [ 0020 ] of Palubiak suggested using their imaging system in LIDAR applications pertaining to vehicles.
Laifenfeld taught parallax processing was known in TOF LIDAR systems.
Nisenzon taught that imaging data was used for vehicle control.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Palubiak (United States Patent Application Publication No. 2020/0252564) in view of Gocho (United States Patent Application Publication No. 2020/0035710).
With respect to claim 2, Palubiak discloses: A photoelectric conversion apparatus [ taught by figure 5 ] comprising a pixel including: a photoelectric conversion unit configured to output a first signal in response to incidence of a photon, the photoelectric conversion unit including an avalanche diode configured to multiply a charge occurring from the incidence of the photon by avalanche multiplication [ taught by SPAD (24); the first signal being output from node VA ]; a counter configured to count the first signal output from the photoelectric conversion unit; and a signal processing circuit connected between the counter and the photoelectric conversion unit and configured to control output of a third signal based on the first signal and a second signal [ taught by the delay (110) wherein figure 6 show the input from node (VA) being interacted with second signals (vdn and vdp) to produce a third output signal (V out) ], wherein the signal processing circuit includes a first element and a second element [ figure 6 teaches transistors (152 and 154) wherein Vdn is set at a higher voltage (3.3V) than Vdp (0.0V) ], and is configured such that the first signal is input to the first element and the second signal is input to the second element [ the node voltage (VA) is input to transistors (152 and 154) via transistors (150 and 156) ], and wherein a gate insulting film of a transistor included in the first element has a thickness greater than that of a gate insulating film of a transistor included in the second element.
Figures 5 and 6 do not explicitly disclose a counter configured to count the first signal output from the photoelectric conversion unit.
Paragraph [ 0026 ] of Paluniak states, “…Each SPAD pixel may be coupled to an (analog) pulse counter or other readout circuits that generates a corresponding pixel voltage based on received photons…”.
Therefore, it would have been obvious for a person of ordinary skill in the art to have had a reasonable expectation of success in adding a counter to count the output of the disclosed pixels, when following the teaching of paragraph [ 0026 ].
Palubiak further does not teach wherein a gate insulting film of a transistor included in the first element has a thickness greater than that of a gate insulating film of a transistor included in the second element.
Gocho teaches that it was known before the effective filing date of the present application to have fabricated transistors on a substrate wherein the gate insulating film of a first transistor (20) is thicker (W2) than a second transistor (10) (W1) wherein paragraph [ 0074 ] taught the transistors had different withstand voltages.
Therefore, it would have been obvious for a person of ordinary skill in the art to have fabricated the transistors of Palubiak with different gate insulating thickness, when enabling the construction of the device in order to meet the voltages set forth by figure 6.
Allowable Subject Matter
Claims 7 and 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Any inquiry concerning this communication should be directed to MARK HELLNER at telephone number (571)272-6981.
Examiner interviews are available via a variety of formats. See MPEP § 713.01. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
/MARK HELLNER/ Primary Examiner, Art Unit 3645
Prosecution Insights