Office Action Predictor
Last updated: April 16, 2026
Application No. 18/761,339

MULTI-LAYER CERAMIC CAPACITOR

Non-Final OA §102§103
Filed
Jul 02, 2024
Examiner
MCFADDEN, MICHAEL P
Art Unit
2848
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Yageo Corporation
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
2y 2m
To Grant
99%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allow Rate
701 granted / 815 resolved
+18.0% vs TC avg
Strong +20% interview lift
Without
With
+20.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
25 currently pending
Career history
840
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
54.8%
+14.8% vs TC avg
§102
33.2%
-6.8% vs TC avg
§112
6.8%
-33.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 815 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-4 and 7-9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by NAGAI et al (US 2020/0312550). Regarding claim 1, NAGAI discloses a multi-layer ceramic capacitor (Fig. 1-11), comprising: a multi-layer brick (Fig. 4, 3), comprising: a ceramic body (Fig. 1, 3) having a first surface and a second surface (Fig. 1, 3a/3b) that are opposite to each other (Fig. 1), and a first end surface and a second end surface (Fig. 1, 3e) that are opposite to each other (Fig. 1), wherein the first end surface and the second end surface are connected between the first surface and the second surface (Fig. 1); and a plurality of first internal electrodes (Fig. 4, 7) and a plurality of second internal electrodes (Fig. 4, 9) alternately embedded in the ceramic body in sequence and physically separated from each other (Fig. 4), wherein the first internal electrodes extend from the first end surface toward the second end surface and are spaced apart from the second end surface (Fig. 4), and the second internal electrodes extend from the second end surface toward the first end surface and are spaced apart from the first end surface (Fig. 4); a first terminal electrode (Fig. 4, 5 on left) extending from a first portion of the first surface (Fig. 3, where 5 is on bottom) through the first end surface to a first portion of the second surface (Fig. 3, where 5 is on top), wherein the first terminal electrode comprises a first stress buffer layer (Fig. 3, E2 on left) located in an inner of the first terminal electrode under the first portion of the second surface (Fig. 3); and a second terminal electrode (Fig. 4, 5 on right) extending from a second portion of the first surface (Fig. 3, where 5 is on bottom) through the second end surface to a second portion of the second surface (Fig. 3, where 5 is on top), wherein the first terminal electrode and the second terminal electrode are physically separated from each other (Fig. 4), and the second terminal electrode comprises a second stress buffer layer (Fig. 3, E2 on right) located in an inner of the second terminal electrode under the second portion of the second surface (Fig. 3). Regarding claim 2, NAGAI further discloses that the first internal electrodes and the second internal electrodes are perpendicular to the first surface and the second surface (Fig. 3). Regarding claim 3, NAGAI further discloses that the first terminal electrode comprises: a first terminal electrode inner layer (Fig. 11, E1) covering the first portion of the first surface, the first end surface, and the first portion of the second surface (Fig. 3 and 11), wherein the first stress buffer layer is located under the first terminal electrode inner layer (Fig. 11, E2 is below E1); and a first terminal electrode outer layer (Fig. 3, E3) covering the first terminal electrode inner layer and the first stress buffer layer (Fig. 3); and the second terminal electrode comprises: a second terminal electrode inner layer (Fig. 3, E1) covering the second portion of the first surface, the second end surface, and the second portion of the second surface (Fig. 3 and 11), wherein the second stress buffer layer is located under the second terminal electrode inner layer (Fig. 11, E2 is below E1); and a second terminal electrode outer layer (Fig. 11, E3) covering the second terminal electrode inner layer and the second stress buffer layer (Fig. 11). Regarding claim 4, NAGAI further discloses that a thickness of the first stress buffer layer and a thickness of the second stress buffer layer are both equal to or greater than 100 µm (Fig. 10, multiple examples T3 greater than 100 µm). Regarding claim 7, NAGAI further discloses that materials of the first stress buffer layer and the second stress buffer layer are silver paste or copper paste ([0074-0075]). Regarding claim 8, NAGAI further discloses that the first terminal electrode outer layer comprises: a first conductive layer (Fig. 3, E3) covering the first terminal electrode inner layer and the first stress buffer layer (Fig. 3); and a second conductive layer (Fig. 3, E4) covering the first conductive layer (Fig. 3); and the second terminal electrode outer layer comprises: a third conductive layer (Fig. 3, E3) covering the second terminal electrode inner layer and the second stress buffer layer (Fig. 3); and a fourth conductive layer (Fig. 3, E4) covering the third conductive layer (Fig. 3). Regarding claim 9, NAGAI further discloses that materials of the first terminal electrode inner layer and the second terminal electrode inner layer are copper ([0073]), silver, or silver-palladium alloy, materials of the first conductive layer and the third conductive layer are nickel ([0077]), and materials of the second conductive layer and the fourth conductive layer are tin ([0078]). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 5, 10-12, and 14-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over NAGAI et al (US 2020/0312550) in view of MURAMATSU (US 2020/0234887). Regarding claim 5, NAGAI fails to teach the claim limitations. MURAMATSU teaches that the first internal electrodes and the second internal electrodes (Fig. 5, 20a/20b) are separated from the first surface (Fig. 4, top surface) by a first distance (Fig. 4, 26a), the first internal electrodes and the second internal electrodes are separated from the second surface (Fig. 4, bottom surface) by a second distance (Fig. 4, bottom 26a), the first distance is equal to the second distance (Fig. 4), and the first distance and the second distance are equal to or greater than 25 µm (10-70 µm [0041]). It would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to combine the teachings of MURAMATSU to the invention of NAGAI, in order to provide a gap so that there is lower chances of shorts in the capacitor (MURAMATSU [0041]). Regarding claim 10, NAGAI fails to teach the claim limitations. MURAMATSU teaches that the first stress buffer layer and the second stress buffer layer (Fig. 2, 34 on bottom) respectively contact with the first portion and the second portion of the second surface (Fig. 2, 34 contacts bottom of capacitor at near ends); the first terminal electrode (Fig. 2, 14b) comprises: a first terminal electrode inner layer (Fig. 2, 34 on sides and top and bottom) covering the first portion of the first surface, the first end surface, and the first stress buffer layer (Fig. 2); and a first terminal electrode outer layer (Fig. 2, 30) covering the first terminal electrode inner layer and the first stress buffer layer (Fig. 2); and the second terminal electrode (Fig. 2, 15a) comprises: a second terminal electrode inner layer (Fig. 2, 34 on right side and top and bottom) covering the second portion of the first surface, the second end surface, and the second stress buffer layer (Fig. 2); and a second terminal electrode outer layer (Fig. 2, 30) covering the second terminal electrode inner layer and the second stress buffer layer (Fig. 2). It would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to combine the teachings of MURAMATSU to the invention of NAGAI, in order to improve the reliability of the external electrodes (MURAMATSU [0006]). Regarding claim 11, NAGAI, as modified by MURAMATSU, further teaches that a thickness of the first stress buffer layer and a thickness of the second stress buffer layer are both equal to or greater than 100 µm (Fig. 10, multiple examples T3 greater than 100 µm). Regarding claim 12, NAGAI fails to teach the claim limitations. MURAMATSU teaches that the first internal electrodes and the second internal electrodes (Fig. 5, 20a/20b) are separated from the first surface (Fig. 4, top surface) by a first distance (Fig. 4, 26a), the first internal electrodes and the second internal electrodes are separated from the second surface (Fig. 4, bottom surface) by a second distance (Fig. 4, bottom 26a), the first distance is equal to the second distance (Fig. 4), and the first distance and the second distance are equal to or greater than 25 µm (10-70 µm [0041]). It would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to combine the teachings of MURAMATSU to the invention of NAGAI, in order to provide a gap so that there is lower chances of shorts in the capacitor (MURAMATSU [0041]). Regarding claim 14, NAGAI, as modified by MURAMATSU, further teaches that materials of the first stress buffer layer and the second stress buffer layer are silver paste or copper paste ([0074-0075]). Regarding claim 15, NAGAI, as modified by MURAMATSU, further teaches that materials of the first stress buffer layer and the second stress buffer layer are non-conductive materials (at least some of the materials are non-conductive such as the thermosetting resin [0074-0075]). Regarding claim 16, NAGAI, as modified by MURAMATSU, further teaches that the first terminal electrode outer layer comprises: a first conductive layer (Fig. 3, E3) covering the first terminal electrode inner layer and the first stress buffer layer (Fig. 3); and a second conductive layer (Fig. 3, E4) covering the first conductive layer (Fig. 3); and the second terminal electrode outer layer comprises: a third conductive layer (Fig. 3, E3) covering the second terminal electrode inner layer and the second stress buffer layer (Fig. 3); and a fourth conductive layer (Fig. 3, E4) covering the third conductive layer (Fig. 3). Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over NAGAI et al (US 2020/0312550) in view of AHN et al (US 2014/0138136). Regarding claim 6, NAGAI fails to teach the claim limitations. AHN teaches that the first internal electrodes (Fig. 2, 121) and the second internal electrodes (Fig. 2, 122) are separated from the first surface by a first distance (Fig. 3, D), the first internal electrodes and the second internal electrodes are separated from the second surface by a second distance (Fig. 3, B), and the second distance is greater than the first distance (Fig. 3), wherein the first distance is equal to or greater than 25 µm (Table 1, sample 1-18; 40 µm), and the second distance is equal to or greater than 100 µm (Table 1, sample 1-18; 120.0 µm). It would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to combine the teachings of AHN to the invention of NAGAI, in order to reduce noise created by vibrations (AHN [0014]). Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over NAGAI et al (US 2020/0312550) in view of MURAMATSU (US 2020/0234887) in further view of AHN et al (US 2014/0138136). Regarding claim 13, NAGAI fails to teach the claim limitations. AHN teaches that the first internal electrodes (Fig. 2, 121) and the second internal electrodes (Fig. 2, 122) are separated from the first surface by a first distance (Fig. 3, D), the first internal electrodes and the second internal electrodes are separated from the second surface by a second distance (Fig. 3, B), and the second distance is greater than the first distance (Fig. 3), wherein the first distance is equal to or greater than 25 µm (Table 1, sample 1-18; 40 µm), and the second distance is equal to or greater than 100 µm (Table 1, sample 1-18; 120.0 µm). It would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to combine the teachings of AHN to the invention of NAGAI, in order to reduce noise created by vibrations (AHN [0014]). Additional Relevant Prior Art: ONODERA et al (US 2020/0211774) teaches relevant art in Fig. 2-5. YI et al (US 2020/0273621) teaches the buffer layer can be non-conductive Fig. 2, [0069]. TAKEUCHI et al (US 2021/0343475) teaches relevant art in Fig. 2. Lee et al (US 2022/0392707) teaches relevant art in Fig. 4. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL P MCFADDEN whose telephone number is (571)270-5649. The examiner can normally be reached M-Thur 8am-9pm PST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Dole can be reached at (571) 272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MICHAEL P MCFADDEN/ Primary Examiner, Art Unit 2848
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Prosecution Timeline

Jul 02, 2024
Application Filed
Jan 20, 2026
Non-Final Rejection — §102, §103
Mar 31, 2026
Response Filed

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
99%
With Interview (+20.3%)
2y 2m
Median Time to Grant
Low
PTA Risk
Based on 815 resolved cases by this examiner. Grant probability derived from career allow rate.

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