DETAILED ACTION
This office action is in response to the application filed on July 2, 2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/02/2024 has been considered by the examiner.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claims 2 objected to because of the following informalities: Claims 2-3 “a field effect transistor S2” and “a field effect transistor S4” this transistor need to be differentiated from the transistor s1 and s3 with the term another, other, second, etc. Claim 4 last lines “a first gate driver signal” and “a first complementary gate drive signal” should be “the first gate driver signal” and “the first complementary gate drive signal”. Claim 5 “capacitor c1a2” this capacitor need to be differentiated from the capacitor C1a1 with the term another, other, second, etc. Claims 6-8 10 and 12 recite “a resistor” in multiple locations these resistors need to be differentiated from the resistor already mentioned in the claims with the term another, other second, etc. Claim 9 last lines “a second gate driver signal” and “a second complementary gate drive signal” should be “second first gate driver signal” and “the second complementary gate drive signal”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liu et al. Synthesis of input-rectifierless AC/DC converters.
Regarding Claim 1, Liu teaches (Figures 3-7) a negative reactance synthesizer (see fig. 5), comprising: a DC power source (at U, which powers dc/dc 2), a first converter (dc/dc1) configured for shaping an input current under an AC input voltage (e(t)) that has a given peak value E (E) and converting a variable DC voltage (input to converter dc/dc1) to a fixed DC voltage Uo(U); a second converter (dc/dc2) configured for converting the fixed DC voltage Uo (U) to a stack-up DC voltage VE (ξ), wherein the stack-up DC voltage VE is greater than the peak value E of the AC input voltage (see section II, B) and stacked on the AC input voltage to form the variable DC voltage (Fig. 4); a first control circuitry (at Fig. 7a) configured to generate a first gate driver signal (d1) and a first complementary gate drive signal (1-d1) for controlling the first converter; and a second control circuitry (at fig. 7b) configured to generate a second gate driver signal and a second complementary gate drive signal (d2 and 1-d2) for controlling the second converter; and wherein: the first converter acts as a buck-type converter and the second converter acts as a boost-type converter when a condition VE +E >VE>VE – E > Uo is fulfilled; the first converter acts as a buck/boost-type converter and the second converter acts as a boost-type converter when a condition VE +E >VE> Uo>VE – E is fulfilled; the first converter acts as a buck/boost-type converter and the second converter acts as a buck-type converter when a condition VE +E > Uo> VE> VE – E is fulfilled; or the first converter acts as a boost-type converter (step-up, see table III) and the second converter acts as a buck-type converter (stepup-stepdown) when a condition Uo>VE +E >VE>VE – E is fulfilled (table III, when U> ξ+E and when U>E). (For Example: See Sections II through V)
Regarding Claim 9, Liu teaches (Figures 3-7), wherein the second control circuitry (Fig. 7b) comprises: a voltage sensor (for the feedback signal) configured to sense the stack-up DC voltage VE (see fig. 5 with ξ) and generate a sensed voltage proportional to the stack-up DC voltage VE (feedback); a voltage amplifier (error amplifier) configured to amplify a difference between the sensed voltage and a second reference signal (vref), and generate a second output signal; a second controller (PWM) configured to generate a second gate driver signal based on the second output signal (PWM output); and a second driver (inverter and driver) configured to derive a second complementary gate drive signal from the second gate driver signal (see fig. 7b).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu in view of Chang US 2022/0060103.
Regarding Claim 2, Liu teaches (Figures 3-7), wherein the first converter (dc/dc1) has an input port for receiving the AC input voltage (e(t)) and an output port for delivering the fixed DC voltage Uo (U); and the first converter comprises: an inductor L1 (inductor, see fig. 3); a field effect transistor S1 having a gate for receiving the first gate driver signal (primary transistor and d1, see fig. 3), a drain connected to the second end of the inductor L1 (see fig. 3), a source connected to a negative terminal of the input port of the first converter (see fig. 3); a field effect transistor S2 (secondary transistor, see fig. 3) having a gate for receiving the first complementary gate drive signal(1-d1), a drain connected to a positive terminal of the output port of the first converter (primary transistor fig. 3), and a source connected to the second end of the inductor L1 (see fig. 3); and an output coupling capacitor Co1 (capacitor of converter 1) having a first end connected to the positive terminal of the output port of the first converter and a second end connected to a negative terminal of the output port of the first converter (see fig. 3).
Liu does not teach a sampling resistor Rsense having a first end connected to a positive terminal of the input port of the first converter; a limiting resistor rL1 having a first end connected to a second end of the sampling resistor Rsense; an inductor L1 having a first end connected to a second end of the limiting resistor rL1.
Chang teaches (Figure 3) a sampling resistor Rsense (RL) having a first end connected to a positive terminal of the input port of the first converter; a limiting resistor rL1 (Rin) having a first end connected to a second end of the sampling resistor Rsense; an inductor L1 (L1) having a first end connected to a second end of the limiting resistor rL1. (For Example: See Par. 19-20)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Liu to include a sampling resistor Rsense having a first end connected to a positive terminal of the input port of the first converter; a limiting resistor rL1 having a first end connected to a second end of the sampling resistor Rsense; an inductor L1 having a first end connected to a second end of the limiting resistor rL1, as taught by Chan to provide a higher power factor in a power delivery system to reduce losses and improve voltage regulation at the load.
Regarding Claim 3, Liu teaches (Figures 3-7)wherein the second converter (converter2, see fig. 3) has an input port for receiving the fixed DC voltage Uo (U) and an output port for delivering the stack-up DC voltage VE (ξ); and the second converter comprises: a field effect transistor S3 (primary switch) having a gate for receiving the second gate driver signal (d2), a drain connected to a positive terminal of the input port of the second converter (see fig. 3); a field effect transistor S4 (secondary switch) having a gate for receiving the second complementary gate drive signal (1-d2), a drain connected to a source of the field effect transistor S3 (see fig. 3), and a source connected to a negative terminal of the input port of the second converter (see fig. 3); an inductor L2 (inductor of second converter) having a first end connected to the source of the field effect transistor S3 (primary switch) and the drain of the field effect transistor S4 (secondary switch); and an output coupling capacitor Co2 (capacitor of converter 2) having a first end connected to the positive terminal of the output port of the second converter and a second end connected to a negative terminal of the output port of the second converter (see fig. 3). (For Example: See Sections II through V)
Liu does not teach a limiting resistor rL2 having a first end connected to a second end of the inductor L2 and a second end connected to a positive terminal of the output port of the second converter.
Chang teaches (Figure 3) a limiting resistor rL2 (Rm2) having a first end connected to a second end of the inductor L2 (L2) and a second end connected to a positive terminal of the output port (at N2). (For Example: See Par. 19-20)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Liu to include a limiting resistor rL2 having a first end connected to a second end of the inductor L2 and a second end connected to a positive terminal of the output port of the second converter, as taught by Chan to provide a higher power factor in a power delivery system to reduce losses and improve voltage regulation at the load.
Claim(s) 4 and 6-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu in view of Liu et al. General impedance synthesis using simple switching converters (herein Liu2).
Regarding Claim 4, Liu teaches (Figures 3-7) wherein the first control circuitry (fig. 7a) comprises: a multiplier (fig. 7a, x) configured to generate a control signal by multiplying the input analog signal with a first reference signal (delta ξ and current shaping reference); a current sensor (sensing Iin) having a gain M (this can be any value including 1) and configured to sense the input current to generate a sensed current (Iin); a current amplifier (amplifier) configured to amplify a difference between the sensed current and the control signal to generate a first output signal Vo1 (sent to PWM); a first controller (pwm) configured to generate a first gate driver signal based on the first output signal (output of pwm); and a first driver (driver and inverter) configured to generate a first complementary gate drive signal (1-d1) based on the first gate driver signal (see fig. 7a).
Liu does not teach a voltage sampler having a gain N and configured to sample the input AC voltage to generate a sampled voltage; an active-filter having a transfer function and configured to determine a type of reactance to be synthesized and generate an input analog signal according to the sampled voltage.
Liu2 teaches (Figures 3-8) a voltage sampler (sampling Vi) having a gain N (any value) and configured to sample the input AC voltage to generate a sampled voltage (sent to G(s)); an active-filter (G(s)) having a transfer function (see fig. 6-7) and configured to determine a type of reactance to be synthesized (Abstract and Section IV) and generate an input analog signal according to the sampled voltage (sent to PWM control). (For Example: See Sections III-IV)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Liu to include a voltage sampler having a gain N and configured to sample the input AC voltage to generate a sampled voltage; an active-filter having a transfer function and configured to determine a type of reactance to be synthesized and generate an input analog signal according to the sampled voltage, as taught by Liu2 for synthesizing impedance using a minimal configuration of switching converters.
Regarding Claim 6, Liu teaches (Figures 3-7) the apparatus.
Liu does not teach wherein the active-filter comprises: an error amplifier; a resistor R1having a first end connected to an input port of the active-filter and a second end connected to a negative input port of the error amplifier; a resistor R2 having a first end connected to a negative input port of the error amplifier and a second end connected to an output port of the error amplifier; and a capacitor C1connected in parallel with the resistor R2.
Liu2 teaches (Figures 3-8) wherein the active-filter (Fig. 6) comprises: an error amplifier; a resistor R1 (R1) having a first end connected to an input port of the active-filter and a second end connected to a negative input port of the error amplifier (see fig. 6); a resistor R2 (R2) having a first end connected to a negative input port of the error amplifier and a second end connected to an output port of the error amplifier (see fig. 6); and a capacitor C1 (C1) connected in parallel with the resistor R2. (For Example: See Sections III)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Liu to include wherein the active-filter comprises: an error amplifier; a resistor R1having a first end connected to an input port of the active-filter and a second end connected to a negative input port of the error amplifier; a resistor R2 having a first end connected to a negative input port of the error amplifier and a second end connected to an output port of the error amplifier; and a capacitor C1connected in parallel with the resistor R2, as taught by Liu2 for synthesizing impedance using a minimal configuration of switching converters.
Regarding Claim 7, Liu teaches (Figures 3-7) the apparatus.
Liu does not teach wherein the active-filter comprises: an error amplifier; a resistor R3having a first end connected to an input port of the active-filter and a second end connected to a negative input port of the error amplifier; a resistor R4having a first end connected to the negative input port of the error amplifier and a second end connected to an output port of the error amplifier; and a capacitor C2 connected in parallel with the resistor R3.
Liu2 teaches (Figures 3-8) the active-filter comprises: an error amplifier (fig. 7); a resistor R3 (R6) having a first end connected to an input port of the active-filter and a second end connected to a negative input port of the error amplifier (See fig. 7); a resistor R4 (R7) having a first end connected to the negative input port of the error amplifier and a second end connected to an output port of the error amplifier (see fig. 7); and a capacitor C2 (C2) connected in parallel with the resistor R3 (R6). (For Example: See Sections III)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Liu to include the active-filter comprises: an error amplifier; a resistor R3having a first end connected to an input port of the active-filter and a second end connected to a negative input port of the error amplifier; a resistor R4having a first end connected to the negative input port of the error amplifier and a second end connected to an output port of the error amplifier; and a capacitor C2 connected in parallel with the resistor R3, as taught by Liu2 for synthesizing impedance using a minimal configuration of switching converters.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu in view of Liu et al. General impedance synthesis using simple switching converters (herein Liu2) and further in view of Cheng US 9762125.
Regarding Claim 5, Liu teaches (Figures 3-7) wherein the current amplifier (error amplifier) comprises: an error amplifier (fig. 7a).
Liu does not teach a resistor R1_a1 having a first end connected to a negative input port of the error amplifier; a capacitor C1_a1having a first end connected to a second end of the resistor R1_a1 and a second end connected to an output port of the error amplifier; and a capacitor C1_a2 having a first end connected to the negative input port of the error amplifier and a second end connected to the output port of the error amplifier.
Cheng teaches (Figure 3) a resistor R1_a1 (R2) having a first end connected to a negative input port of the error amplifier (EA); a capacitor C1_a1 (c2) having a first end connected to a second end of the resistor R1_a1 (R2) and a second end connected to an output port of the error amplifier (EA); and a capacitor C1_a2 (c1) having a first end connected to the negative input port of the error amplifier (EA) and a second end connected to the output port of the error amplifier (EA). (For Example: See Col. 8 lines 10-42)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Liu to include a resistor R1_a1 having a first end connected to a negative input port of the error amplifier; a capacitor C1_a1having a first end connected to a second end of the resistor R1_a1 and a second end connected to an output port of the error amplifier; and a capacitor C1_a2 having a first end connected to the negative input port of the error amplifier and a second end connected to the output port of the error amplifier, as taught by Cheng to provide compensation for the amplifier.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu in view of Liu et al. General impedance synthesis using simple switching converters (herein Liu2) and further in view of Hwang US 2003/0222633.
Regarding Claim 8, Liu teaches (Figures 3-7) the wherein first control circuitry (at fig. 7a).
Liu does not teach further comprises: a resistor R1_f1 connected between the current sensor and a negative input port of the current amplifier; and a resistor R1_f2 connected between the multiplier and a positive input port of the current amplifier..
Hwang teaches (Figure 3) a resistor R1_f1 (rb) connected between the current sensor (Rs) and a negative input port of the current amplifier (22); and a resistor R1_f2 (Ra) connected between the multiplier (20) and a positive input port of the current amplifier(22). (For Example: See Par. 56-61)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Liu to include wherein first control circuitry further comprises: a resistor R1_f1 connected between the current sensor and a negative input port of the current amplifier; and a resistor R1_f2 connected between the multiplier and a positive input port of the current amplifier, as taught by Hwang to reduce power dissipation and avoid reduction in efficiency.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu in view of Blanc US 5773963.
Regarding Claim 10, Liu teaches (Figures 3-7) the apparatus with a second converter (converter 2).
Liu does not teach wherein the voltage sensor comprises: a sensing resistor R2_v1 having a first end connected to the positive terminal of the output port of the second converter; a sensing resistor R2_v2 having a first end connected to a second end of the sensing resistor R2_v1; and the sensed voltage is generated at a connection node between the sensing resistor R2_v1 and the sensing resistor R2_v2.
Blanc teaches (Figure 2) wherein the voltage sensor (R-R2) comprises: a sensing resistor R2_v1 (R1) having a first end connected to the positive terminal of the output port of the converter; a sensing resistor R2_v2 (r2) having a first end connected to a second end of the sensing resistor R2_v1; and the sensed voltage is generated at a connection node between the sensing resistor R2_v1 and the sensing resistor R2_v2 (node in fig. 2). (For Example: See Sections III-IV)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Liu to include wherein the voltage sensor comprises: a sensing resistor R2_v1 having a first end connected to the positive terminal of the output port of the second converter; a sensing resistor R2_v2 having a first end connected to a second end of the sensing resistor R2_v1; and the sensed voltage is generated at a connection node between the sensing resistor R2_v1 and the sensing resistor R2_v2, as taught by Blanc to programmably adjust its output voltage to more efficiently.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu in view of Cheng US 9762125.
Regarding Claim 11, Liu teaches (Figures 3-7) wherein the voltage amplifier comprises an error amplifier (fig. 7b).
Liu does not teach a resistor R2_a1 having a first end connected to a negative input port of the error amplifier; and a capacitor C2_a1having a first end connected to a second end of the resistor R2_a1 and a second end connected to an output port of the error amplifier.
Cheng teaches (Figure 3) a resistor R2_a1 (R2) having a first end connected to a negative input port of the error amplifier (EA); and a capacitor C2_a1 (c2) having a first end connected to a second end of the resistor R2_a1 and a second end connected to an output port of the error amplifier(). (For Example: See Col. 8 lines 10-42)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Liu to include a resistor R2_a1 having a first end connected to a negative input port of the error amplifier; and a capacitor C2_a1having a first end connected to a second end of the resistor R2_a1 and a second end connected to an output port of the error amplifier, as taught by Cheng to provide compensation for the amplifier.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu in view of Cheng and further in view of Blanc US 5773963.
Regarding Claim 12, Liu teaches (Figures 3-7) the apparatus with a second control circuitry (Fig. 7b).
Liu does not teach wherein the second control circuitry further comprises: a resistor R2_f1 connected between the second reference signal and a negative input port of the voltage amplifier; and a resistor R2_f2 connected between the voltage sensor and a positive input port of the voltage amplifier.
Blanc teaches (Figure 2) wherein the control circuitry further comprises: a resistor R2_f1 (r3) connected between the second reference signal and a negative input port of the voltage amplifier (160); and a resistor R2_f2 (R4) connected between the voltage sensor (R1-R2) and a positive input port of the voltage amplifier (160). (For Example: See Sections III-IV)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Liu to include wherein the second control circuitry further comprises: a resistor R2_f1 connected between the second reference signal and a negative input port of the voltage amplifier; and a resistor R2_f2 connected between the voltage sensor and a positive input port of the voltage amplifier, as taught by Blanc to programmably adjust its output voltage to more efficiently.
Conclusion
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/GUSTAVO A ROSARIO-BENITEZ/Primary Examiner, Art Unit 2838