DETAILED ACTION
This office action is in response to the remarks filed on 06/15/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claims 17 and 20 are objected to because of the following informalities: Claims 6 and 17 “in discontinuous conduction” this should be “in a discontinuous conduction”. Claim 20 recites “ is in a turn on state” due to the dependency to claim 1 this claim should read “is in the turn on state”. Appropriate correction is required.
Claim Interpretation
In re to claims 14 and 17-19, method claims 14 and 17-19 are rejected based on the following case law, note that under MPEP 2112.02, the principles of inherency, if a prior art device, in its normal and usual operation, would necessarily perform the method claimed, then the method claimed will be considered to be anticipated by the prior art device. When the prior art device is the same as a device described in the specification for carrying out the claimed method, it can be assumed the device inherently performs the claimed process. In re King, 801 F.2d 1324, 231 USPQ 136 (Fed Cir. 1986). Therefore the previous rejections based on the apparatus will not be repeated.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 4, 9, 10-11, 14 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Maruyama US 2022/0038009 in view of Lin US 2024/0333164.
Regarding Claims 1 and 14, Maruyama teaches (Figures 1-12) a switch control circuit of a flyback converter (Fig. 1) comprising a transformer (24), and the switch control circuit (22) comprises: a driving current regulation circuit (54 and 57), configured to generate a current regulation trigger signal (EN) according to an operating state of the flyback converter (determined by the enable signal), the current regulation trigger signal being transmitted to the switch control driving unit (60), wherein when the current regulation trigger signal is at inactive state (L, see fig. 7), the switch control driving unit drives the first switch transistor (23) to be turned on at a first switching rate (state 4, Fig. 7); when the current regulation trigger signal is at active state (H, see fig. 7), the switch control driving unit drives the first switch transistor (23) to be turned on at a second switching rate (state 3), wherein the second switching rate is lower than the first switching rate (small and large states, see fig. 7). (For Example: Par. 47-59 and 90-116)
Maruyama does not teach a first switch transistor, a second switch transistor, a first capacitor and a first inductor, wherein a resonant circuit is formed by the first capacitor and the first inductor when the second switch transistor is in turn-on state; a switch control driving unit (60), configured to generate a first switch driving signal and a second switch driving signal according to an output feedback signal of the flyback converter, to drive the first switch transistor and the second switch transistor, respectively, wherein the driving current regulation circuit is configured to generate the current regulation trigger signal at the active state in response to at least one of: a detection that the flyback converter is operating in a discontinuous conduction mode; a detection that a drain-source voltage across the first switch transistor is greater than a first threshold voltage.
Lin teaches (Figures 5-11) a first switch transistor (s1), a second switch transistor (s2), a first capacitor (Cr) and a first inductor (Lr), wherein a resonant circuit is formed by the first capacitor and the first inductor when the second switch transistor is in turn-on state (s2 on state); a switch control driving unit (850, part of 840 and 820-830), configured to generate a first switch driving signal and a second switch driving signal (GH and GL) according to an output feedback signal of the flyback converter (FB), to drive the first switch transistor and the second switch transistor, respectively (see fig. 7), wherein the driving current regulation circuit (Fig. 11) is configured to generate the current regulation trigger signal (2001) at the active state in response to at least one of: a detection that the flyback converter is operating in a discontinuous conduction mode (see figs. 7-8 and 11); a detection that a drain-source voltage across the first switch transistor is greater than a first threshold voltage. (For example: Par. 74, 78-80, 96, 127-138)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Maruyama to include a first switch transistor, a second switch transistor, a first capacitor and a first inductor, wherein a resonant circuit is formed by the first capacitor and the first inductor when the second switch transistor is in turn-on state; a switch control driving unit (60), configured to generate a first switch driving signal and a second switch driving signal according to an output feedback signal of the flyback converter, to drive the first switch transistor and the second switch transistor, respectively; wherein the driving current regulation circuit is configured to generate the current regulation trigger signal at the active state in response to at least one of: a detection that the flyback converter is operating in a discontinuous conduction mode; a detection that a drain-source voltage across the first switch transistor is greater than a first threshold voltage, as taught by Lin to improve power efficiency and raise power density.
Regarding Claim 2, Maruyama teaches (Figures 1-12) wherein when the first switch transistor (23) is turned on at the second switching rate (small, state3), a variation rate of a drain-source voltage across the first switch transistor is slowed down to a preset range (see figs. 9-10). (For Example: Par. 194-199 and 214-216)
Regarding Claim 4, Maruyama teaches (Figures 1-12) wherein when the current regulation trigger signal (EN) is at active state (en=H), the switch control driving unit controls a pull-up driving current of the first switch transistor to decrease (Fig. 7, move from state2 to state 3), so as to drive the first switch transistor to be turned on at the second switching rate (state 3). (For Example: Par. 47-59 and 90-116)
Regarding Claim 9, Maruyama teaches (Figures 1-12) the circuitry.
Maruyama does not teach wherein the switch control driving unit comprises a switch control signal generation circuit and a driving unit, the switch control signal generation circuit is configured to generate a first switch control signal and a second switch control signal according to the output feedback signal and an output reference signal, the driving unit is configured to generate the first switch driving signal and the second switch driving signal according to the first switch control signal and the second switch control signal, respectively.
Lin teaches (Figures 5-11) wherein the switch control driving unit ( 850, part of 840 and 820-830) comprises a switch control signal generation circuit (820-830 and part of 840) and a driving unit (850), the switch control signal generation circuit is configured to generate a first switch control signal and a second switch control signal (output from 840) according to the output feedback signal (Fb) and an output reference signal (840), the driving unit (850) is configured to generate the first switch driving signal and the second switch driving signal (Gh and GL) according to the first switch control signal and the second switch control signal, respectively. (For example: Par. 74-79)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Maruyama to include wherein the switch control driving unit comprises a switch control signal generation circuit and a driving unit, the switch control signal generation circuit is configured to generate a first switch control signal and a second switch control signal according to the output feedback signal and an output reference signal, the driving unit is configured to generate the first switch driving signal and the second switch driving signal according to the first switch control signal and the second switch control signal, respectively, as taught by Jiang to realize zero-voltage turn-on and recover energy on leakage inductor.
Regarding Claim 10, Maruyama teaches (Figures 1-12) wherein the driving unit (60) comprises a plurality of driving switches that are connected in parallel (at 100-102 see fig. 6), the switch control driving unit (54 and 57) is configured to adjust a number of one or more of the plurality of driving switches which is controlled to be turned on (with En signal and IN signal, which produce D0-D3 signal), according to the current regulation trigger signal at active state (en=H, fig. 7), so as to regulate a pull-up driving current of the first switch transistor (Fig. 6, with 130). (For Example: Par. 47-59 and 90-116)
Regarding Claim 11, Maruyama teaches (Figures 1-12) wherein the driving unit (60) comprises a plurality of parallel driving branches (at 100, fig. 6), each of which is formed by a current source and a resistor (current mirror and Rs), the switch control driving unit (54 and 57) is configured to regulate a current through one or more of the plurality of parallel driving branches (with En signal and IN signal, which produce D0-D3 signal) according to the current regulation trigger signal (EN) at active state (en=H, Fig. 7), so as to control a pull-up driving current of the first switch transistor (with 130). (For Example: Par. 47-59 and 90-116)
Regarding Claim 20, Maruyama teaches (Figures 1-12) a flyback converter, comprising a transformer (fig. 1, 24).
Maruyama does not teach a first switch transistor, a second switch transistor, a first capacitor, a first inductor, and a switch control circuit according to claim 1, wherein a resonant circuit is formed by the first capacitor and the first inductor when the second switch transistor is in turn-on state, wherein the switch control circuit is configured to control the first switch transistor and the second switch transistor to be turned on and off; the flyback converter further comprises a rectifier switch transistor, which is located on a secondary side of the transformer, and the first switch transistor and the second switch transistor are located on a primary side of the transformer, the flyback converter further comprises a rectifier switch transistor, which is located on a secondary side of the transformer, and the first switch transistor and the second switch transistor are located on a primary side of the transformer.
Lin teaches (Figures 5-11) a first switch transistor (s1), a second switch transistor (s2), a first capacitor (Cr) and a first inductor (Lr), wherein a resonant circuit is formed by the first capacitor and the first inductor when the second switch transistor is in turn-on state (s2 on state); wherein the switch control circuit (820-830, part of 840 and 850), configured to control the first switch transistor and the second switch transistor (s1-s2) to be turn on and off (on and off states); and the first switch transistor and the second switch transistor (s1-s2) are located on a primary side of the transformer (see fig. 5), the flyback converter further comprises a rectifier switch transistor (s3), which is located on a secondary side of the transformer (see fig. 5), and the first switch transistor and the second switch transistor are located on a primary side of the transformer (s1-s2, see fig. 5). (For example: Par. 74, 78-80, 96, 127-138)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Maruyama to include a first switch transistor, a second switch transistor, a first capacitor and a first inductor, wherein a resonant circuit is formed by the first capacitor and the first inductor when the second switch transistor is in turn-on state; wherein the switch control circuit, configured to control the first switch transistor and the second switch transistor to be turn on and off; and the first switch transistor and the second switch transistor are located on a primary side of the transformer, the flyback converter further comprises a rectifier switch transistor, which is located on a secondary side of the transformer, and the first switch transistor and the second switch transistor are located on a primary side of the transformer, as taught by as taught by Lin to improve power efficiency and raise power density.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Maruyama US 2022/0038009 in view of Lin US 2024/0333164 and further in view of Richter US2020/0152611.
Regarding Claim 3, Maruyama teaches (Figures 1-12) the first switch transistor (23).
Maruyama does not teach wherein, depending on a type of the first switch transistor, the preset range is set as follows: when the first switch transistor is a silicon-based transistor, the preset range is set to 2V/ns to 20V/ns; when the first switch transistor is a GaN-based transistor, the preset range is set to 5V/ns to 200V/ns.
Richter teaches wherein, depending on a type of the first switch transistor, the preset range is set as follows: when the first switch transistor is a silicon-based transistor, the preset range is set to 2V/ns to 20V/ns (10v/ns and above); when the first switch transistor is a GaN-based transistor, the preset range is set to 5V/ns to 200V/ns (10V/ns and above). (For example: Par. 5)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Maruyama to include wherein, depending on a type of the first switch transistor, the preset range is set as follows: when the first switch transistor is a silicon-based transistor, the preset range is set to 2V/ns to 20V/ns; when the first switch transistor is a GaN-based transistor, the preset range is set to 5V/ns to 200V/ns, as taught by Jiang to realize zero-voltage turn-on and recover energy on leakage inductor.
Claim(s) 5 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Maruyama US 2022/0038009 in view of Lin US 2024/0333164 and further in view of Hayakawa US 20160380527.
Regarding Claims 5 and 18, Maruyama teaches (Figures 1-12) the circuitry.
Maruyama does not teach wherein the driving current regulation circuit comprises a voltage detection circuit and a comparison circuit, before the first switch transistor is turned on, the voltage detection circuit is configured to obtain a voltage detection signal by detecting a drain-source voltage across the first switch transistor, the comparison circuit is configured to compare the voltage detection signal and a first threshold voltage, and generate the current regulation trigger signal at active state if the voltage detection signal is greater than the first threshold voltage.
Hayakawa teaches (Figures 1-4) wherein the driving current regulation circuit (15-16 and R1) comprises a voltage detection circuit (15 and R1 and 16b) and a comparison circuit (16a and 55), before the first switch transistor is turned on (with the sample and hold operation, par. 47), the voltage detection circuit is configured to obtain a voltage detection signal by detecting a drain-source voltage across the first switch transistor (with the ID current, par. 46-47), the comparison circuit (16a and 55) is configured to compare the voltage detection signal and a first threshold voltage (Vth2), and generate the current regulation trigger signal (from 55) at active state (high state) if the voltage detection signal is greater than the first threshold voltage (par .52). (For Example: Par. 46-55)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Maruyama to include wherein the driving current regulation circuit comprises a voltage detection circuit and a comparison circuit, before the first switch transistor is turned on, the voltage detection circuit is configured to obtain a voltage detection signal by detecting a drain-source voltage across the first switch transistor, the comparison circuit is configured to compare the voltage detection signal and a first threshold voltage, and generate the current regulation trigger signal at active state if the voltage detection signal is greater than the first threshold voltage, as taught by Hayakawa to reduce switching losses or a switching noise increases.
Claim(s) 6-8 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Maruyama US 2022/0038009 in view of Lin US 2024/0333164 and further in view of Liu 2011/0057637.
Regarding Claims 6-7 and 17, Maruyama teaches (Figures 1-12) the flyback circuitry.
Maruyama does not teach wherein the driving current regulation circuit comprises a mode detection circuit, configured to generate the current regulation trigger signal at active state when the mode detection circuit detects that the flyback converter is operating in discontinuous conduction mode; wherein the driving current regulation circuit is configured to detect an operating mode of the flyback converter according to switching times of the first switch transistor and the second switch transistor, the mode detection circuit detects that the flyback converter is operating in discontinuous conduction mode when a time interval, which starts from a time for turning off the second switch transistor to a time for turning on the first switch transistor, reaches a first time threshold.
Liu teaches (Figures 6-15) wherein the driving current regulation circuit (14-16) comprises a mode detection circuit (14), configured to generate the current regulation trigger signal at active state (dcm) when the mode detection circuit detects that the flyback converter is operating in discontinuous conduction mode (Fig. 9, DCM); wherein the driving current regulation circuit is configured to detect an operating mode of the converter (see fig. 9) according to switching times of the first switch transistor and the second switch transistor (at power stage 12), the mode detection circuit detects that the converter is operating in discontinuous conduction mode when a time interval, which starts from a time for turning off the second switch transistor to a time for turning on the first switch transistor (Det-Out with fig. 14 and the comparison in the gate 1442), reaches a first time threshold (Vgate). (For Example: Par. 49-50)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Maruyama to include wherein the driving current regulation circuit comprises a mode detection circuit, configured to generate the current regulation trigger signal at active state when the mode detection circuit detects that the flyback converter is operating in discontinuous conduction mode; wherein the driving current regulation circuit is configured to detect an operating mode of the flyback converter according to switching times of the first switch transistor and the second switch transistor, the mode detection circuit detects that the flyback converter is operating in discontinuous conduction mode when a time interval, which starts from a time for turning off the second switch transistor to a time for turning on the first switch transistor, reaches a first time threshold, as taught by Liu to avoid larger switching loss and higher EMI.
Regarding Claim 8, Maruyama teaches (Figures 1-12) wherein the driving current regulation circuit (60) detects an operating mode (mode of operation) of the flyback converter according to an output reference signal (Vfbdiv) and the output feedback signal (FB) of the flyback converter. (For Example: Par. 47-59 and 90-116)
Allowable Subject Matter
Claims 12-13, 15-16 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Reasons for Indicating Allowable Subject Matter
The following is an examiner’s statement of reasons for indicating Allowable Subject Matter:
Claim 13; prior art of record fails to disclose either by itself or in combination: “…wherein the driving unit comprises a logic operation circuit and a driving circuit, the logic operation circuit is configured to generate a first logic operation signal and a second logic operation signal according to the current regulation trigger signal, the first switch control signal and the second switch control signal, the driving circuit is configured to control a pull-up driving current of the first switch transistor and a pull-up driving current of the second switch transistor according to the first logic operation signal and the second logic operation signal.”
Claim 12; prior art of record fails to disclose either by itself or in combination: “…wherein the switch control signal generation circuit comprises a signal generation circuit and a signal regulation circuit, the signal generation circuit is configured to generate the first switch control signal and the second switch control signal according to the output feedback signal and the output reference signal; the signal regulation circuit is configured to perform regulation on the first switch control signal and the second switch control signal according to the current regulation trigger signal, to transmit the first switch control signal and the second switch control signal, which are obtained after the regulation, to the driving unit as output signals.”
Claim 19; prior art of record fails to disclose either by itself or in combination: “…wherein when the drain-source voltage across the first switch transistor of the flyback converter decreases to be lower than a second threshold voltage, the first switch transistor is controlled to be turned on at the first switching rate; and when the drain-source voltage across the first switch transistor of the flyback converter rises to be greater than the first threshold voltage, the first switch transistor is controlled to be turned on at the second switching rate, wherein the first threshold voltage is greater than the second threshold voltage.”
These features taken alone or in combination are neither disclosed nor suggested by the prior art of record.
Response to Arguments
Applicant's arguments filed 06/15/2026 have been fully considered but they are not persuasive.
Applicant argued that “Thus, in Maruyama's disclosure, the switching rate is not always in SMALL state when the enable signal en is at the active state. Therefore, the correspondence between the switching rate and the active state of the enable signal en in Maruyama's disclosure does not correspond to the control logic of limitation (B)”. In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., is not always in small sate) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUSTAVO A ROSARIO-BENITEZ whose telephone number is (571)270-7888. The examiner can normally be reached M-F 9AM-5PM.
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/GUSTAVO A ROSARIO-BENITEZ/Primary Examiner, Art Unit 2838
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