DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement filed on 07/02/2024, 03/18/2024, 03/25/2025, 01/13/2026, 03/06/2026 and 08/27/2026 have been considered and placed in the application file.
Double Patenting
Claims 1-23 are rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claims 1-26 of U.S. Patent No. 12,034,420. Although the conflicting claims are not identical, they are not patentably distinct from each other because all limitations/features of the present claims are present in the patented claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 7, 12-16, 19 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Azuhata (U.S. 10,367,458).
Regarding claim 1, Azuhata (hereinafter, Ref~458) discloses (please see Fig. 1 and related text for details) an apparatus, comprising:
a control circuit (the circuit/elements disposed between input unit 2 and the output stage/transistors 11 of Fig. 1 can be read as the claimed one OR at least it is functionally equivalent to it) having an input (IN+/In- of Fig. 1), first control outputs (outputs from upper gate driver 10 of Fig. 1), and second control outputs (outputs from the lower date driver 10 of Fig. 1), the control circuit including a modulated signal generator (centered by comparator 9 of Fig. 1) coupled between the input and the first control outputs and an amplifier (e.g., error amplifier 7 of Fig. 1 can be read as the claimed amplifier) coupled between the input and the second control outputs;
a first power stage (upper transistors 11 of Fig. 1) having first control inputs (gate terminals of transistors 11 of Fig. 1) and a first power stage output (output from the upper transistors 11 of Fig. 1), the first control inputs coupled to the first control outputs; and
a second power stage (lower transistors 11 of Fig. 1) having second control inputs (gate terminals of transistors 11 of Fig. 1) and a second power stage output (output from the lower transistors 11 of Fig. 1), the second control inputs coupled to the second control outputs, meeting claim 1.
Regarding claim 7, Ref~458 discloses the apparatus of claim 1, wherein the modulated signal generator is a pulse width modulation (PWM) signal generator (PWM 3 of Fig. 1), meeting claim 7.
Regarding claim 12, Ref~458 discloses the apparatus of claim 1, wherein the first power stage output is coupled to an inductor terminal (see inductor terminal of the upper output inductor of Fig.1 ), and the second power stage output is coupled to a capacitor terminal ( see capacitor terminal of the lower output capacitor of Fig. 1), meeting claim 12.
Regarding claim 13, Ref~458 discloses the apparatus of claim 1, wherein the input is an audio input, and the apparatus further comprises an inductor coupled between the first power stage output and a first speaker terminal, a first capacitor coupled between the first speaker terminal and a second speaker terminal, and a second capacitor coupled between the second speaker terminal and a reference terminal (ground), the second speaker terminal coupled to the second power stage output as seen from Fig. 1, meeting claim 13.
Regarding claim 14, Ref~458 does not expressly disclose the apparatus of claim 1, wherein the control circuit and the first and second power stages are part of an integrated circuit. However, these are normal design features in the field depending on custom specifications, meeting claim 14.
Regarding claim 15, Ref~458 discloses the apparatus of claim 1, wherein the control circuit and the first and second power stages are part of an audio amplifier circuit as seen/disclosed, meeting claim 15.
Regarding claim 16, Ref~458 discloses (see Fig. 1 and related text for details) an apparatus comprising:
a control circuit (the circuit/elements disposed between input unit 2 and the output stage/transistors 11 of Fig. 1 can be read as the claimed one OR at least it is functionally equivalent to it) having an input (IN+/In- of Fig. 1), first control outputs (outputs from upper gate driver 10 of Fig. 1), and second control outputs (outputs from the lower date driver 10 of Fig. 1), the control circuit including a modulated signal generator (centered by comparator 9 of Fig. 1) coupled between the input and the first control outputs and an amplifier (e.g., error amplifier 7 of Fig. 1 can be read as the claimed amplifier) coupled between the input and the second control outputs;
a first transistor (first/upper transistor 11 of Fig. 1) coupled between a power terminal and a first output, the first transistor having a first control terminal (gate) coupled to the first control outputs;
a second transistor (second/upper transistor 11 of Fig. 1) coupled between the first output and a reference terminal (ground), the second transistor having a second control terminal (gate) coupled to the first control outputs;
a third transistor (first/lower transistor 11 of Fig. 1) coupled between the power terminal and a second output, the third transistor having a third control terminal (gate) coupled to the second control outputs; and
a fourth transistor (second/lower transistor 11 of Fig. 1) coupled between the second output and the reference terminal, the fourth transistor having a fourth control terminal (gate) coupled to the second control outputs as seen, meeting claim 16.
Regarding claim 19, Ref~458 discloses the apparatus of claim 16, wherein the input is an audio input, the first output is coupled to a first speaker terminal (out+ of Fig. 1), and the second output is coupled to a second speaker terminal (out- of Fig. 1) as seen from Fig. 1, meeting claim 19.
Regarding claim 22, Ref~458 discloses (see Fig. 1 and related text for details) method comprising: receiving a first signal (IN of Fig. 1);
generating (via upper gate driver 10 of Fig. 1) first control signals from the first signal using a modulated signal generator (comparator 9 of Fig. 1);
generating (via lower gate driver 10 of Fig. 1) second control signals from the first signal using an amplifier;
generating (via upper transistors 11 pair of Fig. 1) a second signal by providing the first control signals to a first power stage (upper transistors 11 pair of Fig. 1); and
generating a third signal (via lower transistors 11 pair of Fig. 1) by providing the second control signals to a second power stage (lower transistors 11 pair of Fig. 1), meeting claim 22.
Allowable Subject Matter
Claims 2-6, 8-11, 17-18, 20-21 and 23 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HIEU P NGUYEN whose telephone number is 571-272-8577. The examiner can normally be reached on Monday-Friday 8:30AM-6:00PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Lindgren Baltzell can be reached on 571-272-5918. The fax phone number for the organization where this application or proceeding is assigned is 703-872-9306.
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/HIEU P NGUYEN/Primary Examiner, Art Unit 2843
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