Prosecution Insights
Last updated: October 02, 2026
Application No. 18/761,451

SUPERCONDUCTING RESONANT CIRCUIT AND MEASUREMENT METHOD

Non-Final OA §103
Filed
Jul 02, 2024
Priority
Jul 26, 2023 — JP 2023-121716
Examiner
SEDOROOK, DAVID PAUL
Art Unit
Tech Center
Assignee
NEC Corporation
OA Round
1 (Non-Final)
92%
Grant Probability
Favorable
1-2
OA Rounds
10m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 92% — above average
92%
Career Allowance Rate
140 granted / 153 resolved
+31.5% vs TC avg
Moderate +8% lift
Without
With
+7.5%
Interview Lift
resolved cases with interview
Typical timeline
3y 0m
Avg Prosecution
29 currently pending
Career history
166
Total Applications
across all art units

Statute-Specific Performance

§103
66.3%
+26.3% vs TC avg
§102
27.8%
-12.2% vs TC avg
§112
5.5%
-34.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 153 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claims 1-6 are rejected under 35 U.S.C. 103 as being unpatentable over Eden et al (WO 0055936) in view of Jacob et al (US 2024/0220840) and Brink et al (US 10305015). Regarding Claim 1, Eden et al discloses a superconducting resonant circuit (superconductor HTS filter resonant structure [page 6, lines 14-44] Fig 1a, Fig 1b, Fig 1c) comprising: a first superconducting circuit chip (fixed substrate 20, and fixed plates 10 and 15 [page 6, lines 14-44] Fig 1a) including lumped circuit elements [page 6, lines 40-44], and a first lumped constant capacitor electrode (fixed capacitor plate 15 Fig 1a); a second superconducting circuit chip (moveable substrate 35 [page 6, lines 40-44] Fig 1a) including a second lumped constant capacitor electrode (floating capacitor plate 30 [page 6, lines 40-44] Fig 1a) facing the first lumped constant capacitor electrode (15 Fig 1a); and an actuator (piezoelectric actuator structure 70 [page 9, lines 1-23] Fig 3b) configured to change an inter-electrode distance (variable vacuum gap 50 between capacitor plates [page 9, lines 1-23] Fig 1a) between the first lumped constant capacitor electrode (15 Fig 1a and Fig 3a) and the second lumped constant capacitor electrode (30 Fig 1a and Fig 3a). Eden et al does not disclose a first superconducting circuit chip including a readout waveguide, and a lumped constant inductor. Jacob et al, in the related art of semiconductor devices that include superconducting devices, discloses a first superconducting circuit chip (qubit chip 84 (chip 1) [0087] Fig 6 viewed from 180 degrees) including a readout waveguide (coplanar waveguides CPW 85 for readout [0087] Fig 6 viewed from 180 degrees), and a lumped constant inductor (lumped inductor is placed above the SiO.sub2 cladding connected through vias [0080] in the area where microwave inductive feedlines 110 and 112 [0088] are present Fig 6 viewed from 180 degrees). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Eden et al to include a first superconducting circuit chip including a readout waveguide, and a lumped constant inductor as taught by Jacob et al in order to have most of the inductive energy stored on the readout plane [column 9, lines 60-67]-[column 10, lines 1-16] as referred to by Brink et al, which would optimize the electrical functioning of the device. Further, a person of ordinary skill in the art would have recognized that having a lumped inductor on the same plane as the readout waveguide would be advantageous in having same plane advantages wherein lumped components can be easily attached (see MPEP 2143.I(D)). Regarding Claim 2, the combination of Eden et al, Jacob et al, and Brink et al discloses the limitations of claim 1 as explained above. The combination of Eden et al, Jacob et al, and Brink et al further discloses wherein the actuator (piezoelectric actuator structure 70 [page 9, lines 1-23] Fig 3b Eden et al) is configured to change the inter-electrode distance by moving one of the first superconducting circuit chip (fixed substrate 20, and fixed plates 10 and 15 [page 6, lines 14-44] Fig 1a Eden et al) and the second superconducting circuit chip (moveable substrate 35 [page 6, lines 40-44] Fig 1a Eden et al) with respect to the other of the first superconducting circuit chip (fixed substrate 20, and fixed plates 10 and 15 [page 6, lines 14-44] Fig 1a Eden et al) and the second superconducting circuit chip (moveable substrate 35 [page 6, lines 40-44] Fig 1a Eden et al) in a direction (vertical direction) in which the first lumped constant capacitor electrode (15 Fig 1a and Fig 3a Eden et al) and the second lumped constant capacitor electrode (30 Fig 1a and Fig 3a Eden et al) face each other. Regarding Claim 3, the combination of Eden et al, Jacob et al, and Brink et al discloses the limitations of claim 1 as explained above. The combination of Eden et al, Jacob et al, and Brink et al further discloses wherein the actuator includes a piezo actuator (piezoelectric actuator structure 70 [page 9, lines 1-23] Fig 3b Eden et al). Regarding Claim 4, the combination of Eden et al, Jacob et al, and Brink et al discloses the limitations of claim 1 as explained above. The combination of Eden et al, Jacob et al, and Brink et al further discloses wherein the readout waveguide (coplanar waveguides CPW 85 for readout [0087] Fig 6 viewed from 180 degrees Jacob et al) and the lumped constant inductor (lumped inductor is placed above the SiO.sub2 cladding connected through vias [0080] in the area where microwave inductive feedlines 110 and 112 [0088] are present Fig 6 viewed from 180 degrees Jacob et al) are coupled (both the readout waveguide and the lumped constant inductor are attached to the same semiconductor chip (first) which would be considered at least electrically coupled in the broadest reasonable interpretation and would meet this limitation). Regarding Claim 5, the combination of Eden et al, Jacob et al, and Brink et al discloses the limitations of claim 1 as explained above. The combination of Eden et al, Jacob et al, and Brink et al further discloses wherein the readout waveguide (coplanar waveguides CPW 85 for readout [0087] Fig 6 viewed from 180 degrees Jacob et al) and the first lumped constant capacitor electrode (15 Fig 1a and Fig 3a Eden et al) are coupled (both the readout waveguide and the first lumped constant capacitor electrode are attached to the same semiconductor chip (first) which would be considered at least electrically coupled in the broadest reasonable interpretation and would meet this limitation). Regarding Claim 6, the combination of Eden et al, Jacob et al, and Brink et al discloses the limitations of claim 1 as explained above. The combination of Eden et al, Jacob et al, and Brink et al further discloses wherein the readout waveguide (coplanar waveguides CPW 85 for readout [0087] Fig 6 viewed from 180 degrees Jacob et al) includes a coplanar waveguide (coplanar waveguides CPW 85 for readout [0087] Fig 6 viewed from 180 degrees Jacob et al). Claims 7-12 are rejected under 35 U.S.C. 103 as being unpatentable over Eden et al (WO 0055936) in view of Jacob et al (US 2024/0220840) and Brink et al (US 10305015), and in further view of Marek (EP 0895092). Regarding Claim 7, Eden et al discloses a superconducting resonant circuit (superconductor HTS filter resonant structure [page 6, lines 14-44] Fig 1a, Fig 1b, Fig 1c) comprising: a first superconducting circuit chip (fixed substrate 20, and fixed plates 10 and 15 [page 6, lines 14-44] Fig 1a) including lumped circuit elements [page 6, lines 40-44], and a first lumped constant capacitor electrode (fixed capacitor plate 15 Fig 1a); a second superconducting circuit chip (moveable substrate 35 [page 6, lines 40-44] Fig 1a) including a second lumped constant capacitor electrode (floating capacitor plate 30 [page 6, lines 40-44] Fig 1a) facing the first lumped constant capacitor electrode (15 Fig 1a); and an actuator (piezoelectric actuator structure 70 [page 9, lines 1-23] Fig 3b) configured to change an inter-electrode distance (variable vacuum gap 50 between capacitor plates [page 9, lines 1-23] Fig 1a) between the first lumped constant capacitor electrode (15 Fig 1a and Fig 3a) and the second lumped constant capacitor electrode (30 Fig 1a and Fig 3a). Eden et al does not disclose a measurement method comprising a first superconducting circuit chip including a readout waveguide, and a lumped constant inductor. Jacob et al, in the related art of semiconductor devices that include superconducting devices, discloses a first superconducting circuit chip (qubit chip 84 (chip 1) [0087] Fig 6 viewed from 180 degrees) including a readout waveguide (coplanar waveguides CPW 85 for readout [0087] Fig 6 viewed from 180 degrees), and a lumped constant inductor (lumped inductor is placed above the SiO.sub2 cladding connected through vias [0080] in the area where microwave inductive feedlines 110 and 112 [0088] are present Fig 6 viewed from 180 degrees). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Eden et al to include a first superconducting circuit chip including a readout waveguide, and a lumped constant inductor as taught by Jacob et al in order to have most of the inductive energy stored on the readout plane [column 9, lines 60-67]-[column 10, lines 1-16] as referred to by Brink et al, which would optimize the electrical functioning of the device. Further, a person of ordinary skill in the art would have recognized that having a lumped inductor on the same plane as the readout waveguide would be advantageous in having same plane advantages wherein lumped components can be easily attached (see MPEP 2143.I(D)). The combination of Eden et al, Jacob et al, and Brink et al does not directly disclose a measurement method comprising a superconducting resonant circuit. Marek, in the related art of semiconductor devices that include superconducting resonators, discloses a measurement method (measurement method [page 2, lines 21-42]) comprising a superconducting resonant circuit (superconducting resonator [page 2, lines 21-42]). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Eden et al, Jacob et al, and Brink et al to include a measurement method comprising a superconducting resonant circuit as taught by Marek in order to apply to NMR spectroscopy by measuring additional loss resistances which will reduce the decay time of the excitation pulse [page 2, lines 21-42]. Further, a person of ordinary skill in the art would have recognized that using superconductor resonator in a measurement method would be advantageous in expanding the function and use of the device (see MPEP 2143.I(D)). Regarding Claim 8, the combination of Eden et al, Jacob et al, Brink et al, and Marek discloses the limitations of claim 7 as explained above. The combination of Eden et al, Jacob et al, Brink et al, and Marek further discloses further comprising: extracting a loss amount of the superconducting resonant circuit (superconductor HTS filter resonant structure [page 6, lines 14-44] Fig 1a, Fig 1b, Fig 1c Eden et al) based on the high frequency response characteristics (desired resonance frequency from a measurement sample such as a high frequency resonator [page 1, lines 1-11] Marek). Regarding Claim 9, the combination of Eden et al, Jacob et al, Brink et al, and Marek discloses the limitations of claim 7 as explained above. The combination of Eden et al, Jacob et al, Brink et al, and Marek further discloses wherein the changing includes moving one of the first superconducting circuit chip (fixed substrate 20, and fixed plates 10 and 15 [page 6, lines 14-44] Fig 1a Eden et al) and the second superconducting circuit chip (moveable substrate 35 [page 6, lines 40-44] Fig 1a Eden et al) with respect to the other of the first superconducting circuit chip (fixed substrate 20, and fixed plates 10 and 15 [page 6, lines 14-44] Fig 1a Eden et al) and the second superconducting circuit chip (moveable substrate 35 [page 6, lines 40-44] Fig 1a Eden et al) in a direction (vertical direction) in which the first lumped constant capacitor electrode (15 Fig 1a and Fig 3a Eden et al) and the second lumped constant capacitor electrode (15 Fig 1a and Fig 3a Eden et al) face each other. Regarding Claim 10, the combination of Eden et al, Jacob et al, Brink et al, and Marek discloses the limitations of claim 7 as explained above. The combination of Eden et al, Jacob et al, Brink et al, and Marek further discloses wherein the readout waveguide (coplanar waveguides CPW 85 for readout [0087] Fig 6 viewed from 180 degrees Jacob et al) and the lumped constant inductor (lumped inductor is placed above the SiO.sub2 cladding connected through vias [0080] in the area where microwave inductive feedlines 110 and 112 [0088] are present Fig 6 viewed from 180 degrees Jacob et al) are coupled (both the readout waveguide and the lumped constant inductor are attached to the same semiconductor chip (first) which would be considered at least electrically coupled in the broadest reasonable interpretation and would meet this limitation). Regarding Claim 11, the combination of Eden et al, Jacob et al, Brink et al, and Marek discloses the limitations of claim 7 as explained above. The combination of Eden et al, Jacob et al, Brink et al, and Marek further discloses wherein the readout waveguide (coplanar waveguides CPW 85 for readout [0087] Fig 6 viewed from 180 degrees Jacob et al) and the first lumped constant capacitor electrode (15 Fig 1a and Fig 3a Eden et al) are coupled (both the readout waveguide and the first lumped constant capacitor electrode are attached to the same semiconductor chip (first) which would be considered at least electrically coupled in the broadest reasonable interpretation and would meet this limitation). Regarding Claim 12, the combination of Eden et al, Jacob et al, Brink et al, and Marek discloses the limitations of claim 7 as explained above. The combination of Eden et al, Jacob et al, Brink et al, and Marek further discloses wherein the readout waveguide (coplanar waveguides CPW 85 for readout [0087] Fig 6 viewed from 180 degrees Jacob et al) includes a coplanar waveguide (coplanar waveguides CPW 85 for readout [0087] Fig 6 viewed from 180 degrees Jacob et al). Claims 13-17 are rejected under 35 U.S.C. 103 as being unpatentable over Eden et al (WO 0055936) in view of Bestwick et al (US 2025/0077926). Regarding Claim 13, Eden et al discloses a superconducting resonant circuit (superconductor HTS filter resonant structure [page 6, lines 14-44] Fig 1a, Fig 1b, Fig 1c) comprising: a first superconducting circuit chip (fixed substrate 20, and fixed plates 10 and 15 [page 6, lines 14-44] Fig 1a) including lumped circuit elements [page 6, lines 40-44], and a first lumped constant capacitor electrode (fixed capacitor plate 15 Fig 1a); a second superconducting circuit chip (moveable substrate 35 [page 6, lines 40-44] Fig 1a) including a second lumped constant capacitor electrode (floating capacitor plate 30 [page 6, lines 40-44] Fig 1a) facing the first lumped constant capacitor electrode (15 Fig 1a); and an actuator (piezoelectric actuator structure 70 [page 9, lines 1-23] Fig 3b) configured to change an inter-electrode distance (variable vacuum gap 50 between capacitor plates [page 9, lines 1-23] Fig 1a) between the first lumped constant capacitor electrode (15 Fig 1a and Fig 3a) and the second lumped constant capacitor electrode (30 Fig 1a and Fig 3a). Eden et al does not disclose a first superconducting circuit chip including a readout waveguide; and a second superconducting circuit chip including a lumped constant inductor. Bestwick et al, in the related art of semiconductor devices that include superconducting devices, discloses a first superconducting circuit chip (cap wafer 212 [0096] Fig 2) including a readout waveguide (circuitry portions 214 and 216 include coplanar waveguides [0108] for readout [0107] Fig 2); and a second superconducting circuit chip (quantum processor chip 202 [0106] Fig 2) including a lumped constant inductor (quantum circuit devices 204 may include inductors or other circuitry elements [0096] Fig 2/frequency-specific filter 1936 may include lumped inductors [0242] Fig 19A, which are known in the art to be part of quantum circuit devices). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Eden et al to include a readout waveguide in the first superconducting chip and a lump inductor in the second superconducting chip as taught by Bestwick et al in order to mitigate unwanted modes [0113]. Further, a person of ordinary skill in the art would have recognized that mode preservation would optimize the optical and electrical functioning of the device (see MPEP 2143.I(D)). Regarding Claim 14, the combination of Eden et al and Bestwick et al discloses the limitations of claim 13 as explained above. The combination of Eden et al and Bestwick et al further discloses wherein the actuator (piezoelectric actuator structure 70 [page 9, lines 1-23] Fig 3b Eden et al) is configured to change the inter-electrode distance by moving one of the first superconducting circuit chip (fixed substrate 20, and fixed plates 10 and 15 [page 6, lines 14-44] Fig 1a Eden et al) and the second superconducting circuit chip (moveable substrate 35 [page 6, lines 40-44] Fig 1a Eden et al) with respect to the other of the first superconducting circuit chip (fixed substrate 20, and fixed plates 10 and 15 [page 6, lines 14-44] Fig 1a Eden et al) and the second superconducting circuit chip (moveable substrate 35 [page 6, lines 40-44] Fig 1a Eden et al) in a direction (vertical direction) in which the first lumped constant capacitor electrode (15 Fig 1a and Fig 3a Eden et al) and the second lumped constant capacitor electrode (30 Fig 1a and Fig 3a Eden et al) face each other. Regarding Claim 15, the combination of Eden et al and Bestwick et al discloses the limitations of claim 13 as explained above. The combination of Eden et al and Bestwick et al further discloses wherein the actuator includes a piezo actuator (piezoelectric actuator structure 70 [page 9, lines 1-23] Fig 3b Eden et al). Regarding Claim 16, the combination of Eden et al and Bestwick et al discloses the limitations of claim 13 as explained above. The combination of Eden et al and Bestwick et al further discloses wherein the readout waveguide (circuitry portions 214 and 216 include coplanar waveguides [0108] for readout [0107] Fig 2 Bestwick et al) and the first lumped constant capacitor electrode (15 Fig 1a and Fig 3a Eden et al) are coupled (both the readout waveguide and the first lumped constant capacitor electrode are attached to the same semiconductor chip (first) which would be considered at least electrically coupled in the broadest reasonable interpretation and would meet this limitation). Regarding Claim 17, the combination of Eden et al and Bestwick et al discloses the limitations of claim 13 as explained above. The combination of Eden et al and Bestwick et al further discloses wherein the readout waveguide includes a coplanar waveguide (circuitry portions 214 and 216 include coplanar waveguides [0108] for readout [0107] Fig 2 Bestwick et al). Related Cited Prior Art The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Abraham et al (US 2019/0042963) which discloses superconducting circuits [0004], and Topaloglu et al (US 2020/0075833) which discloses piezoelectric actuators [0088]. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID PAUL SEDOROOK whose telephone number is (571)272-4158. The examiner can normally be reached Monday - Friday 7:30 am -5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William B Partridge can be reached on (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /D.P.S./Examiner, Art Unit 2812 /William B Partridge/Supervisory Patent Examiner, Art Unit 2812
Read full office action

Prosecution Timeline

Jul 02, 2024
Application Filed
Aug 24, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12733238
OHMIC ELECTRODE FOR TWO-DIMENSIONAL CARRIER GAS (2DCG) SEMICONDUCTOR DEVICE
2y 1m to grant Granted Sep 08, 2026
Patent 12727221
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
3y 1m to grant Granted Sep 01, 2026
Patent 12727241
STACKED MULTI-GATE DEVICE WITH DIFFUSION STOPPING LAYER AND MANUFACTURING METHOD THEREOF
3y 2m to grant Granted Sep 01, 2026
Patent 12720830
METHOD OF MANUFACTURING SILICON CARBIDE SUBSTRATE, SILICON CARBIDE SINGLE-CRYSTAL SUBSTRATE AND SILICON CARBIDE SEMICONDUCTOR DEVICE
3y 4m to grant Granted Aug 25, 2026
Patent 12696537
SEMICONDUCTOR DEVICES
2y 11m to grant Granted Jul 28, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
92%
Grant Probability
99%
With Interview (+7.5%)
3y 0m (~10m remaining)
Median Time to Grant
Low
PTA Risk
Based on 153 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month