DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This non-final Office action is in response to Applicant’s amendment filed 1/26/26 which amended claims 1, 8, 10, 13, 16, 18-20, and 23. Claims 1, 3-14, 16, and 18-23 are pending.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3-14, 16, and 18-23 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Patent Application Publication 2022/0270703 to CHANDRAMANI et al.
Regarding claims 1, 10, 16, and 21-23, CHANDRAMANI describes a “RELINKING SCHEME IN SUB-BLOCK MODE” (title).
He teaches that a list of bad blocks may include factory-marked bad blocks and grown bad blocks (0004). He further teaches that each block includes a plurality of sub-blocks (0005 and Figs. 8-14).
CHANDRAMANI mentions executing read, write, and erase operations on sub-blocks at 0031. If these are successful, sub-blocks may be logically linked to form metablocks (a grouping of sub-blocks) as taught at 0032. Each sub-block that is linked is first identified as a sub-block relinking candidate, as claimed.
CHANDRAMANI shows various metrics used to determine which sub-blocks to link, such as whether a given sub-block is sub-block 0 or sub-block 1, as shown in Fig. 14. More specifically, in Fig. 14 he shows that one metric used in the relinking process is the sub-block identifier “sub-block 0” (shown for example as relinked metablocks 1408 and 1412, each having four sub-block 0s). Another example of this metric is sub-block identifier “sub-block 1” (shown for example as relinked metablock 1410 having four sub-block 1s). So while the language of claims 21-23 includes a number of program erase cycles in the list of possible metrics, the list is enumerated in the alternative (“one or more of a number of program erase cycles and” a sub-block identifier), so the claims are anticipated by the reference which shows the sub-block identifiers “sub-block 0” and “sub-block 1”.
CHANDRAMANI shows the claimed first sub-block being associated with a first ordinal range of physical wordlines as sub-block 0 in Fig. 6 with the range of wordlines being wordline 0 to wordline N/2-1. He further shows the claimed second sub-block being associated with a second ordinal range of physical wordlines as sub-block 1 in Fig. 6 with the range of wordlines being wordline N/2 to wordline N-1. This is described at 0059-0060. Sub-block 0 is in a first position in the metablock, and sub-block 1 is in a second position in the metablock, as claimed, as shown in Figs. 6 and 10-12, for example. Wordlines are discussed by CHANDRAMANI at 0030, 0033-0035, 0059-0060, 0070, 0082-0083, and elsewhere.
Regarding claim 3, CHANDRAMANI shows an exemplary block in Fig. 6 comprising two sub-blocks and teaches that each block comprises plural sub-blocks in different planes (abstract). In Fig. 10, CHANDRAMANI shows a metablock logically linking two sub-blocks, as claimed.
Regarding claims 4 and 18, CHANDRAMANI records address information as claimed (see Fig. 7).
Regarding claims 5, 12, and 19, CHANDRAMANI’s device retires sub-blocks as claimed as shown by the “crossed-out” sub-blocks in Figs. 9-13. Retired sub-blocks are shown as bad sub-blocks in Fig. 14 that are blank (white with no pattern inside).
Regarding claims 6, 9, 11, and 20, CHANDRAMANI mentions executing read, write, and erase operations on sub-blocks at 0031.
Regarding claims 7 and 13, CHANDRAMANI’s device repeats the claimed operation on additional sub-blocks as claimed and as shown in Fig. 11, for example, where a single metablock comprises four sub-blocks.
Regarding claim 8, CHANDRAMANI shows the claimed logical linking in Fig. 11, for example.
Regarding claim 14, CHANDRAMANI’s device operating frequency necessarily depends at least in part on the operating state of the device. In other words, his device can identify relinking candidates faster when the storage device is on than when it is off (on and off being different operating states).
Note
It is noted that any citations to specific pages, columns, lines, or figures in the prior art references and any interpretation of the reference should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. See MPEP § 2123.
Conclusion
Any inquiry concerning this Office action should be directed to the Examiner by phone at (571) 272-4214.
Any response to this Office action should be labeled appropriately (including serial number, Art Unit 2132, and type of response) and mailed to Commissioner for Patents, P.O. Box 1450, Alexandria, VA 22313-1450; hand-carried or delivered to the Customer Service Window at the Knox Building, 501 Dulany Street, Alexandria, VA 22314; faxed to (571) 273-8300; or filed electronically using the Patent Center.
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/Kevin Verbrugge/
Kevin Verbrugge
Primary Examiner
Art Unit 2132