DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Email Communication
Applicant is encouraged to authorize the Examiner to communicate with applicant via email by filing form PTO/SB/439 either via USPS, Central Fax, or EFS-Web. See MPEP 502.01, 502.03, 502.05.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-4, 7-10, & 13-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2022/0208464) in view of Nakano et al. (US 2001/0055192).
In regards to claim 1,
Lee ‘464 discloses a multilayer electronic component, comprising:
a body (110 – fig. 1; [0021]) including a dielectric layer (111 – fig. 3; [0021]) and an internal electrode (121 & 122 – fig. 3; [0021]) alternately disposed in a first direction, and including first and second surfaces opposing each other in the first direction, third and fourth surfaces opposing each other in a second direction and connected to the first and second surfaces, and fifth and sixth surfaces opposing each other in a third direction and connected to the first to fourth surfaces (fig. 2; [0021]);
an insulating layer (141 – fig. 3) disposed on the first, second, fifth, and sixth surfaces and including at least one of Al2O3 and BN ([0038]);
an external electrode (131 or 132 – fig. 1; [0021]) disposed on the body. Lee ‘464 fails to disclose wherein each of the first and second surfaces is concave into the body.
Nakano ‘192 discloses a multilayer electronic component, comprising:
a body including a dielectric layer (11 – fig. 1; [0023]) and an internal electrode (12 – fig. 1; [0023]) alternately disposed in a first direction, and including first and second surfaces opposing each other in the first direction, third and fourth surfaces opposing each other in a second direction and connected to the first and second surfaces , and fifth and sixth surfaces opposing each other in a third direction and connected to the first to fourth surfaces (fig. 1-2; [0024]);
an external electrode (21/23 or 22/24 – fig. 1; [0023]) disposed on the body,
wherein each of the first and second surfaces is concave into the body (fig. 2; [0024-0025], table 1, & table 4).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to form the body of Lee ‘464 to have concave surfaces as taught by Nakano ‘192 to obtain a capacitor that is less likely to have delamination and cracking issues.
In regards to claim 2,
Lee ‘464 as modified by Nakano ‘192 further disclose wherein each of the fifth and sixth surfaces (S3 & S4 – fig. 2 of Lee ‘464) is concave into the body (fig. 2; [0024-0025], table 2, & table 4 of Nakano ‘192).
In regards to claim 3,
Lee ‘464 as modified by Nakano ‘192 further disclose wherein each of the third and fourth surfaces (S3 & S4 – fig. 2 of Lee ‘464) is concave into the body (fig. 2; [0024-0025], table 2, & table 4 of Nakano ‘192).
In regards to claim 4,
Lee ‘464 as modified by Nakano ‘192 further disclose wherein the insulating layer extends to at least a portion of the third and fourth surfaces (fig. 3 of Lee ‘464).
In regards to claim 7,
Lee ‘464 as modified by Nakano ‘192 further disclose wherein the dielectric layer includes one or more of BaTiO3, (Ba1-xCax)TiO3 (0<x<1), Ba(Ti1-yCay)O3 (0<y<1), (Ba1-xCax)(Ti1-yZry)O3 (0<x<1, 0<y<1), and Ba(Ti1-yZry)O3 (0<y<1) ([0028] of Lee ‘464).
In regards to claim 8,
Lee ‘464 as modified by Nakano ‘192 further disclose wherein the dielectric layer includes a main component that includes a material having a reduction rate during firing lower than that of the insulating layer ([0028] & [0038] of Lee ‘464).
In regards to claim 9,
Lee ‘464 as modified by Nakano ‘192 further disclose wherein the external electrode is disposed on the third and fourth surface and is disposed on at least a portion of the insulating layer (fig. 3 of Lee ‘464).
In regards to claim 10,
Lee ‘464 as modified by Nakano ‘192 further disclose wherein the external electrode includes an electrode layer (131a or 132a – fig. 3; [0021] of Lee ‘464) connected to the internal electrode and a plating layer ([0050] of Lee ‘464) disposed on the electrode layer, and the insulating layer extends to a region between the electrode layer and the plating layer (fig. 3 of Lee ‘464).
In regards to claim 13,
Lee ‘464 as modified by Nakano ‘192 further disclose wherein, in a cross-section taken in the first and third directions in a center of the multilayer electronic component taken in the second direction, when a minimum size in the first direction is defined as Tc, and a maximum size in the first direction is defined as Te, Tc/Te is less than 1.000 and greater than 0.950 (table 4 – example 18 of Nakano ‘192 Tc/Te=0.982).
In regards to claim 14,
Lee ‘464 as modified by Nakano ‘192 further disclose wherein, in a cross-section taken in the first and third directions in a center of the multilayer electronic component taken in the second direction, when a minimum size in the third direction is defined as Wc, and a maximum size in the third direction is defined as We, Wc/We is less than 1.000 and greater than 0.950 (table 4 – example 18 of Nakano ‘192 Wc/We=0.965).
In regards to claim 15,
Lee ‘464 as modified by Nakano ‘192 further disclose wherein, in a cross-section taken in the first and second directions in a center of the multilayer electronic component taken in the third direction, when a minimum size in the second direction is defined as Lc, and a maximum size in the second direction is defined as Le, Lc/Le is less than 1.000 and greater than 0.950 (table 4 – example 18 of Nakano ‘192 Lc/Le=0.965).
In regards to claim 16,
Lee ‘464 as modified by Nakano ‘192 further disclose wherein the body comprises a material included in the insulating layer in a region adjacent to the insulating layer ([0044-0045] of Lee ‘464 – it is noted that during sintering some of the insulating layer material will diffuse into the ceramic body).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee ‘464 as modified by Nakano ‘192 as applied to claim 1 above, and further in view of Peuser (US 2017/0316878).
In regards to claim 6,
Lee ‘464 as modified by Nakano ‘192 fails to disclose the insulating layer including BN.
Peuser ‘878 discloses an insulating layer (18 – fig. 1-2) disposed on a ceramic body and including Al2O3 or BN ([0028]).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to use BN as taught by Peuser ‘878 to form the insulating layer of Lee ‘464 as modified by Nakano ‘192 as such a combination is a mere substitution of known alternatives as taught by Peuser ‘878. Furthermore, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Claim(s) 17 & 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee ‘464 as modified by Nakano ‘192 as applied to claim 2 & 13 above, and further in view of Kowase (US 2017/0250027).
In regards to claim 17,
Lee ‘464 as modified by Nakano ‘192 further disclose wherein each of the fifth and sixth surfaces (S3 & S4 – fig. 2 of Lee ‘464) is concave into the body (fig. 2; [0024-0025], table 2, & table 4 of Nakano ‘192). Lee ‘464 as modified by Nakano ‘192 fails to disclose wherein each of the third and fourth surfaces is concave into the body.
Kowase discloses wherein each of the third and fourth (end surfaces) surfaces is concave into the body (fig. 2; abstract).
It would have been obvious to one ordinary skill in the art prior to the effective filing date of the claimed invention to form the end surfaces of Lee ‘464 as modified by Nakano ‘192 to be concave as taught by Kowase to obtain a capacitor with good capacitance and delamination characteristics.
In regards to claim 19,
Lee ‘464 as modified by Nakano ‘192 further disclose wherein, in the cross-section taken in the first and third directions in a center of the multilayer electronic component taken in the second direction, when a minimum size in the third direction is defined as Wc, and a maximum size in the third direction is defined as We, Wc/We is less than 1.000 and greater than 0.950 (table 4 – example 18 of Nakano ‘192 Wc/We=0.965). Lee ‘464 as modified by Nakano ‘192 fails to disclose wherein, in a cross-section taken in the first and second directions in a center of the multilayer electronic component taken in the third direction, when a minimum size in the second direction is defined as Lc, and a maximum size in the second direction is defined as Le, Lc/Le is less than 1.000 and greater than 0.950.
Kowase discloses wherein, in a cross-section taken in the first and second directions in a center of the multilayer electronic component taken in the third direction, when a minimum size in the second direction is defined as Lc, and a maximum size in the second direction is defined as Le, Lc/Le is less than 1.000 and greater than 0.950 (fig. 2 & 4; [0067]).
It would have been obvious to one ordinary skill in the art prior to the effective filing date of the claimed invention to form the end surfaces of Lee ‘464 as modified by Nakano ‘192 to be concave as taught by Kowase to obtain a capacitor with good capacitance and delamination characteristics.
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee ‘464 as modified by Nakano ‘192 and Kowase as applied to claim 17 above, and further in view of Peuser ‘878.
In regards to claim 18,
Lee ‘464 as modified by Nakano ‘192 and Kowase fails to disclose the insulating layer including BN.
Peuser ‘878 discloses an insulating layer (18 – fig. 1-2) disposed on a ceramic body and including Al2O3 or BN ([0028]).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to use BN as taught by Peuser ‘878 to form the insulating layer of Lee ‘464 as modified by Nakano ‘192 and Kowase as such a combination is a mere substitution of known alternatives as taught by Peuser ‘878. Furthermore, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Claim(s) 1, 4-5, & 10-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2021/0074481) in view of Nakano ‘192.
In regards to claim 1,
Lee ‘481 discloses a multilayer electronic component, comprising:
a body (110 – fig. 2; [0036]) including a dielectric layer (111 – fig. 2; [0036]) and an internal electrode (121 & 122 – fig. 2; [0036]) alternately disposed in a first direction, and including first and second surfaces opposing each other in the first direction, third and fourth surfaces opposing each other in a second direction and connected to the first and second surfaces, and fifth and sixth surfaces opposing each other in a third direction and connected to the first to fourth surfaces (fig. 1; [0036]);
an insulating layer (140 – fig. 3; [0036]) disposed on the first, second, fifth, and sixth surfaces and including at least one of Al2O3 and BN ([0105-0106]);
an external electrode (131 or 132 – fig. 2; [0036]) disposed on the body. Lee ‘481 fails to disclose wherein each of the first and second surfaces is concave into the body.
Nakano ‘192 discloses a multilayer electronic component, comprising:
a body including a dielectric layer (11 – fig. 1; [0023]) and an internal electrode (12 – fig. 1; [0023]) alternately disposed in a first direction, and including first and second surfaces opposing each other in the first direction, third and fourth surfaces opposing each other in a second direction and connected to the first and second surfaces , and fifth and sixth surfaces opposing each other in a third direction and connected to the first to fourth surfaces (fig. 1-2; [0024]);
an external electrode (21/23 or 22/24 – fig. 1; [0023]) disposed on the body,
wherein each of the first and second surfaces is concave into the body (fig. 2; [0024-0025], table 1, & table 4).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to form the body of Lee ‘481 to have concave surfaces as taught by Nakano ‘192 to obtain a capacitor that is less likely to have delamination and cracking issues.
In regards to claim 4,
Lee ‘481 as modified by Nakano ‘192 further discloses wherein the insulating layer extends to at least a portion of the third and fourth surfaces (fig. 3 of Lee ‘481).
In regards to claim 5,
Lee ‘481 as modified by Nakano ‘192 further discloses wherein the insulating layer is disposed to not cover the internal electrode on the third and the fourth surfaces.
In regards to claim 10,
Lee ‘481 as modified by Nakano ‘192 further discloses wherein the external electrode includes an electrode layer (131a or 132a – fig. 2; [0036] of Lee ‘481) connected to the internal electrode and a plating layer (131c or 132c – fig. 9; [0087-0088] of Lee ‘481) disposed on the electrode layer, and the insulating layer extends to a region between the electrode layer and the plating layer (fig. 9 of Lee ‘481).
In regards to claim 11,
Lee ‘481 as modified by Nakano ‘192 further discloses wherein the electrode layer includes a base electrode layer (131a or 132a – fig. 2; [0036] & [0064] of Lee ‘481) in contact with the internal electrode and including glass, and a conductive resin layer (131b or 132b – fig. 2; [0036] & [0070] of Lee ‘481) including resin disposed on the base electrode layer.
In regards to claim 12,
Lee ‘481 as modified by Nakano ‘192 further discloses wherein the external electrode includes: a base electrode layer (131a or 132a – fig. 2; [0036] & [0064] of Lee ‘481) in contact with the internal electrode and including glass, and a conductive resin layer (131b or 132b – fig. 2; [0036] & [0070] of Lee ‘481) disposed on the base electrode layer and including resin, and the insulating layer extends to a region between the base electrode layer and the conductive resin layer (fig. 2).
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 10,366,834) in view of Peuser ‘878.
In regards to claim 20,
Lee ‘834 discloses a multilayer electronic component, comprising:
a body (110 – fig. 2; C3:L7-36) including a dielectric layer (111 – fig. 2; C3:L7-36)and an internal electrode (121 & 122 – fig. 2; C3:L7-36) alternately disposed in a first direction, and including first and second surfaces opposing each other in the first direction, third and fourth surfaces opposing each other in a second direction and connected to the first and second surfaces , and fifth and sixth surfaces opposing each other in a third direction and connected to the first to fourth surfaces (seen in fig. 1-2);
an insulating layer (143 – fig. 1-2) disposed on the first, second, fifth, and sixth surfaces and including Al2O3 (C3:L7-36 & C6:L40-43); and
an external electrode (161 & 162 – fig. 2; C3:L7-36) disposed on the body. Lee ‘834 fails to disclose the insulating layer including BN.
Peuser ‘878 discloses an insulating layer (18 – fig. 1-2) disposed on a ceramic body and including Al2O3 or BN ([0028]).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to use BN as taught by Peuser ‘878 to form the insulating layer of Lee ‘834 as such a combination is a mere substitution of known alternatives as taught by Peuser ‘878. Furthermore, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2023/0020333 – fig. 1 US 2022/0328251 – fig. 2B
US 2014/0326493 – fig. 2 US 2021/0280374 – fig. 2
JP2004111489A – fig. 1
Communication
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID M SINCLAIR whose telephone number is (571)270-5068. The examiner can normally be reached M-TH from 8AM-4PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Dole can be reached at (571) 272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/David M Sinclair/Primary Examiner, Art Unit 2848