Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The references listed in the Information Disclosure Statement (IDS) filed on 07/02/2024, and have been considered by the examiner (see attached PTO-1449 or PTO/SB/08A and 08B forms).
Drawings
The “Replacement SHEET” of the Drawings filed on 09/17/2024 have been considered.
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the limitation “wherein the second semiconductor chip includes a second-chip first conductive bump that does not overlap the first semiconductor chip, a first sidewall that overlaps the first semiconductor chip, and a second sidewall that does not overlap the first semiconductor chip, wherein the first sidewall and the second sidewall are opposite to each other”, as recited in claim 1 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
To further clarify the Drawings (e.g., Fig. 2A appears to show a first sidewall “CSW1” of the second chip ‘CH2’ does not overlap the first semiconductor chip (CH1), wherein the second sidewall (CSW2) of the second chip ‘CH2’ overlaps the first semiconductor chip (CH1).
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities: please insert “now U.S. Patent No. 12,062,647” after ‘December 5, 2021’.
Appropriate correction is required.
Claim Objections
Claim 3 is objected to because of the following informalities: the phrase, “stacked vias”, appears to lack adequate support elsewhere in the specification. The examiner suggests that more obvious synonym be employed in place of this phrase. Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a
nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-3, are 12-14 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3, 12-14 of U.S. Patent No. 12062647 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because claims of the present application (18/762,255) and claims of the US. Patent No. 12062647 B2 are drawn to the same features and any differences are minor and would have been obvious to one skilled in the art.
The Parent Patent (U.S. Patent No. 12062647) does not claim as follows:
wherein the second via structure is connected to the second chip first conductive bump and the second chip second conductive bump as claimed in claim 4.
wherein the first mold via connects the second chip first conductive bump to the first redistribution substrate as claimed in claim 5.
wherein the first redistribution substrate further includes a second redistribution pattern that connects the first redistribution pattern to the first mold via, wherein the second redistribution pattern is vertically spaced apart from the second-chip first conductive bump” as claimed in claim 6 (and claims 7-11).
wherein the first mold via connects the second chip first conductive bump to the first redistribution substrate” as claimed in claim 15.
Claims 16-20 are allowed.
The following is an examiner’s statement of reasons for allowance: The US Patent (12062647 B2) substantially claims: A semiconductor package, comprising: a first redistribution substrate; a first semiconductor chip disposed on the first redistribution substrate; a first mold layer that covers the first semiconductor chip and the first redistribution substrate; a second redistribution substrate disposed on the first mold layer; a second semiconductor chip disposed on the second redistribution substrate, wherein the second semiconductor chip includes a second-chip first conductive bump that does not overlap the first semiconductor chip”, but does not further claim: “a third semiconductor chip disposed on the second redistribution substrate and spaced apart from the second semiconductor chip, and a first mold via that penetrates the first mold layer, wherein the second semiconductor chip includes a first sidewall and a second sidewall that are opposite to each other, wherein the third semiconductor chip includes a first sidewall and a second sidewall that are opposite to each other, wherein the first wall of the second semiconductor chip and the first wall of the third semiconductor chip overlap the first semiconductor chip, and wherein the second wall of the second semiconductor chip and the second wall of the third semiconductor chip do not overlap the first semiconductor chip” as the present claimed invention.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASMINE J CLARK whose telephone number is (571)272-1726. The examiner can normally be reached 8:30-5.30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, ZANDRA SMITH can be reached at (571) 272 2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JASMINE J CLARK/Primary Examiner, Art Unit 2899