Prosecution Insights
Last updated: April 19, 2026
Application No. 18/762,273

MEMORY CONFIGURATION

Non-Final OA §103
Filed
Jul 02, 2024
Examiner
CHIANG, JASON
Art Unit
2431
Tech Center
2400 — Computer Networks
Assignee
STMicroelectronics
OA Round
1 (Non-Final)
83%
Grant Probability
Favorable
1-2
OA Rounds
2y 9m
To Grant
99%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allow Rate
450 granted / 542 resolved
+25.0% vs TC avg
Strong +29% interview lift
Without
With
+28.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
21 currently pending
Career history
563
Total Applications
across all art units

Statute-Specific Performance

§101
10.7%
-29.3% vs TC avg
§103
57.9%
+17.9% vs TC avg
§102
8.2%
-31.8% vs TC avg
§112
8.9%
-31.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 542 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION This action is in response to the communication filed on 07/02/2024. Claims 1-25 are under examination. The Information Disclosure Statements filed on 07/02/2024 has been entered and considered. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-25 are rejected under 35 U.S.C. 103 as being unpatentable over Kemisetti et al. (US 2024/0220425 A1), Okada (US 6,275,917 B1) and Roozbeh et al. (US 2018/0314453 A1). Regarding claim 1, Kemisetti et al. discloses A method, comprising: configuring a memory for use in executing an application [abs, method for assigning secure memory ranges for applications], the configurating the memory including: defining a set of virtual memory resources associated with one or more contiguous memory areas of the memory [par. 0043, “(i) a range of non-secure virtual memory addresses 316 corresponding to non-secure memory resources 322, and (ii) a range of secure virtual memory addresses 318 corresponding to secure memory resources 320”]; wherein a security attribute assigned to a virtual memory resource indicates the virtual memory resource is a secure memory resource, a non-secure memory resource, or a non-secure callable memory resource [par. 0043, “(i) a range of non-secure virtual memory addresses 316 corresponding to non-secure memory resources 322, and (ii) a range of secure virtual memory addresses 318 corresponding to secure memory resources 320”]; merging contiguous virtual memory resources of the set of virtual memory resources [pars. 0047-0050, increasing secure memory virtual address range (merging contiguous virtual memory resources), “Because the memory command is secure, the UMD 204 may associate a virtual memory address from the secure memory range 318 with the memory command”]. Kemisetti et al. does not explicitly disclose selectively merging contiguous virtual memory resources of the set of virtual memory resources based on respective security attributes of the virtual memory resources of the set of virtual memory resources, generating a merged set of virtual memory resources. However Okada teaches selectively merging contiguous virtual memory resources of the set of virtual memory resources based on respective security attributes of the virtual memory resources of the set of virtual memory resources, generating a merged set of virtual memory resources [col. 4, lines 20-22, “sections having the same memory protection attribute and continuous address space are merged in order to obtain a single section”, also see col. 5, lines 50-62]. Before the effective filing date of the claimed invention, it would have been obvious to a person having ordinary skill in the art to incorporate the teaching of Okada into the teaching of Kemisetti et al. with the motivation such that sections allocated to continuous address space are merged so that it is possible to easily realize memory management as taught by Okada [Okada: col. 4, lines 20-25]. They do not explicitly disclose storing configuration information indicative of the merged set of virtual memory resources. However, Roozbeh et al. teaches storing configuration information indicative of the merged set of virtual memory resources [par. 0070, after memory merging, updating the address translation tables (storing configuration information)]. Before the effective filing date of the claimed invention, it would have been obvious to a person having ordinary skill in the art to incorporate the teaching of Roozbeh et al. into the teaching of Kemisetti et al. and Okada with the motivation such that requests to access to the memory will be redirected to an address range of memory as taught by Roozbeh et al. [Roozbeh et al.: par. 0070]. Regarding claim 2, the rejection of claim 1 is incorporated. Roozbeh et al. further teaches the information indicative of the merged set of virtual memory resources comprises configuration data values for one or more memory ranges of the memory [par. 0070, after memory merging, updating the address translation tables (storing configuration information), requests to access to the shared part of memory will be redirected to an address range (configuration data values) of shared memory]. Before the effective filing date of the claimed invention, it would have been obvious to a person having ordinary skill in the art to incorporate the teaching of Roozbeh et al. into the teaching of Kemisetti et al. and Okada with the motivation such that requests to access to the memory will be redirected to an address range of memory as taught by Roozbeh et al. [Roozbeh et al.: par. 0070]. Regarding claim 3, the rejection of claim 2 is incorporated. Kemisetti et al. further disclose the configuration data values include memory addresses and security attribute values [par. 0043, “(i) a range of non-secure virtual memory address 316 corresponding to non-secure memory resources 322, and (ii) a range of secure virtual memory addresses 318 corresponding to secure memory resources 320”, par. 0049, non-secure page table or secure page table]. Regarding claim 4, the rejection of claim 1 is incorporated. Kemisetti et al. further disclose a security attribute indicating the contiguous virtual memory resources are non-secure memory resources [par. 0043, “a range of non-secure virtual memory address 316 corresponding to non-secure memory resources 322”, par. 0039, “if the command is to non-secure memory, the UMD 204 may determine a 32-bit virtual memory address from a range of 32-bit virtual memory addresses corresponding to non-secure memory resources”]. Okada teaches selectively merging comprises merging contiguous virtual memory resources of the set of virtual memory resources having a same security attribute indicating the contiguous virtual memory resources [col. 4, lines 20-22, “sections having the same memory protection attribute and continuous address space are merged in order to obtain a single section”, also see col. 5, lines 50-62]. Before the effective filing date of the claimed invention, it would have been obvious to a person having ordinary skill in the art to incorporate the teaching of Okada into the teaching of Kemisetti et al. with the motivation such that sections allocated to continuous address space are merged so that it is possible to easily realize memory management as taught by Okada [Okada: col. 4, lines 20-25]. Regarding claim 5, the rejection of claim 4 is incorporated. Kemisetti et al. further disclose a security attribute indicating the contiguous virtual memory resources are non-secure memory resources or non-secure callable memory resources [par. 0043, “a range of non-secure virtual memory address 316 corresponding to non-secure memory resources 322”, par. 0039, “if the command is to non-secure memory, the UMD 204 may determine a 32-bit virtual memory address from a range of 32-bit virtual memory addresses corresponding to non-secure memory resources”]. Okada teaches the selectively merging comprises merging contiguous virtual memory resources of the set of virtual memory resources having security attributes indicating the contiguous virtual memory resources [col. 4, lines 20-22, “sections having the same memory protection attribute and continuous address space are merged in order to obtain a single section”, also see col. 5, lines 50-62]. Regarding claim 6, the rejection of claim 1 is incorporated. Kemisetti et al. further disclose a security attribute indicating the contiguous virtual memory resources are non-secure memory resources or non-secure callable memory resources [par. 0043, “a range of non-secure virtual memory address 316 corresponding to non-secure memory resources 322”, par. 0039, “if the command is to non-secure memory, the UMD 204 may determine a 32-bit virtual memory address from a range of 32-bit virtual memory addresses corresponding to non-secure memory resources”]. Okada teaches the selectively merging comprises merging contiguous virtual memory resources of the set of virtual memory resources having security attributes indicating the contiguous virtual memory resources [col. 4, lines 20-22, “sections having the same memory protection attribute and continuous address space are merged in order to obtain a single section”, also see col. 5, lines 50-62]. Before the effective filing date of the claimed invention, it would have been obvious to a person having ordinary skill in the art to incorporate the teaching of Okada into the teaching of Kemisetti et al. for merging contiguous virtual memory resources of the set of virtual memory resources having security attributes indicating the contiguous virtual memory resources are non-secure memory resources or non-secure callable memory resources, with the motivation such that sections allocated to continuous address space are merged so that it is possible to easily realize memory management as taught by Okada [Okada: col. 4, lines 20-25]. Regarding claim 7, the rejection of claim 6 is incorporated. Kemisetti et al. further disclose the merged contiguous virtual memory resource has a security attribute value indicating the merged contiguous virtual memory resource is a non-secure virtual memory resource [par. 0043, “(i) a range of non-secure virtual memory address 316 corresponding to non-secure memory resources 322, and (ii) a range of secure virtual memory addresses 318 corresponding to secure memory resources 320”, par. 0049, non-secure page table or secure page table]. Regarding claim 8, the rejection of claim 1 is incorporated. Roozbeh et al. further teaches executing the application using the memory and based on the stored configuration information indicative of the merged set of virtual memory resources [par. 0070, after memory merging, updating the address translation tables (storing configuration information), requests to access to the shared part of memory will be redirected to an address range (configuration data values) of shared memory]. Before the effective filing date of the claimed invention, it would have been obvious to a person having ordinary skill in the art to incorporate the teaching of Roozbeh et al. into the teaching of Kemisetti et al. and Okada with the motivation such that requests to access to the memory will be redirected to an address range of memory as taught by Roozbeh et al. [Roozbeh et al.: par. 0070]. Regarding claim 9, it recites limitations like claim 1. The reason for the rejection of claim 1 is incorporated herein. Regarding claim 10, it recites limitations like claim 2. The reason for the rejection of claim 2 is incorporated herein. Regarding claim 11, it recites limitations like claim 3. The reason for the rejection of claim 3 is incorporated herein. Regarding claim 12, it recites limitations like claim 4. The reason for the rejection of claim 4 is incorporated herein. Regarding claim 13, it recites limitations like claim 5. The reason for the rejection of claim 5 is incorporated herein. Regarding claim 14, it recites limitations like claim 6. The reason for the rejection of claim 6 is incorporated herein. Regarding claim 15, it recites limitations like claim 7. The reason for the rejection of claim 7 is incorporated herein. Regarding claim 16, it recites limitations like claim 8. The reason for the rejection of claim 8 is incorporated herein. Regarding claim 17, it recites limitations like claim 1. The reason for the rejection of claim 1 is incorporated herein. Regarding claim 18, the rejection of claim 1 is incorporated. Roozbeh et al. further teaches wherein the processing circuitry, in operation, implements a configuration tool to perform the selective merging and the storing of the configuration information [par. 0035, “in order to provide the memory merging that is adapted to the computer system 100, a Memory Merging Function (MMF) 110 is provided. The MMF 110 may be implemented in SW, HW or partially HW and partially SW”, par. 0070, after memory merging, updating the address translation tables (storing configuration information), requests to access to the shared part of memory will be redirected to an address range (configuration data values) of shared memory]. Before the effective filing date of the claimed invention, it would have been obvious to a person having ordinary skill in the art to incorporate the teaching of Roozbeh et al. into the teaching of Kemisetti et al. and Okada with the motivation such that requests to access to the memory will be redirected to an address range of memory as taught by Roozbeh et al. [Roozbeh et al.: par. 0070]. Regarding claim 19, the rejection of claim 1 is incorporated. Kemisetti et al. further disclose the system comprising the memory [abs, method for assigning secure memory ranges for applications]. Regarding claim 20, the rejection of claim 1 is incorporated. Kemisetti et al. further disclose an integrated circuit including the processing circuitry, the interface, and the memory [par. 0016, integrated circuit hardware, par. 0029, interface, par. 0030, memory]. Regarding claim 21, it recites limitations like claim 1. The reason for the rejection of claim 1 is incorporated herein. Regarding claim 22, it recites limitations like claim 4. The reason for the rejection of claim 4 is incorporated herein. Regarding claim 23, it recites limitations like claim 5. The reason for the rejection of claim 5 is incorporated herein. Regarding claim 24, it recites limitations like claim 6. The reason for the rejection of claim 6 is incorporated herein. Regarding claim 25, the rejection of claim 21 is incorporated. Kemisetti et al. further disclose the contents comprise instructions executed by the processing device [par. 0021, One or more processors in the processing system may execute software. Software can be construed broadly to mean instructions, instruction sets, par. 0022, the functions may be stored on or encoded as one or more instructions or code on a computer-readable medium]. Conclusion The prior art made of record and not relied upon is considered pertinent to Applicant’s disclosure: US 20230168999 A1 USE AFTER FREE DETECTION WITH DOUBLE FREE PROTECTION US 20230161484 A1 DYNAMIC MANAGEMENT OF A MEMORY FIREWALL US 20200073822 A1 Security Configuration For Memory Address Translation From Object Specific Virtual Address Spaces To A Physical Address Space US 9558297 B1 Memory Management Techniques US 20160154593 A1 MEMORY SYSTEM AND A DATA MANAGING METHOD THEREOF US 20150121009 A1 METHOD AND APPARATUS FOR REFORMATTING PAGE TABLE ENTRIES FOR CACHE STORAGE US 20140089626 A1 TECHNIQUES FOR DYNAMIC PHYSICAL MEMORY PARTITIONING US 20110208935 A1 Storing Secure Mode Page Table Data In Secure And Non-Secure Regions Of Memory US 20100223432 A1 MEMORY SHARING AMONG COMPUTER PROGRAMS US 7219206 B1 File System Virtual Memory Descriptor Generation Interface System And Method Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON CHIANG whose telephone number is (571)270-3393. The examiner can normally be reached on 9 AM to 6 PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynn Feild can be reached on (571) 272-2092. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JASON CHIANG/Primary Examiner, Art Unit 2431
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Prosecution Timeline

Jul 02, 2024
Application Filed
Jan 10, 2026
Non-Final Rejection — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
83%
Grant Probability
99%
With Interview (+28.6%)
2y 9m
Median Time to Grant
Low
PTA Risk
Based on 542 resolved cases by this examiner. Grant probability derived from career allow rate.

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