Detailed Office Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Abstract
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The use of thew word “comprises” in the abstract should be avoided.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 5, 7, 11 are rejected under 35 U.S.C. 103 as being unpatentable over Tsen et al. (US Patent Number 11,588,482) in view of Weng et al. (US Patent Number 11,502,695) and Alhoshany et al. (US Patent Number 11,265,008).
Regarding claim 1, Tsen et al. disclose a sample-and-hold circuit (figs. 1A, 1B) comprising: a first differential input terminal (the line that feeds 115 in figs. 1A, 1B, top part) ; a second differential input terminal (the line that feeds 115 in figs. 1A, 1B, bottom part); a first unity gain buffer (135, figs. 1A, 1B) configured to receive the first differential input voltage from the first differential input terminal and to output a first differential output voltage to a first differential output terminal (figs. 1A, 1B; column 4, lines 25 – 27); a second unity gain buffer (135, figs. 1A, 1B) configured to receive the second differential input voltage from the second differential input terminal and to output a second differential output voltage to a second differential output terminal (figs. 1A, 1B; column 4, lines 25 – 27); an amplifier (155, figs. 1A, 1B)
but do not disclose
a sample and hold circuit that comprise an amplifier configured to compare received voltages and amplifying results of the comparison, wherein the amplifier is configured to generate a feedback voltage, which regulates outputs of the first and second unity gain buffers based on a common mode voltage that is provided from the first and second unity gain buffers and a reference voltage.
However, Weng et al., in the same field of endeavor, disclose a signal processing circuit (figs. 1, 3) comprises an amplifier (comparator) (3300, fig. 3) configured to compare received voltages and amplifying results of the comparison, wherein the amplifier is configured to generate a feedback voltage, which regulates outputs of the first and second unity gain buffers based on a common mode voltage that is provided from the first and second unity gain buffers and a reference voltage (see fig. 3).
Therefore, it would have been obvious to one of ordinary skill in the art at the time of the effective filing of the invention to modify Tsen et al.’s multiplexing sample and hold circuit with that of Weng et al. in order to improve the performance of the sample and hold circuit.
Moreover, both Tsen et al. and Weng et al. do not specifically disclose a sample and hold circuit that comprises a first differential input terminal configured to receive a first differential input voltage among differential input voltages; a second differential input terminal configured to receive a second differential input voltage among the differential input voltages, which is different from the first differential input voltage.
However, Alhoshany et al., in the same field of endeavor, disclose a circuitry (fig. 4) that comprises a sample and hold circuit (410, fig. 4) that comprises a first differential input terminal configured to receive a first differential input voltage among differential input voltages (column 9, lines 48 – 58); a second differential input terminal configured to receive a second differential input voltage among the differential input voltages, which is different from the first differential input voltage (column 9, lines 48 – 58).
Therefore, it would have been obvious to one of ordinary skill in the art at the time of the effective filing of the invention to modify Tsen et al. and Weng et al.’s device with that of Alhoshany et al. to improve the performance of the sample and hold circuit.
Regarding claim 11, Tsen et al. disclose a sample-and-hold circuit (figs. 1A, 1B) comprising: a first differential input terminal (the line that feeds 115 in figs. 1A, 1B, top part) ; a second differential input terminal (the line that feeds 115 in figs. 1A, 1B, bottom part); a first unity gain buffer (135, figs. 1A, 1B) configured to receive the first differential input voltage from the first differential input terminal and to output a first differential output voltage to a first differential output terminal (figs. 1A, 1B; column 4, lines 25 – 27); a second unity gain buffer (135, figs. 1A, 1B) configured to receive the second differential input voltage from the second differential input terminal and to output a second differential output voltage to a second differential output terminal (figs. 1A, 1B; column 4, lines 25 – 27); a first feedback switch (140, fig. 1A) having one terminal connected to an output terminal of the first unity gain buffer (135); a second feedback switch (140, figs. 1A, 1B ) having one terminal connected to an output terminal of the second unity gain buffer (135) and the other terminal connected to the first feedback switch (figs. 1A, 1B); and an amplifier (155, figs. 1A, 1B) having a first input terminal connected to the first and second feedback switches (figs. 1A, 1B), but do not disclose a sample and hold circuit where a second input terminal receiving a reference voltage, and an output terminal outputting a feedback voltage that regulates outputs of the first and second unity gain buffers. However, Weng et al., in a related art, disclose sample and hold circuit (fig. 1) that comprise an amplifier (comparator) wherein a reference voltage is connected at an input of the amplifier (fig. 1). Therefore, it would have been obvious to one of ordinary skill in the art at the time of the effective filing of the invention to modify Tsen et al.’s multiplexing sample and hold circuit with that of Weng et al. in order to improve the performance of the sample and hold circuit.
Moreover, both Tsen et al. and Weng et al. disclose all the limitations discussed above except a sample and hold where the second differential input is different from the first differential input voltage. However, Alhoshany et al., in the same field of endeavor, disclose a circuitry (fig. 4) that comprises a sample and hold circuit (410, fig. 4) that comprises a first differential input terminal configured to receive a first differential input voltage among differential input voltages (column 9, lines 48 – 58); a second differential input terminal configured to receive a second differential input voltage among the differential input voltages, which is different from the first differential input voltage (column 9, lines 48 – 58). Therefore, it would have been obvious to one of ordinary skill in the art at the time of the effective filing of the invention to modify Tsen et al. and Weng et al.’s device with that of Alhoshany et al. to improve the performance of the sample and hold circuit.
Regarding claim 2, Tsen et al. disclose a sample-and-hold circuit (figs. 1A, 1B) further comprising: a first sampling switch (115, top switch) configured to connect to the first differential input terminal and the first unity gain buffer (135) during a first phase and to disconnect from the first differential input terminal and the first unity gain buffer during a second phase (see figs. 1A, 1B); and a second sampling switch (115, bottom part) configured to connect to the second differential input terminal and the second unity gain buffer (135) during the first phase and to disconnect from the second differential input terminal and the second unity gain buffer during the second phase (see figs. 1A, 1B).
Regarding claim 3, Tsen et al. disclose a sample-and-hold circuit (figs. 1A, 1B), further comprising: a first sampling capacitor (130, the top capacitor) connected between the first sampling switch and the first unity gain buffer; and a second sampling capacitor (130, the bottom capacitor) connected between the second sampling switch and the second unity gain buffer.
Regarding claim 4, Tsen et al. disclose a sample-and-hold circuit (figs. 1A, 1B) wherein the sample-and-hold circuit is configured to sample the differential input voltages to the first and second sampling capacitors (130) during the first phase, the first sampling capacitor is configured to provide a first sampled differential input voltage to the first unity gain buffer during the second phase, and the second sampling capacitor (130) is configured to provide a second sampled differential input voltage to the second unity gain buffer during the second phase (figs. 1A, 1B).
Regarding claim 5, Tsen et al. disclose a sample-and-hold circuit (figs. 1A, 1B) further comprising: a first feedback switch (140) connected in series to the first unity gain buffer; and a second feedback switch (140) connected in series to the second unity gain buffer and the first feedback switch.
Regarding claim 7, Tsen et al. disclose a sample-and-hold circuit (figs. 1A, 1B), wherein the first and second unity gain buffers are configured to receive the feedback voltage (figs. 1A, 1B).
Regarding claim 12, Tsen et al. disclose a sample-and-hold circuit (figs. 1A, 1B), further comprising: a first sampling switch (115) connected between the first differential input terminal (the input signal) and the first unity gain buffer (135); and a second sampling switch (115) connected between the second differential input terminal (the input signal) and the second unity gain buffer (135).
Regarding claim 13, Tsen et al. disclose a sample-and-hold circuit (figs. 1A, 1B), further comprising: a first sampling capacitor (130) connected between the first sampling switch (115) and the first unity gain buffer (135); and a second sampling capacitor (130) connected between the second sampling switch (115) and the second unity gain buffer (135).
Regarding claim 15, Tsen et al. disclose a sample-and-hold circuit (figs. 1A, 1B),, wherein the output terminal of the amplifier is connected to the first and second unity gain buffers (figs. 1A, 1B).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Gorecki et al. (USPGPUB 2016/0352372) in view of Tsen et al. (US Patent Number 11,588,482), and Alhoshany et al. (US Patent Number 11,265,008).
Regarding claim 18, Gorecki et al. an analog-to-digital converter (ADC) circuit (fig. 2A) comprising: a plurality of sub-ADCs (118, fig. 2A) configured to convert analog signals into digital signals in a time-interleaving method; and a sample-and-hold circuit (116, fig. 2A)
but do not disclose
an analog to digital converter that comprises a sample and hold that is configured to repeatedly sample and buffer a first differential input voltage among differential input voltages by using a first unity gain buffer, and repeatedly sample and buffer a second differential input voltage among the differential input voltages, wherein the second differential input voltage is different from the first differential input voltage by using a second unity gain buffer, wherein in response to the first and second differential input voltages being sampled, the sample-and-hold circuit is configured to input a common mode voltage generated from the first and second differential input voltages by the first and second unity gain buffers, to an amplifier and to regulate outputs of the first and second unity gain buffers based on the common mode voltage and a reference voltage, and in response to the first and second differential input voltages being buffered, the sample-and-hold circuit is configured to provide the regulated outputs of the first and second unity gain buffers to the sub-ADCs.
However, Tsen et al., in the same field of endeavor, disclose a multiplexing sample and hold circuit (figs. 1A, 1B) is configured to repeatedly sample and buffer a first differential input voltage among differential input voltages by using a first unity gain buffer (col. 3, line 63 to col. 4, line 33), and repeatedly sample and buffer a second differential input voltage among the differential input voltages second differential input voltages being sampled (col. 3, line 63 to col. 4, line 33), the sample-and-hold circuit is configured to input a common mode voltage (105, fig. 1A, 1B) generated from the first and second differential input voltages by the first and second unity gain buffers (135) , to an amplifier and to regulate outputs of the first and second unity gain buffers based on the common mode voltage and a reference voltage, and in response to the first and second differential input voltages being buffered (col. 3, line 63 to col. 4, line 33).
Therefore, it would have been obvious to one of ordinary skill in the art at the time of the effective filing of the invention to modify Gorecki et al.’s system with that of Tsen et al. to improve the performance of the sample and hold circuit.
Moreover, both Gorecki et al. and Tsen et al. combined disclose all the limitations discussed above except the analog to digital converter wherein the sample and hold circuit comprises a second differential input voltage is different from the first differential input voltage.
However, Alhoshany et al., in the same field of endeavor, disclose a system (fig. 4) that comprises a sample and hold circuit (410) comprises a second differential input voltage is different from the first differential input voltage (col. 9, lines 48 – 58). Therefore, it would have been obvious to one of ordinary skill in the art at the time of the effective filing of the invention to modify Gorecki et al.’s system combined with that of Tsen et al. and Alhoshany et al. to improve the performance of the sample and hold circuit.
Allowable Subject Matter
Claims 6, 8, 9, 10, 14, 16, 17, 19, 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/JEAN B JEANGLAUDE/Primary Examiner, Art Unit 2845