DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is in response to Application 18/762284 filed on July 2, 2024 in which Claims 1-30 are presented for examination.
Status of Claims
Claims 1-30 are pending, of which claims 1-30 are rejected under 103.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 7, 17-19, 21, 22, 24 and 28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kariya (US Patent Application 2021/0202328) in view of Chang (US Patent Application 2010/0281342).
Claim 1, Kariya teaches a method, comprising: receiving, at a logic block of a first semiconductor die of a semiconductor system a command to read a data segment stored at the semiconductor system (View Kariya ¶ 2, 17, 22; receive read command; semiconductor devices; data to be read from the memory cells of the memory cell array 145 to determine whether the read data matches the written data), the semiconductor system comprising a plurality of memory arrays of a set of one or more second semiconductor dies coupled with the first semiconductor die (View Kariya Fig. 2, Components 214 (1) – (3), ¶ 22, 29; memory cell arrays); detecting an error in the data segment based on receiving the command to read the data segment (View Kariya ¶ 22; mBIST circuit may detect defects in the memory cell array by causing data to be written to memory cells of the memory cell array, and then causing data to be read from the memory cells of the memory cell array to determine whether the read data matches the written data).
Kariya does not explicitly teach retrieving, at the logic block based on detecting the error in the data segment, a plurality of data segments of a data set that includes the data segment, each of the plurality of data segments retrieved from a respective first memory array of the plurality of memory arrays; retrieving, at the logic block based on detecting the error in the data segment, parity information associated with the data set, the parity information retrieved from one or more respective second memory arrays of the plurality of memory arrays; and correcting, at the logic block, the error in the data segment based on the parity information and the plurality of data segments of the data set.
However, Chang teaches retrieving, at the logic block based on detecting the error in the data segment, a plurality of data segments of a data set that includes the data segment, each of the plurality of data segments retrieved from a respective first memory array of the plurality of memory arrays (View Chang ¶ 18, 75, 84; retrieve read data stored on a page basis in the memory cell array during a read operation); retrieving, at the logic block based on detecting the error in the data segment, parity information associated with the data set, the parity information retrieved from one or more respective second memory arrays of the plurality of memory arrays (View Chang ¶ 18, 75; plurality N parities derived from the plurality of N segments); and correcting, at the logic block, the error in the data segment based on the parity information and the plurality of data segments of the data set (View Chang ¶ 18, 75; perform error correction).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to modify Kariya with retrieving, at the logic block based on detecting the error in the data segment, a plurality of data segments of a data set that includes the data segment, each of the plurality of data segments retrieved from a respective first memory array of the plurality of memory arrays; retrieving, at the logic block based on detecting the error in the data segment, parity information associated with the data set, the parity information retrieved from one or more respective second memory arrays of the plurality of memory arrays; and correcting, at the logic block, the error in the data segment based on the parity information and the plurality of data segments of the data set since it is known in the art that data segments can be corrected (View Chang ¶ 18, 75, 84). Such modification would have allowed multiple parities to correct multiple data segments.
Claim 7, most of the limitations of this claim has been noted in the rejection of Claim 1. Chang further teaches outputting the data segment from the logic block based on correcting the error (View Chang ¶ 7, 18; correct detected error, resume transmission of read data).
Claim 17, Kariya teaches a method, comprising: receiving, at a logic block of a first semiconductor die of a semiconductor system, a command to read a data segment stored at the semiconductor system (View Kariya ¶ 2, 17, 22; receive read command, semiconductor devices), the semiconductor system comprising a plurality of memory arrays of a set of one or more second semiconductor dies coupled with the first semiconductor die (View Kariya fig. 2, Components 214 (1) – (3), ¶ 22, 29; memory cell arrays).
Kariya does not explicitly teach retrieving, at the logic block based on receiving the command, a plurality of data segments of a data set that includes the data segment, each of the plurality of data segments retrieved from a respective first memory array of the plurality of memory arrays; retrieving, at the logic block based on receiving the command, error correction information associated with the data set, the error correction information retrieved from one or more respective second memory arrays of the plurality of memory arrays; and performing, at the logic block, an error control operation on the data set based on the error correction information.
However, Chang teaches retrieving, at the logic block based on receiving the command, a plurality of data segments of a data set that includes the data segment, each of the plurality of data segments retrieved from a respective first memory array of the plurality of memory arrays (View Chang ¶ 18, 75; retrieve read data stored on a page basis in the memory cell array during a read operation, wherein the page of read data comprises a plurality of N segments); retrieving, at the logic block based on receiving the command, error correction information associated with the data set, the error correction information retrieved from one or more respective second memory arrays of the plurality of memory arrays (View Chang ¶ 18, 75; plurality N parities derived from the plurality of N segments); and performing, at the logic block, an error control operation on the data set based on the error correction information (View Chang ¶ 18, 75; perform an error detection and correction operation on the read data on the segment by segment basis for each one of the plurality of N segments).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to modify Kariya with retrieving, at the logic block based on receiving the command, a plurality of data segments of a data set that includes the data segment, each of the plurality of data segments retrieved from a respective first memory array of the plurality of memory arrays; retrieving, at the logic block based on receiving the command, error correction information associated with the data set, the error correction information retrieved from one or more respective second memory arrays of the plurality of memory arrays; and performing, at the logic block, an error control operation on the data set based on the error correction information since it is known in the art that data segments can be corrected (View Chang ¶ 18, 75, 84). Such modification would have allowed multiple parities to correct multiple data segments.
Claim 18, most of the limitations of this claim has been noted in the rejection of Claim 17. Chang further teaches retrieving second error control information associated with the data segment from the respective first memory array of the plurality of memory arrays (View Chang ¶ 53, 54; respective parity data sets (or “parities") may be generated by operation of the controller in relation to the respective segments); and performing a second error control operation on the data segment based on second error control information associated with the data segment based on retrieving the data segment (View Chang ¶ 18, 53, 63, 75; perform an error detection and correction operation on the read data on the segment by segment basis for each one of the plurality of N segments).
Claim 19, most of the limitations of this claim has been noted in the rejection of Claim 17. Chang further teaches the error correction information comprises a plurality of portions (View Chang ¶ 53, 54; respective parity data sets (or “parities") may be generated by operation of the controller in relation to the respective segments). Kariya further teaches each portion of the plurality of portions stored at a respective second semiconductor die of the set of one or more second semiconductor dies (View Kariya Fig. 2, Component 210 (1) – (3); ¶ 28, 29; semiconductor dies).
Claim 20, most of the limitations of this claim has been noted in the rejection of Claim 17. Kariya further teaches each of the plurality of data segments is stored at a respective second semiconductor die of the set of one or more second semiconductor dies (View Kariya Fig. 2, Component 210 (1) – (3); ¶ 28, 29; semiconductor dies).
Claim 21, most of the limitations of this claim has been noted in the rejection of Claim 17. Chang further teaches outputting the data segment from the logic block based on performing the error control operation (View Chang ¶ 7, 18; correct detected error, resume transmission of read data).
Claim 24, Kariya teaches a system, comprising: a set of one or more second semiconductor dies of a semiconductor system (View Kariya ¶ 2, 10, 11; multiple semiconductor devices; multiple semiconductor die), the set of one or more second semiconductor dies comprising a plurality of memory arrays (View Kariya fig. 2, Components 214 (1) – (3), ¶ 22, 29; memory cell arrays); and a first semiconductor die of the semiconductor system coupled with the set of one or more second semiconductor dies (View Kariya ¶ 10, 11, 26; multiple semiconductor die are interconnected via the scribe lines, the multiple semiconductor die may share common I/O buses), the first semiconductor die comprising a logic block configured to: receive a command to read a data segment from the semiconductor system (View Kariya ¶ 2, 17, 22; receive read command; semiconductor devices; data to be read from the memory cells of the memory cell array to determine whether the read data matches the written data); detect an error in the data segment based on receiving the command to read the data segment (View Kariya ¶ 22; mBIST circuit may detect defects in the memory cell array by causing data to be written to memory cells of the memory cell array, and then causing data to be read from the memory cells of the memory cell array to determine whether the read data matches the written data).
Kariya does not explicitly teach retrieve, based on detecting the error in the data segment, a plurality of data segments of a data set that includes the data segment, each of the plurality of data segments retrieved from a respective first memory array of the plurality of memory arrays; retrieve, based on detecting the error in the data segment, parity information associated with the data set, the parity information retrieved from one or more respective second memory arrays of the plurality of memory arrays; and correct the error in the data segment based on the parity information and the plurality of data segments of the data set.
However, Chang teaches retrieve, based on detecting the error in the data segment, a plurality of data segments of a data set that includes the data segment, each of the plurality of data segments retrieved from a respective first memory array of the plurality of memory arrays (View Chang ¶ 18, 75, 84; retrieve read data stored on a page basis in the memory cell array during a read operation); retrieve, based on detecting the error in the data segment, parity information associated with the data set, the parity information retrieved from one or more respective second memory arrays of the plurality of memory arrays (View Chang ¶ 18, 75; plurality N parities derived from the plurality of N segments); and correct the error in the data segment based on the parity information and the plurality of data segments of the data set (View Chang ¶ 18, 53, 63, 75; perform an error detection and correction operation on the read data on the segment by segment basis for each one of the plurality of N segments and a corresponding plurality of N parities respectively derived from the plurality of N segments).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to modify Kariya with retrieve, based on detecting the error in the data segment, a plurality of data segments of a data set that includes the data segment, each of the plurality of data segments retrieved from a respective first memory array of the plurality of memory arrays; retrieve, based on detecting the error in the data segment, parity information associated with the data set, the parity information retrieved from one or more respective second memory arrays of the plurality of memory arrays; and correct the error in the data segment based on the parity information and the plurality of data segments of the data set since it is known in the art that data segments can be corrected (View Chang ¶ 18, 75, 84). Such modification would have allowed multiple parities to correct multiple data segments.
Claim 28, Kariya teaches a system, comprising: a set of one or more second semiconductor dies of a semiconductor system (View Kariya ¶ 2, 10, 11; multiple semiconductor devices; multiple semiconductor die), the set of one or more second semiconductor dies comprising a plurality of memory arrays (View Kariya fig. 2, Components 214 (1) – (3), ¶ 22, 29; memory cell arrays); and a first semiconductor die of the semiconductor system coupled with the set of one or more second semiconductor dies (View Kariya ¶ 10, 11, 26; multiple semiconductor die are interconnected via the scribe lines, the multiple semiconductor die may share common I/O buses), the first semiconductor die comprising a logic block configured to: receive a command to read a data segment stored at the semiconductor system (View Kariya ¶ 2, 17, 22; receive read command; semiconductor devices; data to be read from the memory cells of the memory cell array to determine whether the read data matches the written data).
Kariya does not explicitly teach retrieve, based on receiving the command, a plurality of data segments of a data set that includes the data segment, each of the plurality of data segments retrieved from a respective first memory array of the plurality of memory arrays; retrieve, based on receiving the command, error correction information associated with the data set, the error correction information retrieved from one or more respective second memory arrays of the plurality of memory arrays; and perform an error control operation on the data set based on the error correction information.
However, Chang teaches retrieve, based on receiving the command, a plurality of data segments of a data set that includes the data segment, each of the plurality of data segments retrieved from a respective first memory array of the plurality of memory arrays (View Chang ¶ 18, 75, 84; retrieve read data stored on a page basis in the memory cell array during a read operation); retrieve, based on receiving the command, error correction information associated with the data set, the error correction information retrieved from one or more respective second memory arrays of the plurality of memory arrays (View Chang ¶ 18, 75; plurality N parities derived from the plurality of N segments); and perform an error control operation on the data set based on the error correction information View Chang ¶ 18, 53, 63, 75; perform an error detection and correction operation on the read data on the segment by segment basis for each one of the plurality of N segments and a corresponding plurality of N parities respectively derived from the plurality of N segments).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to modify Kariya with retrieve, based on receiving the command, a plurality of data segments of a data set that includes the data segment, each of the plurality of data segments retrieved from a respective first memory array of the plurality of memory arrays; retrieve, based on receiving the command, error correction information associated with the data set, the error correction information retrieved from one or more respective second memory arrays of the plurality of memory arrays; and perform an error control operation on the data set based on the error correction information since it is known in the art that data segments can be corrected (View Chang ¶ 18, 75, 84). Such modification would have allowed multiple parities to correct multiple data segments.
Claim(s) 2-4, 23, 25-27, 29 and 30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kariya (US Patent Application 2021/0202328) in view of Chang (US Patent Application 2010/0281342) and further in view of D’Abreu (US Patent Application 2013/0003480).
Claim 2, most of the limitations of this claim has been noted in the rejection of Claim 1. The combination of teachings above does not explicitly teach the first semiconductor die comprises a plurality of interface blocks coupled with the logic block that are each operable to access or more respective memory arrays of the plurality of memory arrays.
However, D’Abreu teaches the first semiconductor die comprises a plurality of interface blocks coupled with the logic block that are each operable to access or more respective memory arrays of the plurality of memory arrays (View D’Abreu ¶ 23, 46; the first periphery die may include a NAND smart bridge that includes control logic, a first ECC engine, a second ECC engine, a first core interface, and a second core interface).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to modify the combination of teachings with the first semiconductor die comprises a plurality of interface blocks coupled with the logic block that are each operable to access or more respective memory arrays of the plurality of memory arrays since it is known in the art that a plurality of interfaces can be used (View D’Abreu ¶ 23, 46). Such modification would have allowed memory arrays to have multiple interfaces.
Claim 25 is the system corresponding to the method of Claim 2 and is therefore rejected under the same reasons set forth in the rejection of Claim 2.
Claim 29 is the system corresponding to the method of Claim 2 and is therefore rejected under the same reasons set forth in the rejection of Claim 2.
Claim 3, most of the limitations of this claim has been noted in the rejection of Claim 2. Chang further teaches retrieving the plurality of data segments comprises retrieving each of the plurality of data segments from the respective first memory array of the plurality of memory arrays via a respective first interface block of the plurality of interface blocks (View Chang ¶ 18, 75, 84; retrieve read data stored on a page basis in the memory cell array during a read operation, wherein the page of read data comprises a plurality of N segments); and retrieving the parity information comprises retrieving the parity information from the one or more respective second memory arrays of the plurality of memory arrays via one or more respective second interface blocks of the plurality of interface blocks (View Chang ¶ 18, 75; retrieve read data stored on a page basis in the memory cell array during a read operation, wherein the page of read data comprises a plurality of N segments and a corresponding plurality of N parities respectively derived from the plurality of N segments).
Claim 26 is the system corresponding to the method of Claim 3 and is therefore rejected under the same reasons set forth in the rejection of Claim 3.
Claim 30 is the system corresponding to the method of Claim 3 and is therefore rejected under the same reasons set forth in the rejection of Claim 3.
Claim 4, most of the limitations of this claim has been noted in the rejection of Claim 2. Chang further teaches performing, by an interface block of the plurality of interface blocks, an error control operation on the data segment based on error control information associated with the data segment, wherein detecting the error in the data segment is based on performing the error control operation (View Chang ¶ 65; control unit runs an ECC operation on the read data received from the flash memory on a second unit (e.g., a segment) basis, smaller than the first unit (e.g., page) basis).
Claim 27 is the system corresponding to the method of Claim 7 and is therefore rejected under the same reasons set forth in the rejection of Claim 7.
Claim 22, most of the limitations of this claim has been noted in the rejection of Claim 17. The combination of teachings above does not explicitly teach the first semiconductor die comprises a plurality of interface blocks coupled with the logic block that are each operable to access or more respective memory arrays of the plurality of memory arrays.
However, D’Abreu teaches the first semiconductor die comprises a plurality of interface blocks coupled with the logic block that are each operable to access or more respective memory arrays of the plurality of memory arrays (View D’Abreu ¶ 23, 46; the first periphery die may include a NAND smart bridge that includes control logic, a first ECC engine, a second ECC engine, a first core interface, and a second core interface).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to modify the combination of teachings with the first semiconductor die comprises a plurality of interface blocks coupled with the logic block that are each operable to access or more respective memory arrays of the plurality of memory arrays since it is known in the art that a plurality of interfaces can be used (View D’Abreu ¶ 23, 46). Such modification would have allowed data segments to have multiple interfaces.
Claim 23, most of the limitations of this claim has been noted in the rejection of Claim 22. Chang further teaches retrieving the plurality of data segments comprises retrieving each of the plurality of data segments from the respective first memory array of the plurality of memory arrays via a respective first interface block of the plurality of interface blocks (View Chang ¶ 18, 75, 84; retrieve read data stored on a page basis in the memory cell array during a read operation, wherein the page of read data comprises a plurality of N segments); and retrieving the error correction information comprises retrieving the error correction information from the one or more respective second memory arrays of the plurality of memory arrays via one or more respective second interface blocks of the plurality of interface blocks (View Chang ¶ 18, 75; retrieve read data stored on a page basis in the memory cell array during a read operation, wherein the page of read data comprises a plurality of N segments and a corresponding plurality of N parities respectively derived from the plurality of N segments).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kariya (US Patent Application 2021/0202328) in view of Chang (US Patent Application 2010/0281342) and further in view of Sunwoo (US Patent Application 2017/0293449).
Claim 5, most of the limitations of this claim has been noted in the rejection of Claim 1. The combination of teachings above does not explicitly teach receiving, at the logic block, a second command to read a second data segment stored at semiconductor system; retrieving, at the logic block, the second data segment based on receiving the second command; suppressing, at the logic block, retrieving a second data set comprising the second data segment and parity information associated with the second data set based on not detecting an error in the second data segment; and outputting the second data segment from the logic block.
However, Sunwoo teaches receiving, at the logic block, a second command to read a second data segment stored at semiconductor system (View Sunwoo ¶ 73, 97; the read mode signal RD_MODE is activated, the selection circuit may select and output the contents of the second register); retrieving, at the logic block, the second data segment based on receiving the second command (View Sunwoo ¶ 7, 9, 62; a plurality of second segments having a programmed information defining a programmed segment from the plurality of first segments); suppressing, at the logic block, retrieving a second data set comprising the second data segment and parity information associated with the second data set based on not detecting an error in the second data segment (View Sunwoo ¶ 82, 83, 90; the control logic may generate the signals for determining whether to operate the randomizer and the error correction); and outputting the second data segment from the logic block (View Sunwoo ¶ 90, 102; the error-corrected data may be programmed in the memory cell array ).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to modify the combination of teachings with receiving, at the logic block, a second command to read a second data segment stored at semiconductor system; retrieving, at the logic block, the second data segment based on receiving the second command; suppressing, at the logic block, retrieving a second data set comprising the second data segment and parity information associated with the second data set based on not detecting an error in the second data segment; and outputting the second data segment from the logic block since it is known in the art that data can be output to a memory array (View Sunwoo ¶ 81, 90, 102). Such modification would have allowed corrected data segments to be suppressed.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kariya (US Patent Application 2021/0202328) in view of Chang (US Patent Application 2010/0281342) and further in view of Swenson (US Patent 8,464,093).
Claim 6, most of the limitations of this claim has been noted in the rejection of Claim 1. The combination of teachings above does not explicitly teach performing an Exclusive-OR operation using the parity information and the data set, wherein correcting the error is based on performing the Exclusive-OR operation.
However, Swenson teaches performing an Exclusive-OR operation using the parity information and the data set, wherein correcting the error is based on performing the Exclusive-OR operation (View Swenson Col. 1, Lines 31-45; parity checking perform exclusive OR operation).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to modify the combination of teachings with performing an Exclusive-OR operation using the parity information and the data set, wherein correcting the error is based on performing the Exclusive-OR operation since it is known in the art that an XOR operation can be performed (View Swenson Col. 1, Lines 31-45). Such modification would have allowed a data segment to be corrected.
Claim(s) 8 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kariya (US Patent Application 2021/0202328) in view of Madan (US Patent Application 2011/0035644).
Claim 8, Kariya teaches a method, comprising: receiving, at a logic block of a first semiconductor die of a semiconductor system, a command to write a data segment at the semiconductor system (View Kariya ¶ 18; when the write command is issued and a row address and a column address are timely supplied with the write command, and then the input/output circuit may receive write data at the data terminals), the semiconductor system comprising a plurality of memory arrays of a set of one or more second semiconductor dies coupled with the first semiconductor die (View Kariya Fig. 2, Components 214 (1) – (3), ¶ 22, 29; memory cell arrays).
Kariya does not explicitly teach modifying, by the logic block, parity information stored at a first memory array of the plurality of memory arrays, the parity information associated with a plurality of data segments of a data set that includes the data segment, each of the plurality of data segments stored at a respective second memory array of the plurality of memory arrays; and modifying, by the logic block, the data set to include the data segment based on writing the data segment to a second memory array of the plurality of memory arrays.
However, Madan teaches modifying, by the logic block, parity information stored at a first memory array of the plurality of memory arrays, the parity information associated with a plurality of data segments of a data set that includes the data segment, each of the plurality of data segments stored at a respective second memory array of the plurality of memory arrays (View Madan ¶ 61; ECC logic generates new values of ECC bits for data word using the input bytes received in process and the contents of data word that are not being written (and thus remain in buffer). Following process, buffer contains the contents of data word to be written to the selected row in the selected memory array block, including any modified data bits or bytes and the new value of the ECC bits generated in process); and modifying, by the logic block, the data set to include the data segment based on writing the data segment to a second memory array of the plurality of memory arrays (View Madan ¶ 61; ECC logic generates new values of ECC bits for data word using the input bytes received in process and the contents of data word that are not being written (and thus remain in buffer). Following process, buffer contains the contents of data word to be written to the selected row in the selected memory array block, including any modified data bits or bytes and the new value of the ECC bits generated in process).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to modify Kariya with modifying, by the logic block, parity information stored at a first memory array of the plurality of memory arrays, the parity information associated with a plurality of data segments of a data set that includes the data segment, each of the plurality of data segments stored at a respective second memory array of the plurality of memory arrays; and modifying, by the logic block, the data set to include the data segment based on writing the data segment to a second memory array of the plurality of memory arrays since it is known in the art that parity data can be modified (View Madan ¶ 61). Such modification would have allowed parity data to be modified to correct data.
Claim 13, most of the limitations of this claim has been noted in the rejection of Claim 8. Kariya further teaches each of the plurality of data segments is stored at a respective second semiconductor die of the set of one or more second semiconductor dies (View Kariya Fig. 2, Component 210 (1) – (3); ¶ 28, 29; semiconductor dies).
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kariya (US Patent Application 2021/0202328) in view of Madan (US Patent Application 2011/0035644) and further in view of Chang (US Patent Application 2010/0281342).
Claim 9, most of the limitations of this claim has been noted in the rejection of Claim 8. Madan further teaches generating, at the logic block, second parity information for the data set based on the parity information and the data segment (View Madan ¶ 61; ECC logic generates new values of ECC bits for data word); and writing the second parity information to the first memory array (View Madan ¶ 61; ECC logic generates new values of ECC bits for data word using the input bytes received in process and the contents of data word that are not being written (and thus remain in buffer). Following process, buffer contains the contents of data word to be written to the selected row in the selected memory array block, including any modified data bits or bytes and the new value of the ECC bits generated in process).
The combination of teachings above does not explicitly teach modifying the parity information comprises: retrieving, at the logic block, the parity information from the first memory array.
However, Chang teaches modifying the parity information comprises: retrieving, at the logic block, the parity information from the first memory array (View Chang ¶ 18, 75; plurality N parities derived from the plurality of N segments).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to modify the combination of teachings with modifying the parity information comprises: retrieving, at the logic block, the parity information from the first memory array since it is known in the art that parity data can be retrieved (View Chang ¶ 18, 75). Such modification would have allowed parity data to be retrieved to correct data.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kariya (US Patent Application 2021/0202328) in view of Madan (US Patent Application 2011/0035644) in view of Chang (US Patent Application 2010/0281342) and further in view of Syrgabekov (US Patent Application 2015/0006956).
Claim 10, most of the limitations of this claim has been noted in the rejection of Claim 9. The combination of teachings above does not explicitly teach retrieving, at the logic block, a second data segment of the data set, wherein generating the second parity information is based on comparing the data segment with the second data segment.
However, Syrgabekov teaches retrieving, at the logic block, a second data segment of the data set (View Syrgabekov ¶ 44; data subset), wherein generating the second parity information is based on comparing the data segment with the second data segment (View Syrgabekov ¶ 44; data subset compared to create parity data).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to modify the combination of teachings with retrieving, at the logic block, a second data segment of the data set, wherein generating the second parity information is based on comparing the data segment with the second data segment since it is known in the art that parity data can be compared (View Syrgabekov ¶ 44). Such modification would have allowed parity data to be compared to correct data.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kariya (US Patent Application 2021/0202328) in view of Madan (US Patent Application 2011/0035644) and further in view of Sharon (US Patent Application 2011/0252288).
Claim 11, most of the limitations of this claim has been noted in the rejection of Claim 8. The combination of teachings above does not explicitly teach generating, at the logic block, one or more parity bits for the data segment based on receiving the command, wherein modifying the data set is based on writing the one or more parity bits to first memory array.
However, Sharon teaches generating, at the logic block, one or more parity bits for the data segment based on receiving the command (View Sharon ¶ 44; generate parity bits), wherein modifying the data set is based on writing the one or more parity bits to first memory array (View Sharon ¶ 15, 22; parity bits written to appropriate regions or the memory array).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to modify the combination of teachings with generating, at the logic block, one or more parity bits for the data segment based on receiving the command, wherein modifying the data set is based on writing the one or more parity bits to first memory array since it is known in the art that parity data can be compared (View Sharon ¶ 15, 22, 44). Such modification would have allowed parity data to be compared to correct data.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kariya (US Patent Application 2021/0202328) in view of Madan (US Patent Application 2011/0035644) and further in view of Mori (US Patent Application 2001/0008008).
Claim 12, most of the limitations of this claim has been noted in the rejection of Claim 8. The combination of teachings above does not explicitly teach transferring the parity information from the first memory array to a third memory array of the plurality of memory arrays.
However, Mori teaches transferring the parity information from the first memory array to a third memory array of the plurality of memory arrays (View Mori ¶ 81; parity data transferred to cache memory in the other array disk control apparatus).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to modify the combination of teachings with transferring the parity information from the first memory array to a third memory array of the plurality of memory arrays since it is known in the art that parity data can be transferred (View Mori ¶ 81). Such modification would have allowed parity data to be transferred to correct data.
Claim(s) 14 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kariya (US Patent Application 2021/0202328) in view of Madan (US Patent Application 2011/0035644) and further in view of D’Abreu (US Patent Application 2013/0003480).
Claim 14, most of the limitations of this claim has been noted in the rejection of Claim 8. The combination of teachings above does not explicitly teach the first semiconductor die comprises a plurality of interface blocks coupled with the logic block that are each operable to access or more respective memory arrays of the plurality of memory arrays.
However, D’Abreu teaches the first semiconductor die comprises a plurality of interface blocks coupled with the logic block that are each operable to access or more respective memory arrays of the plurality of memory arrays (View D’Abreu ¶ 23, 46; the first periphery die may include a NAND smart bridge that includes control logic, a first ECC engine, a second ECC engine, a first core interface, and a second core interface).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to modify the combination of teachings with the first semiconductor die comprises a plurality of interface blocks coupled with the logic block that are each operable to access or more respective memory arrays of the plurality of memory arrays since it is known in the art that a plurality of interfaces can be used (View D’Abreu ¶ 23, 46). Such modification would have allowed memory arrays to have multiple interfaces.
Claim 15, most of the limitations of this claim has been noted in the rejection of Claim 14. D’Abreu further teaches each of the plurality of interface blocks is coupled with a respective second semiconductor die of the set of one or more second semiconductor dies via a respective channel between each interface block and the respective second semiconductor die (View D’Abreu ¶ 23, 46; the first periphery die may include a NAND smart bridge).
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kariya (US Patent Application 2021/0202328) in view of Madan (US Patent Application 2011/0035644) and further in view of Malakapalli (US Patent Application 2022/0137835).
Claim 16, most of the limitations of this claim has been noted in the rejection of Claim 8. The combination of teachings above does not explicitly teach performing an Exclusive-OR operation using the parity information and the data set, wherein modifying the parity information is based on performing the Exclusive-OR operation.
However, Malakapalli teaches performing an Exclusive-OR operation using the parity information and the data set, wherein modifying the parity information is based on performing the Exclusive-OR operation (View Malakapalli ¶ 36, 69; host to perform the XOR computations and updating the parity data on SSDs).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to modify the combination of teachings with performing an Exclusive-OR operation using the parity information and the data set, wherein modifying the parity information is based on performing the Exclusive-OR operation since it is known in the art that an exclusive-or operation can be performed (View Malakapalli ¶ 36, 69). Such modification would have allowed an XOR operation to modify parity data.
Prior Art Made of Record
The prior art made of record and not relied upon is considered pertinent to Applicant’s disclosure:
Yang et al. (U.S. Patent Application 2010/0332900); teaches During a read operation, the array address input is transferred to the memory array to access a location containing a selected grouping (row) of the SMT MRAM memory cells and their associated the grouping or row of ECC encoded memory cells. The data from the selected grouping and the associated error correction data are transferred to an ECC decoder which performs an error detection operation. If there is an error in the data, the ECC decoder corrects the data and transfers the corrected data to external circuitry and to the scrub machine.
Conclusion
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/SARAI E BUTLER/Primary Examiner, Art Unit 2114
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