DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 3, 5, 6, 14 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. U.S. Patent Publication No. 2024/0386844 (hereinafter Wang) in view of Du et al. U.S. Patent Publication No. 2023/0157102 (hereinafter Du).
Consider claim 1, Wang teaches an electronic device, comprising: a tunable component, electrically connected to a circuit node (Figure 5, OLED); a first source follower circuit, electrically connected to the circuit node (Figure 5, T3); a scan transistor, electrically connected to the circuit node, wherein the scan transistor is further electrically connected to a data line, wherein the scan transistor provides a data voltage to the circuit node from the data line (Figure 5, T4 and respective connections); a first compensation transistor, electrically connected to the first source follower circuit (Figure 5, T7 and respective connections); a first bias transistor, electrically connected to a first terminal of the first source follower circuit and a first operation voltage (Figure 5, T5 and respective connections); a first reset transistor, wherein a first terminal of the reset transistor is electrically connected to the first operation voltage, and a second terminal of the reset transistor is electrically connected to a first control terminal of the first source follower circuit (Figure 5, T2 and respective connections); a first storage capacitor, wherein a first terminal of the first storage capacitor is electrically connected to the first control terminal of the first source follower circuit (Figure 5, capacitor 5 and T3), and a second terminal of the first storage capacitor is electrically connected to the first operation voltage (Figure 5, capacitor 5 is connected to VDD via T5-T6 and T3 (e.g. during emission period t4 in figure 6a)), wherein a first terminal of the first compensation transistor is electrically connected to the first terminal of the first source follower circuit, and a second terminal of the first compensation transistor is electrically connected to a control terminal of the first source follower circuit (Figure 5, T7 and respective connections), wherein a control terminal of the scan transistor and a control terminal of the first compensation transistor receive a scan signal (Figure 5, Gate), wherein during a scan period, the scan transistor and the first compensation transistor are turned-on, and the first bias transistor is turned-off (Figure 6a, t2).
Wang does not appear to specifically disclose a second source follower circuit, electrically connected to the circuit node, wherein the second source follower circuit comprises a second control terminal and a second terminal; a second compensation transistor, electrically connected to the second terminal and the second control terminal of the second source follower circuit; and a second bias transistor, electrically connected to the second terminal of the second source follower circuit and a second operation voltage; wherein a control terminal of the scan transistor, a control terminal of the second compensation transistor, and a control terminal of the first compensation transistor receive a scan signal, wherein a control terminal of the first bias transistor and a control terminal of the second bias transistor receive a bias signal.
However, in a related field of endeavor, Du teaches display device (abstract) and further teaches a second source follower circuit, electrically connected to the circuit node (Figure 2, N4 connected to plurality of pixel circuits 600 comprising driving transistors T3 (e.g. second source follower circuit corresponding to 612)), wherein the second source follower circuit comprises a second control terminal and a second terminal (Figure 2, T3 corresponding to 612 and respective connections); a second compensation transistor, electrically connected to the second terminal and the second control terminal of the second source follower circuit (Figure 2, T2 corresponding to 612 and respective connections); and a second bias transistor, electrically connected to the second terminal of the second source follower circuit and a second operation voltage (Figure 2, T5 corresponding to 612 and respective connections); wherein a control terminal of the scan transistor (Figure 2, T4 corresponding to 611), a control terminal of the second compensation transistor (Figure 2, T2 corresponding to 612), and a control terminal of the first compensation transistor (Figure 2, T2 corresponding to 611) receive a scan signal (Figure 2, Gate), wherein a control terminal of the first bias transistor and a control terminal of the second bias transistor receive a bias signal (Figure 2, T5 or T6 corresponding to 611-612 receives EM).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide a second source follower as taught by Du so that the resolution of the third display region 300 and the second display region 200 is lower than the resolution of the first display region 100, that is, the density of pixels arranged for display in the third display region 300 and the second display region 200 is smaller than the density of pixels of the first display region 100. Therefore, a camera can be provided below the low pixels-per-inch region that can allow more light to pass through as suggested in [0052-0053] and figures 1-2.
Consider claim 3, Wang and Du teach all the limitations of claim 1. In addition, Wang teaches wherein a current is transmitted from the first source follower to the tunable component (Figure 5, current from Vdd to Vss).
Consider claim 5, Wang and Du teach all the limitations of claim 1. In addition, Wang teaches wherein the first source follower circuit comprises a first drive transistor (Figure 5, T3).
Consider claim 6, Wang and Du teach all the limitations of claim 5. In addition, Wang teaches wherein the first drive transistor is a N-type transistor (Figure 5, T3).
Consider claim 14, Wang and Du teach all the limitations of claim 1. In addition, Du teaches a second storage capacitor, electrically connected to the second control terminal of the second source follower circuit (Figure 2 shows a plurality of capacitors C, see motivation to combine in claim 1).
Consider claim 16, Wang and Du teach all the limitations of claim 1. In addition, Wang teaches a third bias transistor, electrically connected between the circuit node and the tunable component (Figure 5, T6 and respective connections).
Claim(s) 4, 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang and Du as applied to claim 1 above, and further in view of Zhang et al. U.S. Patent Publication No. 2018/0130412 (hereinafter Zhang).
Consider claim 4, Wang and Du teach all the limitations of claim 1.
Wang does not appear to specifically disclose wherein a current is transmitted from the tunable component to the first source follower.
However, in a related field of endeavor, Zhang teaches pixel circuit in figure 3-b and further teaches wherein a current is transmitted from the tunable component to the first source follower (Figure 3b, current from VDD to VSS).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to transmit from the tunable component to T1 as taught by Zhang with the benefit that the first end of the light emitting element OLED is cathode, and the second end of the light emitting element OLED is anode; the first electrode of the third transistor T3 is coupled to the second level end VSS, and the second end of the light emitting element OLED is coupled to the first voltage level end VDD as suggested in [0038].
Consider claim 7, Wang and Du teach all the limitations of claim 1.
Wang does not appear to specifically disclose wherein the first drive transistor is a P-type transistor.
However, Zhang teaches wherein the first drive transistor is a P-type transistor (Figure 3b, T1).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide P-type transistors as taught by Zhang in order to meet design choices since Zhang teaches N-type or P-type in [0036]. In addition, the effective levels for turning on the P-type transistors are low levels as suggested in [0052].
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang and Du as applied to claim 1 above, and further in view of Sakariya et al. U.S. Patent Publication No. 2015/0348504 (hereinafter Sakariya).
Consider claim 8, Wang and Du teach all the limitations of claim 1.
Wang does not appear to specifically disclose a smoothing capacitor, electrically connected to the tunable component in parallel.
However, in a related field of endeavor, Sakariya teaches a subpixel circuit in figure 6d and further teaches a smoothing capacitor, electrically connected to the tunable component in parallel (Figure 6D, Cx and 501).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide a smoothing capacitor as taught by Sakariya with the benefit that Cx may be used to determine an intensity of light sensed as suggested in [0067].
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang and Du as applied to claim 1 above, and further in view of Yamashita et al. U.S. Patent Publication No. 2010/0079430 (hereinafter Yamashita).
Consider claim 15, Wang and Du teach all the limitations of claim 1.
Wang does not appear to specifically disclose a third reset transistor, electrically connected to the tunable component in parallel.
However, in a related field of endeavor, Yamashita teaches a pixel array (abstract) and further teaches a third reset transistor, electrically connected to the tunable component in parallel (Figure 48 and [0326], N63 and OLED).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide a reset transistor as taught by Yamashita so that at an initialization time for example, the reset transistor N63 is controlled to enter a turned-on state. In this way, an initialization process is carried out as suggested in [0329].
Response to Arguments
Applicant's arguments filed 11/27/2025 have been fully considered but they are not persuasive.
On pages 7-8 of Applicant’s response, Applicant argues that “Referring to Wang, one terminal of the capacitor 5 of Wang is connected to the control terminal of transistor T3 (alleged as the first source follower circuit as claimed), while the other terminal of this capacitor 5 is electrically connected to the node N4 (Vinit when the Tl is on). The capacitor 5 in Fig. 5 of Wang is not connected to the first power terminal VDD as claimed in claim 1. The Office respectfully disagrees for the following reasons.
Wang shows in figure 5 that capacitor 5 is connected to VDD via T5-T6 and T3 (e.g. during emission period t4 in figure 6a). Consequently, these arguments have been considered but they are not persuasive.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ROBERTO W FLORES/Primary Examiner, Art Unit 2621