DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Election/Restrictions
Applicant's election with traverse of Group I, claims 1-16, in the reply filed on 12/11/2025 is acknowledged. The traversal is on the ground(s) that examination of the two different inventions were not required undo search for due to similar technical features. This is not found persuasive because claim 1 in Group I is directed to an apparatus that avoids outputting garbage data by resetting a buffer in response to an underrun situation whereas claim 17 in Group II is directed to a method for retransmitting a program command for write data based on underrun situations. The inventions provide fault tolerance for buffer underruns in completely different ways and require different search strings and are classified completely differently.
The requirement is still deemed proper and is therefore made FINAL.
Claims 17-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 12/11/2025.
Claim Rejections - 35 USC § 103
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under pre-AIA 35 U.S.C. 103(a) are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-2, 5, 7-11 and 15-16 is/are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over LEE; Hyung-Gyu (US 20110119569 A1, hereafter referred to as LEE) and Harris et al. (US 4300173 A, hereafter referred to as Harris).
LEE is directed to active flow control for maintaining synchronization between a memory controller and memory cells being written to; and, addresses what a system should do midstream when a buffer runs dry (underrun) while writing to a physical storage. LEE teaches clearing logic for clearing a buffer in response to underflow or other errors to ensure that no “stale” or residual data is included when the write operation is reinitialized (clearing a buffer and reinitializing the buffer is substantially a reset operation). Harris is directed to an overflow/underflow prevention system for a data buffer (FIFO) that operates by comparing the relative speeds of the input and output data streams. It counts a clock signal (or data pulses) to maintain a “running tally” of the data currently in the FIFO. When the counter indicates the FIFO is empty, the control logic identifies this as a failure of synchronization triggering a reset for preventing the system from outputting “stale” or “garbage” data.
Rejection of claims 1 and 10:
LEE teaches a memory device comprising: a cell region comprising a plurality of memory cells; and a peripheral region including a buffer region, and configured to receive data to be stored in the cell region (Figure 1 in LEE teaches a memory device 100 comprising: a cell region 101 comprising a plurality of memory cells; and a peripheral region 102 including a buffer region 102-1/102-2, and configured to receive data to be stored in the cell region 101).
However, LEE does not teach the use of a count value of a clock signal to determine an underrun has occurred and to reset a buffer responsive to the determination of the underrun based on the count value.
Harris, in an analogous art, teaches the use of a count value of a clock signal to determine an underrun has occurred in a buffer/FIFO (the buffer/FIFO has gone empty) and to reset the buffer/FIFO responsive to the determination of the underrun based on the count value (column 2, lines 3-13 in Harris).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine LEE with the teachings of Harris by including use of a count value of a clock signal to determine an underrun has occurred and to reset a buffer responsive to the determination of the underrun based on the count value. This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, because one of ordinary skill in the art would have recognized that use of a count value of a clock signal to determine an underrun has occurred and to reset a buffer responsive to the determination of the underrun based on the count value would have prevented the system from outputting “stale” or “garbage” data (column 2, lines 3-13 in Harris).
Rejection of claims 2, 5 and 11:
Column 8 lines 56-61 in Harris.
Rejection of claims 7 and 15:
Step 504 in Figure 5 in LEE.
Rejection of claims 8 and 16:
Column 9, lines 1-9 in Harris.
Rejection of claim 9:
Figures 3-4 in LEE.
Allowable Subject Matter
Claims 3-4, 6 and 12-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
* US 20230393754 A1: Focuses on low-latency recovery. It details how to handle a "write-abort" caused by an underrun in a way that doesn't corrupt the flash translation layer. It’s highly relevant for "Clear/Reset" operations because it discusses resetting the physical page address pointers after a failure.* US 9916105 B1: A key document for predictive buffering. It uses "Data Starvation" detection logic to prevent the underrun before it happens, specifically for PCIe-based storage.* US 7948872 B2: This is about threshold-based flow control. It manages how a buffer "drains" into memory cells and uses specific "Stop/Go" signals based on the fill level. It connects the "Empty" state directly to a "Wait State" (reset-adjacent).* US 20090129172 A1: this is a pillar for Suspend/Resume logic. It provides the "Reset" mechanism for the state machine when the buffer runs dry during a memory write.* US 7228509 B1: It defines the threshold monitoring of a FIFO and the resulting re-set/restart logic for memory writes.* US 20050018514 A1: Describes Buffer Underrun Protection. It’s relevant because it details the "stitching" process—how to clear a buffer and restart a write operation at the exact bit where the underrun occurred.* US 6456628 B1: Focuses on FIFO Status Monitoring. It uses the "Clock Counter" logic to generate "Empty" and "Full" flags that trigger an immediate reset of the transmission logic.* US 6092128 A: A good teaching for FIFO Pointer Logic. It deals with the management of read/write pointers and how to "Reset" them to a zero-state if a synchronization error (underflow) is detected.* US 6049223 A: Deals with Programmable FIFO Status. It allows a user to define "Almost Empty" thresholds. When these are hit, it can trigger a "Clear" or "Reset" to the host.* US 5978868 A: Specifically addresses Data Buffer Management in peripherals. It is relevant for the "Clearing" aspect, as it describes how to flush a buffer and reset the DMA (Direct Memory Access) controller after an underrun.* US 5572148 A / US 5570040 A: These two are "sibling" patents for High-Speed FIFO Control Circuits. They show the physical gates used to compare clocks and initiate a hard-reset when the buffer hits the "Empty" state.* US 4860193 A: a "Bridge" patent. It formalizes the Up/Down Counter method for calculating the "Residual Count" and initiating an inhibit/reset signal.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH D TORRES whose telephone number is (571)272-3829. The examiner can normally be reached Monday-Friday 10-7 PT.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Albert Decady can be reached at 571-272-3819. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JOSEPH D TORRES/Primary Examiner, Art Unit 2112