DETAILED ACTION
This office action is in response to a Request for Continued Examination (RCE) filed 3/10/2026.
Claims 1 and 6 have been amended. No claims are new. No claims have been cancelled. Thus claims 1-15 have been examined.
The objections and rejections from the prior correspondence that are not restated herein are withdrawn.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 3/10/2026 has been entered.
Allowable Subject Matter
Claims 1-5 and 11-15 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding independent claim 1 the claim has been amended to incorporate subject matter from previously allowed claim 11. As such, claim 1 is in condition for allowance as identified on pages 11 and 12 in the Office Action dated 1/15/2026.
Regarding dependent claims 2-5, the claims are allowable based on their dependence from allowed claim 1.
Claims 11-15 are allowed for the reasons identified in the Office Action dated 1/15/2026.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 6-7,and 10 are rejected under 35 U.S.C. 102 (a)(1) and as being anticipated by Luo (An article/thesis titled Architectural Techniques for Improving NAND Flash Memory Reliability by Yixin Luo, August 2018).
Regarding claim 6, Luo teaches A storage device comprising:
a nonvolatile memory device; (Luo, page iii, Abstract lines 4-6 and 26-31 discloses the flash is generally implemented by flash chips managed by a controller within a Solid-State Drive (SSD) where the SSD is an example of a storage device comprising a non-volatile device.)
a volatile memory device configured to store map data including mapping information between a logical address and physical address corresponding to data stored in the nonvolatile memory device; and (Luo page 17 Flash Translation Layer lines 1-12 discloses that the flash includes a flash translation layer to map logical addresses provided by the host to physical addresses in the underlying flash memory block where the data is actually stored.)
a memory controller configured to (Luo, page iii, Abstract lines 7-8 discloses the concepts of the article/thesis are directed to NAND flash memory devices. Luo page 3, Abstract lines 34-37 discloses the concepts are implemented in memory controllers.) determine information on a location of the volatile memory device, at which the map data associated with an external request have been stored, and (Luo page 15 lines 19-40 2.1.3. SSD Controller discloses that the controller access DRAM which stores metadata including an address map to map physical addresses using a flash translation layer (FTL). See also Lou page 17 lines 1-20 Flash Translation Layer that discloses the FLT manages the mapping of logical addresses to physical addresses in the underlying flash memory where the actual data is stored. Thus uses information stored in the DRAM (i.e. dynamic random access memory that is a volatile memory device, at which the map data associated with an external request is stored.) schedule processing performance between a processing operation for the external request and an internal management operation for the nonvolatile memory device, based on a result of the determination, (Luo page 49 lines 5-36 discloses a read reclaim method is performed to mitigate read disturb errors if the block has experienced a high number of reads per a threshold value, where the read remap operation is an example of an internal management operation. Otherwise, if the threshold value is not reached, the data is simply read and not moved. Luo will count reads based on (as a function of ) the logical address included in the external read requests that map to a physical location of the data, and process the block read request (i.e. schedule the read request) and/or the external request based on (as a function of) the appearance frequency of a logical address that maps to the physical that is a location of information of the volatile memory device. The map information that Lou is accessing to count the read disturb errors is based on the information on a location of the volatile memory device, at which the map data associated with an external request is stored (i.e. is based on the determination).)
Regarding claim 7, Luo teaches all of the limitations of claim 6 above. Luo further teaches wherein: the external request comprises a logical address; (Luo page 17, section Flash Translation Layer, lines 12-5 discloses the host uses the logical addresses.)
and the memory controller is configured to schedule the processing performance based on frequency of access to the volatile memory device, (Luo page 49 lines 5-36 discloses in section ‘Read Reclaim to Reduce Read Disturb Errors’ a read reclaim method is performed to mitigate read disturb errors, where the read reclaim remaps (i.e. moves) data in a block to a new flash block if the block has experienced a high number of reads per a threshold value. Luo page 17 Flash Translation Layer lines 1-12 discloses that the flash includes a flash translation layer to map logical addresses provided by the host to physical addresses in the underlying flash memory block where the data is actually stored. Thus Luo is tracking accesses to a flash memory block based on logical addresses included in the external request from the host that is mapped to a physical address of the data and schedules the read reclaim (the processing performance of the maintenance request) based on the frequency of access to the physical address since the data was created at the volatile memory device.)
for reading map data corresponding to the logical address. (Luo page 49 lines 5-36 discloses the physical to logical mapping is stored in metadata. Luo page 15, 2.1.3 SSD Controller lines 1-5 discloses that the SSD controller stores metadata in the DRAM of the SSD.)
Regarding claim 10, Luo teaches all of the limitation of claim 6 above. Lou further teaches wherein the internal management operation comprises at least on of a garbage collection operation, a wear-leveling operation, and a read reclaim operations. (Lou page 49 lines 5-36 discloses in section ‘Read Reclaim to reduce Read Disturb Errors’ a read reclaim method is performed to mitigate read disturb errors, where the read reclaim reaps (i.e. moves) data in a block to a new flash block if the block has experienced a high number of reads per a threshold value.)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over by Luo (An article/thesis titled Architectural Techniques for Improving NAND Flash Memory Reliability by Yixin Luo, August 2018) as detailed in claims 6 above and further in view of Tsou (TSOU et al., US 2018/0260137 A1).
Regarding claim 8, Luo teaches all of the limitation of claim 6 above.
However, Luo does not explicitly disclose wherein the memory controller is configured to schedule the processing performance by adjusting at least one of a credit allocation ratio, a computer resource allocation ratio, a processing opportunity assignment ratio, and priority.
Tsou, of a similar field of endeavor, further teaches wherein the memory controller is configured to schedule the processing performance by adjusting at least one of a credit allocation ratio, a computer resource allocation ratio, a processing opportunity assignment ratio, and priority. (Examiner notes that this claim is disclosed when one of the 4 adjustment options is disclosed. Tsou teaches adjusting the priority. Tsou [0010] discloses that the priority of read reclaims are greater than the priority of data collection, thus adjusts the priority of the read reclaim process above read requests).
Luo and Tsou are in a similar field of endeavor as both relate to scheduling maintenance requests to non-volatile memory that may experience read disturb errors. Thus it would have been obvious to a person of ordinary skill in the art before the claimed invention to incorporate the prioritizing maintenance requests such as a read reclaim within a read cycle as taught by Tsou into the solution of Luo that performs both reads and read reclaim maintenance requests. Thus combining prior art elements according to known methods to achieve predictable results (to enable a system to perform high priority maintenance requests such as read reclaims during the read cycle so that the high priority maintenance requests can be executed without unduly affecting the read latency and yet are not forced to wait for all read requests (which may not be high priority requests) to be performed.
Regarding claim 9, Luo teaches all of the limitation of claim 6 above.
However, Luo does not explicitly teach wherein: the external request comprises a read request; and the memory controller is configured to raise the processing performance of the internal management operation more than the processing operation for the external request when a read request for a specific logical address range or a specific logical address is repeatedly received, during a set time, at set threshold value or more.
Tsou, of a similar field of endeavor, further teaches wherein: the external request comprises a read request; and the memory controller is configured to raise the processing performance of the internal management operation more than the processing operation for the external request when a read request for a specific logical address range or a specific logical address is repeatedly received, during a set time, at set threshold value or more. (Tsou Figs. 2A and 2B and paras [0036-[0047], most notable steps S12 through S220 that prioritizes a maintenance process such as a read reclaim at step S212 over unexecuted read requests that are executed after step S220. Thus enabling the system to execute maintenance requests in a timely fashion as long as the time remaining after a first read request and a maintenance request is below a threshold. The solution of Luo in view of Tsou would receive a read request at the storage controller, recognize that this requires both a read and a read reclaim step and would schedule both steps. Thus when the system enters the system at step S200 while maintaining at least 1 prior read request, the system would process the prior read request at step S204, and process the read reclaim at step S212, and then process the read request that triggered the read reclaim at step S220. The read reclaim at step S212 is execute before (at a higher priority) than the read at step S220.)
The motivation to combine Tsou into Lou is the same as set forth in claim 8 above.
Response to Remarks
Examiner thanks applicant for their claim amendments and remarks of 3/10/2026. They have been fully considered.
Examiner notes the amendments to claim 1 incorporate the concepts of previously allowed claim 11 and thus claims 1-5 are allowable based on the newly amended limitations to claim 1.
Applicant argues on pages 9-10 of their remarks ‘Claim 1 has been amended and claims, inter alia, "determine an appearance frequency of a logical address that is included in the external request when receiving the external request; and schedule, based on a result of the determination, processing performance between a processing operation for the external request and an internal management operation for the nonvolatile memory device". Claim 6 claims similar features.’
Examiner respectfully disagrees. While it is true that claim 1 has been amended as discussed. It is not true that claim 6 claims similar features. Claim 6 recites ‘A storage device comprising: a nonvolatile memory device; a volatile memory device configured to store map data including mapping information between a logical address and physical address corresponding to data stored in the nonvolatile memory device; and a memory controller configured to determine information on a location of the volatile memory device, at which the map data associated with an external request have been stored, and schedule processing performance between a processing operation for the am external request and an internal management operation for the nonvolatile memory device, based on a result of the determination information on a location of the volatile memory device, at which the map data associated with the external request have been stored.’ Claim 6 does not recite “determine an appearance frequency of a logical address” which was required for novelty in claims 1 and 10.
Applicant further argues on page 10 of their remarks ‘The above amendment includes features from allowed claims 11-15. Thus the Applicant respectfully submits that neither Luo nor Tsou discloses “determine an appearance frequences of a logical address…” as claimed in claim 1 and similarly claimed in claim 6. Accordingly, for at least the foregoing reasons, Luo fails to teach all of the features of independent claims 1 and 6, and their respective dependent claims and thus cannot anticipate these claims’.
Examiner respectfully notes that Applicant’s remarks are valid for claims 1-5. However Claim 6 does not recite “determine an appearance frequences of a logical address…”. Thus claim 6 is not allowable based on “determine an appearance frequences of a logical address…” as applicant suggests.
Applicants argument with respect to dependent claims 7-10 all relate to perceived errors in the rejection of claim 6 and thus have been addressed in the rejection and remarks relating to claim 6 above from which claims 7-10 depend.
Conclusion
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/JANICE M. GIROUARD/Primary Examiner, Art Unit 2138