DETAILED ACTION
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on December 23, 2025 has been entered.
Response to Amendment
The Amendment filed December 23, 2025 has been entered. Claims 1-20 remain pending in the application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 2 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tanaka (US 2015/0023101).
Claims 1 and 2 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tanaka (US 2015/0023101).
Regarding claim 1, Tanaka discloses:
A method for adjusting a working state of a memory device, wherein the memory device (FIG. 1 Memory System 100) is configured to be coupled to a host device (FIG. 1 Host 1) and comprises a memory controller (FIG. 1 Controller 50) and a non-volatile memory (FIG. 1 Storage Components (Nonvolatile) 30), and the memory controller is coupled to the non-volatile memory and configured to control an operation of the memory device ([0021] The controller 50 controls operations of the memory system 100 such as write control of data to which a write request has been made from the host 1, and a read control of data to which the read request has been made from the host 1);
the method comprises configuring the memory controller to perform the following steps:
setting a waiting time before the memory device enters a power-down mode (FIG. 7 S 505 Enter low power consumption mode) as a first time value (FIG. 7 S502 Is Te expired?), wherein the memory device enters the power-down mode after the waiting time from being driven by a power-down instruction (FIG. 7 S502 Yes; S505);
determining whether the host device is performing an access operation (FIG. 5 Command/Data; [0034] The timer 46 is reset by a controller 50 each time the command is received from a host 1, and its time measuring operation is restarted at a point in time when the command is received); and
setting the waiting time as a second time value (FIG. 7 S504 Is Tc Expired) in response to the host device being performing the access operation ([0033] a predetermined delay time (waiting time) Tc having elapsed since a command is received just before an LPD output is asserted is added to conditions for transitioning to a low power consumption mode. In the second embodiment, the transition to the low power consumption mode is performed at either a first point in time when a waiting time Te has elapsed since the LPD output is asserted, or a second point in time when a waiting time Tc has elapsed since a command is received just before the point in time when the LPD output is asserted, whichever arrives at a later timing), wherein the first time value is smaller than the second time value ([0033] Tc>Te).
The limitation “determining whether the host device is performing an access operation” is a contingent condition. The broadest reasonable interpretation of a method claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition precedent are not met, MPEP § 2111.04 II. In this case, if it is determined that the host device is not performing an access operation, then the contingent limitation of “setting the waiting time as a second time value in response to the host device being performing the access operation, wherein the first time value is smaller than the second time value.” is not required. Therefore, evidence of the anticipation of the limitation is not required under the broadest reasonable interpretation of claim 1. However, prior art has been applied to all limitations in claim 1 in order to promote compact prosecution. The examiner recommends that applicant amend the limitation “determining whether the host device is performing an access operation” to positively recite that the access operation is being performed.
Regarding claim 2, Tanaka further discloses:
The method according to claim 1, wherein the first time value is greater than or equal to 0ms ([0037] the controller 50 activates the timer 45 to start measuring time (step S501). The controller 50 determines whether the time measured by the timer 45 has exceeded the predetermined delay time Te or not (step S502); It would be obvious to one skilled in the art before the effective filing date of the claimed invention that the first time value is greater than or equal to 0ms because a timer measures positive increments of time from 0, see also FIG. 3).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Tanaka as applied to claim 1 above, and further in view of Muthiah (US 2021/0382649).
Regarding claim 3, Tanaka does not appear to explicitly teach while Muthiah discloses:
The method according to claim 1, wherein the second time value is greater than or equal to 20ms ([0014] the controller is further configured to determine an amount of time needed to execute the command, and wherein the request to extend the time-out window is based on the determined amount of time; [0015] the amount of time needed to execute the command is based on…a time to transfer data to the host; [0059] consider the situation of a write command with a 250 millisecond (ms) sector-wise time allowance. The storage system 100 can communicate/request an extra 50 ms for a specific sector in a given command according to its latency evaluation. The storage system 100 can use this time (250 ms+50 ms=300 ms) for longer operations).
Tanaka and Muthiah are analogous art because Tanaka teach transitioning to a low power consumption mode in a memory system and Muthiah teach memory device timeout.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Tanaka and Muthiah before him/her, to modify the teachings of Tanaka with Muthiah the teachings of setting a waiting time because setting the waiting time for a value greater than or equal to 20ms would allow for the completion of longer operations.
Claims 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over Tanaka as applied to claim 1 above, and further in view of Kumar et al. (US 2017/0177061) and Song et al. (US 2022/0350535).
Regarding claim 4, Tanaka further discloses:
The method according to claim 1, wherein the determining whether the host device is performing the access operation comprises:
detecting whether a read instruction or a write instruction is received from the host device ([0021] The controller 50 controls operations of the memory system 100 such as write control of data to which a write request has been made from the host 1, and a read control of data to which the read request has been made from the host 1),…
Tanaka does not appear to explicitly teach “wherein when the read instruction or the write instruction is detected and at least one of the following conditions is satisfied, determining that the host device is performing the access operation: if a volume of data read or written is greater than a first threshold after the read instruction or the write instruction is performed; or if a quantity of read instructions or write instructions continuously performed is greater than a second threshold after the read instruction or the write instruction is performed.” However, Kumar et al. disclose:
wherein when the read instruction or the write instruction is detected and at least one of the following conditions is satisfied, determining that the host device is performing the access operation:
if a volume of data read or written is greater than a first threshold after the read instruction or the write instruction is performed ([0028] commands for data transfer for each source-destination pair are tracked and are accumulated before generating read requests using the read request generator 104 and reading the data corresponding to the read requests from the corresponding source 107. The commands for data transfer may be accumulated in the command processing unit 102. When an amount of data corresponding to the accumulated commands for data transfer for a source-destination pair is below a predefined threshold, the corresponding read requests are not yet generated and therefore data corresponding to the read requests are not yet read from the data source 107. In addition, the RAM buffer corresponding to the source-destination pair is maintained in the power saving mode. When the amount of data corresponding to the accumulated commands for data transfer for the source-destination pair surpasses the threshold, the read requests corresponding to the commands for data transfer may be generated and data corresponding to the read requests may be read from the data source 107);
Tanaka and Kumar et al. are analogous art because Tanaka teach transitioning to a low power consumption mode in a memory system and Kumar et al. teach power saving in data transfer within a memory system.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Tanaka and Kumar et al. before him/her, to modify the teachings of Tanaka with the teachings of Kumar et al. because performing the access operation after the accumulation of a threshold volume of data would avoid higher power consumption and delay in data transfer (Kumar et al. [0027]).
Tanaka and Kumar et al. do not appear to explicitly teach “or if a quantity of read instructions or write instructions continuously performed is greater than a second threshold after the read instruction or the write instruction is performed.” However, Song et al. disclose:
or if a quantity of read instructions or write instructions continuously performed is greater than a second threshold after the read instruction or the write instruction is performed ([0086] If the quantity of queued commands is less than a threshold quantity (e.g., if the quantity of queued commands is zero), the power mode controller 330 may transition the non-volatile memory 325 from a higher power mode (e.g., a standby mode, an active mode) to a lower power mode. Such a technique may reduce the power consumption of the non-volatile memory 325 by allowing the non-volatile memory 325 to transition to a lower power mode if there is a break in accessing the non-volatile memory 325).
Tanaka, Kumar et al., and Song et al. are analogous art because Tanaka teach transitioning to a low power consumption mode in a memory system; Kumar et al. teach power saving in data transfer within a memory system; and Song et al. teach power mode control in a memory system.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Tanaka, Kumar et al., and Song et al. before him/her, to modify the combined teachings of Tanaka and Kumar et al. with the teachings of Song et al. because performing the access operations when the quantity of instructions continuously performed is above a threshold would avoid higher power consumption by maintain a low-power mode while there is a break in accessing the non-volatile memory (Song et al. [0085]).
Regarding claim 5, Song et al. further disclose that the second threshold is zero, see paragraph [0086]. However, it would be obvious to one skilled in the art before the effective filing date of the claimed invention to modify the threshold level taught by Song et al. to two. The setting of the threshold quantity is a design choice and setting the threshold to two would enable the system to avoid higher power consumption by remaining in a low-power mode longer. Therefore, the combination of Tanaka, Kumar et al., and Song et al. further disclose the limitation:
The method according to claim 4, wherein the second threshold is at least two.
Regarding claim 6, Kumar et al. further disclose:
The method according to claim 4, wherein the first threshold is greater than or equal to 512Kb ([0034] The predefined threshold may be a configurable value and may be configured to ensure an optimal trade-off between power saving and delay in servicing of read requests due to accumulation of the commands for data transfer; Based on the teachings of Kumar, it would be obvious to one skilled in the art before the effective filing date of the claimed invention to set the first threshold to greater than or equal to 512Kb. The setting of the threshold is a design choice to ensure an optimal trade-off between power saving and delay in servicing of read requests due to accumulation of the commands for data transfer).
Claims 7-9, 13-14, and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Tanaka and Muthiah.
Regarding claim 7, Tanaka discloses:
A memory device (FIG. 1 Memory System 100), comprising:
a non-volatile memory (FIG. 1 Storage Components (Nonvolatile) 30), configured to store information ([0018] in the NAND type flash memory, data write and data read are performed for each page); and
a memory controller (FIG. 1 Controller 50), coupled to the non-volatile memory and configured to control an operation of the memory device ([0021] The controller 50 controls operations of the memory system 100 such as write control of data to which a write request has been made from the host 1, and a read control of data to which the read request has been made from the host 1), wherein the memory controller comprises:
…wherein the memory controller is configured to perform the following steps:
setting a waiting time before the memory device enters a power-down mode (FIG. 7 S 505 Enter low power consumption mode) as a first time value (FIG. 7 S502 Is Te expired?), wherein the memory device enters the power-down mode after the waiting time from being driven by a power-down instruction (FIG. 7 S502 Yes; S505);
determining whether the host device is performing an access operation (FIG. 5 Command/Data; [0034] The timer 46 is reset by a controller 50 each time the command is received from a host 1, and its time measuring operation is restarted at a point in time when the command is received); and
setting the waiting time as a second time value (FIG. 7 S504 Is Tc Expired) in response to the host device being performing the access operation ([0033] a predetermined delay time (waiting time) Tc having elapsed since a command is received just before an LPD output is asserted is added to conditions for transitioning to a low power consumption mode. In the second embodiment, the transition to the low power consumption mode is performed at either a first point in time when a waiting time Te has elapsed since the LPD output is asserted, or a second point in time when a waiting time Tc has elapsed since a command is received just before the point in time when the LPD output is asserted, whichever arrives at a later timing), wherein the first time value is smaller than the second time value ([0033] Tc>Te).
Tanaka does not appear to explicitly teach “wherein the memory controller comprises: a processing circuit, configured to control the memory controller according to a plurality of host instructions from a host device to allow the host device to access the non-volatile memory through the memory controller; and a transmission interface circuit, configured to communicate with the host device to perform transmitting and receiving operations.” However, Muthiah discloses:
wherein the memory controller comprises:
a processing circuit (FIG. 2A Controller 102; [0035] The controller 102 (which may be a non-volatile memory controller (e.g., a flash, resistive random-access memory (ReRAM), phase-change memory (PCM), or magnetoresistive random-access memory (MRAM) controller)) can take the form of processing circuitry, a microprocessor or processor, and a computer-readable medium that stores computer-readable program code (e.g., firmware) executable by the (micro)processor, logic gates, switches, an application specific integrated circuit (ASIC), a programmable logic controller, and an embedded microcontroller, for example), configured to control the memory controller according to a plurality of host instructions from a host device to allow the host device to access the non-volatile memory through the memory controller ([0034] Controller 102 interfaces with a host system and transmits command sequences for read, program, and erase operations to non-volatile memory die 104); and
a transmission interface circuit (FIG. 2A ), configured to communicate with the host device to perform transmitting and receiving operations ([0042] Controller 102 includes a front end module 108 that interfaces with a host; [0044] Front end module 108 includes a host interface 120 and a physical layer interface (PHY) 122 that provide the electrical interface with the host or next level storage controller);
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Tanaka and Muthiah before him/her, to modify the teachings of Tanaka with Muthiah’s teachings of a processing circuit and a transmission interface circuit because such a modification would have amounted to little more than combining “familiar elements according to known methods” and would have been obvious because it would have done “no more than yield predictable results.” (MPEP 2143 LA.) A processing circuit to control a memory controller and a transmission interface circuit to communicate with a host are well known memory controller elements. Including these elements would have yielded the predictable result controlling the memory controller and communicating with the host.
Regarding claim 8, Tanaka further discloses:
The memory device according to claim 7, wherein the first time value is greater than or equal to 0ms ([0037] the controller 50 activates the timer 45 to start measuring time (step S501). The controller 50 determines whether the time measured by the timer 45 has exceeded the predetermined delay time Te or not (step S502); It would be obvious to one skilled in the art before the effective filing date of the claimed invention that the first time value is greater than or equal to 0ms because a timer measures positive increments of time from 0, see also FIG. 3).
Regarding claim 9, Tanaka does not appear to explicitly teach while Muthiah further discloses:
The memory device according to claim 7, wherein the second time value is greater than or equal to 20ms ([0014] the controller is further configured to determine an amount of time needed to execute the command, and wherein the request to extend the time-out window is based on the determined amount of time; [0015] the amount of time needed to execute the command is based on…a time to transfer data to the host; [0059] consider the situation of a write command with a 250 millisecond (ms) sector-wise time allowance. The storage system 100 can communicate/request an extra 50 ms for a specific sector in a given command according to its latency evaluation. The storage system 100 can use this time (250 ms+50 ms=300 ms) for longer operations).
Regarding claim 13, Tanaka further discloses:
An electronic device, comprising the memory device according to claim 7, and further comprising:
the host device, coupled to the memory device (FIG. 1 Host 1 coupled to Memory System 100),…
Tanaka does not appear to explicitly teach “wherein the host device comprises: at least one processor, configured to control an operation of the host device; a power supply circuit, coupled to the at least one processor and configured to provide a power source to the at least one processor and the memory device, wherein the memory device provides storage space to the host device.” However, Muthiah further discloses:
wherein the host device comprises:
at least one processor, configured to control an operation of the host device (FIG. 3 Process 330 in Host 300; [0050] computer-readable program code stored in the host memory 340 configures the host processor 330 to playback media read from the memory 104 of the storage system 100);
a power supply circuit, coupled to the at least one processor and configured to provide a power source to the at least one processor and the memory device, wherein the memory device provides storage space to the host device ([0050] The host 300 can take any suitable form, including, but not limited to, a computer, a mobile phone, a tablet, a wearable device, a digital video recorder, a surveillance system, etc… omputer-readable program code stored in the host memory 340 configures the host processor 330 to playback media read from the memory 104 of the storage system 100; One of ordinary skill in the art before the effective filing date of the claimed invention would recognize that a host such as a computer, a mobile phone, a tablet, a wearable device, a digital video recorder, a surveillance system, etc., has a power supply circuit to supply power to the processor and the memory device).
Regarding claim 14, Tanaka further discloses:
The electronic device according to claim 13, wherein the first time value is greater than or equal to 0ms ([0037] the controller 50 activates the timer 45 to start measuring time (step S501). The controller 50 determines whether the time measured by the timer 45 has exceeded the predetermined delay time Te or not (step S502); It would be obvious to one skilled in the art before the effective filing date of the claimed invention that the first time value is greater than or equal to 0ms because a timer measures positive increments of time from 0, see also FIG. 3), and…
Tanaka does not appear to explicitly teach “the second time value is greater than or equal to 20ms.” However, Muthiah further discloses:
the second time value is greater than or equal to 20ms ([0014] the controller is further configured to determine an amount of time needed to execute the command, and wherein the request to extend the time-out window is based on the determined amount of time; [0015] the amount of time needed to execute the command is based on…a time to transfer data to the host; [0059] consider the situation of a write command with a 250 millisecond (ms) sector-wise time allowance. The storage system 100 can communicate/request an extra 50 ms for a specific sector in a given command according to its latency evaluation. The storage system 100 can use this time (250 ms+50 ms=300 ms) for longer operations).
Regarding claim 17, Tanaka discloses:.
A memory controller (FIG. 1 Controller 50) for a memory device (FIG. 1 Memory System 100), wherein the memory device comprises the memory controller (FIG. 1 Controller 50) and a non-volatile memory (FIG. 1 Storage Components (Nonvolatile) 30);
…wherein the memory controller is configured to perform the following steps:
setting a waiting time before the memory device enters a power-down mode (FIG. 7 S 505 Enter low power consumption mode) as a first time value (FIG. 7 S502 Is Te expired?), wherein the memory device enters the power-down mode after the waiting time from being driven by a power-down instruction (FIG. 7 S502 Yes; S505), the waiting time starts when the host device presents an idle state ([0033] the transition to the low power consumption mode is performed at either a first point in time when a waiting time Te has elapsed since the LPD output is asserted, or a second point in time when a waiting time Tc has elapsed since a command is received just before the point in time when the LPD output is asserted, whichever arrives at a later timing. Tc>Te is satisfied; [0036] the transition to the low power consumption mode is performed at either the first point in time when a timer 45 measures the waiting time (delay time) Te after the LPD output is asserted, or the second point in time when the timer 46 measures the waiting time (delay time) Tc after the command is received just before the point in time when the LPD output is asserted, whichever arrives at the later timing);
determining whether the host device is performing an access operation (FIG. 5 Command/Data; [0034] The timer 46 is reset by a controller 50 each time the command is received from a host 1, and its time measuring operation is restarted at a point in time when the command is received); and
setting the waiting time as a second time value (FIG. 7 S504 Is Tc Expired) in response to the host device being performing the access operation ([0033] a predetermined delay time (waiting time) Tc having elapsed since a command is received just before an LPD output is asserted is added to conditions for transitioning to a low power consumption mode. In the second embodiment, the transition to the low power consumption mode is performed at either a first point in time when a waiting time Te has elapsed since the LPD output is asserted, or a second point in time when a waiting time Tc has elapsed since a command is received just before the point in time when the LPD output is asserted, whichever arrives at a later timing), wherein the first time value is smaller than the second time value ([0033] Tc>Te).
The motivation for combining is based on the same rational presented for rejection of independent claim 7.
Regarding claim 18, Tanaka further discloses:
The memory controller according to claim 17, wherein the first time value is greater than or equal to 0ms ([0037] the controller 50 activates the timer 45 to start measuring time (step S501). The controller 50 determines whether the time measured by the timer 45 has exceeded the predetermined delay time Te or not (step S502); It would be obvious to one skilled in the art before the effective filing date of the claimed invention that the first time value is greater than or equal to 0ms because a timer measures positive increments of time from 0, see also FIG. 3), and…
Tanaka does not appear to explicitly teach “the second time value is greater than or equal to 20ms.” However, Muthiah further discloses:
the second time value is greater than or equal to 20ms ([0014] the controller is further configured to determine an amount of time needed to execute the command, and wherein the request to extend the time-out window is based on the determined amount of time; [0015] the amount of time needed to execute the command is based on…a time to transfer data to the host; [0059] consider the situation of a write command with a 250 millisecond (ms) sector-wise time allowance. The storage system 100 can communicate/request an extra 50 ms for a specific sector in a given command according to its latency evaluation. The storage system 100 can use this time (250 ms+50 ms=300 ms) for longer operations).
Claims 10-12, 15-16, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Tanaka and Muthiah as applied to claim 9 above, and further in view of Kumar et al. and Song et al.
Regarding claim 10, Tanaka further discloses:
The memory device according to claim 9, wherein the memory controller is configured to detect whether a read instruction or a write instruction is received from the host device ([0021] The controller 50 controls operations of the memory system 100 such as write control of data to which a write request has been made from the host 1, and a read control of data to which the read request has been made from the host 1); and
Tanaka and Muthiah do not appear to explicitly teach “when the read instruction or the write instruction is detected and at least one of the following conditions is satisfied, the memory controller is configured to determine that the host device is performing the access operation: if a volume of data read or written is greater than a first threshold after the read instruction or the write instruction is performed; or if a quantity of read instructions or write instructions continuously performed is greater than a second threshold after the read instruction or the write instruction is performed.” However, Kumar et al. disclose:
when the read instruction or the write instruction is detected and at least one of the following conditions is satisfied, the memory controller is configured to determine that the host device is performing the access operation:
if a volume of data read or written is greater than a first threshold after the read instruction or the write instruction is performed ([0028] commands for data transfer for each source-destination pair are tracked and are accumulated before generating read requests using the read request generator 104 and reading the data corresponding to the read requests from the corresponding source 107. The commands for data transfer may be accumulated in the command processing unit 102. When an amount of data corresponding to the accumulated commands for data transfer for a source-destination pair is below a predefined threshold, the corresponding read requests are not yet generated and therefore data corresponding to the read requests are not yet read from the data source 107. In addition, the RAM buffer corresponding to the source-destination pair is maintained in the power saving mode. When the amount of data corresponding to the accumulated commands for data transfer for the source-destination pair surpasses the threshold, the read requests corresponding to the commands for data transfer may be generated and data corresponding to the read requests may be read from the data source 107);
Tanaka, Muthiah, and Kumar et al. are analogous art because Tanaka teach transitioning to a low power consumption mode in a memory system; Muthiah teach memory device timeout; and Kumar et al. teach power saving in data transfer within a memory system.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Tanaka, Muthiah, and Kumar et al. before him/her, to modify the combined teachings of Tanaka and Muthiah with the teachings of Kumar et al. because performing the access operation after the accumulation of a threshold volume of data would avoid higher power consumption and delay in data transfer (Kumar et al. [0027]).
Tanaka, Muthiah, and Kumar et al. do not appear to explicitly teach “or if a quantity of read instructions or write instructions continuously performed is greater than a second threshold after the read instruction or the write instruction is performed.” However, Song et al. disclose:
or if a quantity of read instructions or write instructions continuously performed is greater than a second threshold after the read instruction or the write instruction is performed ([0086] If the quantity of queued commands is less than a threshold quantity (e.g., if the quantity of queued commands is zero), the power mode controller 330 may transition the non-volatile memory 325 from a higher power mode (e.g., a standby mode, an active mode) to a lower power mode. Such a technique may reduce the power consumption of the non-volatile memory 325 by allowing the non-volatile memory 325 to transition to a lower power mode if there is a break in accessing the non-volatile memory 325).
Tanaka, Muthiah, Kumar et al., and Song et al. are analogous art because Tanaka teach transitioning to a low power consumption mode in a memory system; Muthiah teach memory device timeout; Kumar et al. teach power saving in data transfer within a memory system; and Song et al. teach power mode control in a memory system.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Tanaka, Muthiah, Kumar et al., and Song et al. before him/her, to modify the combined teachings of Tanaka, Muthiah, and Kumar et al. with the teachings of Song et al. because performing the access operations when the quantity of instructions continuously performed is above a threshold would avoid higher power consumption by maintain a low-power mode while there is a break in accessing the non-volatile memory (Song et al. [0085]).
Regarding claim 11, Song et al. further disclose that the second threshold is zero, see paragraph [0086]. However, it would be obvious to one skilled in the art before the effective filing date of the claimed invention to modify the threshold level taught by Song et al. to two. The setting of the threshold quantity is a design choice and setting the threshold to two would enable the system to avoid higher power consumption by remaining in a low-power mode longer. Therefore, the combination of Tanaka, Muthiah, Kumar et al., and Song et al. further disclose the limitation:
The memory device according to claim 10, wherein the second threshold is at least two.
Regarding claim 12, Kumar et al. further disclose:
The memory device according to claim 10, wherein the first threshold is greater than or equal to 512Kb ([0034] The predefined threshold may be a configurable value and may be configured to ensure an optimal trade-off between power saving and delay in servicing of read requests due to accumulation of the commands for data transfer; Based on the teachings of Kumar, it would be obvious to one skilled in the art before the effective filing date of the claimed invention to set the first threshold to greater than or equal to 512Kb. The setting of the threshold is a design choice to ensure an optimal trade-off between power saving and delay in servicing of read requests due to accumulation of the commands for data transfer).
Regarding claim 15, Tanaka further discloses:
The electronic device according to claim 13, wherein the memory controller is configured to detect whether a read instruction or a write instruction is received from the host device ([0021] The controller 50 controls operations of the memory system 100 such as write control of data to which a write request has been made from the host 1, and a read control of data to which the read request has been made from the host 1); and
Tanaka and Muthiah do not appear to explicitly teach “when the read instruction or the write instruction is detected and at least one of the following conditions is satisfied, the memory controller is configured to determine that the host device is performing the access operation: if a volume of data read or written is greater than a first threshold after the read instruction or the write instruction is performed; or if a quantity of read instructions or write instructions continuously performed is greater than a second threshold after the read instruction or the write instruction is performed.” However, Kumar et al. disclose:
when the read instruction or the write instruction is detected and at least one of the following conditions is satisfied, the memory controller is configured to determine that the host device is performing the access operation:
if a volume of data read or written is greater than a first threshold after the read instruction or the write instruction is performed ([0028] commands for data transfer for each source-destination pair are tracked and are accumulated before generating read requests using the read request generator 104 and reading the data corresponding to the read requests from the corresponding source 107. The commands for data transfer may be accumulated in the command processing unit 102. When an amount of data corresponding to the accumulated commands for data transfer for a source-destination pair is below a predefined threshold, the corresponding read requests are not yet generated and therefore data corresponding to the read requests are not yet read from the data source 107. In addition, the RAM buffer corresponding to the source-destination pair is maintained in the power saving mode. When the amount of data corresponding to the accumulated commands for data transfer for the source-destination pair surpasses the threshold, the read requests corresponding to the commands for data transfer may be generated and data corresponding to the read requests may be read from the data source 107);
Tanaka, Muthiah, and Kumar et al. do not appear to explicitly teach “or if a quantity of read instructions or write instructions continuously performed is greater than a second threshold after the read instruction or the write instruction is performed.” However, Song et al. disclose:
or if a quantity of read instructions or write instructions continuously performed is greater than a second threshold after the read instruction or the write instruction is performed ([0086] If the quantity of queued commands is less than a threshold quantity (e.g., if the quantity of queued commands is zero), the power mode controller 330 may transition the non-volatile memory 325 from a higher power mode (e.g., a standby mode, an active mode) to a lower power mode. Such a technique may reduce the power consumption of the non-volatile memory 325 by allowing the non-volatile memory 325 to transition to a lower power mode if there is a break in accessing the non-volatile memory 325).
Regarding claim 16, Kumar et al. further disclose:
The electronic device according to claim 15…and the first threshold is greater than or equal to 512Kb ([0034] The predefined threshold may be a configurable value and may be configured to ensure an optimal trade-off between power saving and delay in servicing of read requests due to accumulation of the commands for data transfer; Based on the teachings of Kumar, it would be obvious to one skilled in the art before the effective filing date of the claimed invention to set the first threshold to greater than or equal to 512Kb. The setting of the threshold is a design choice to ensure an optimal trade-off between power saving and delay in servicing of read requests due to accumulation of the commands for data transfer).
Song et al. further disclose that the second threshold is zero, see paragraph [0086]. However, it would be obvious to one skilled in the art before the effective filing date of the claimed invention to modify the threshold level taught by Song et al. to two. The setting of the threshold quantity is a design choice and setting the threshold to two would enable the system to avoid higher power consumption by remaining in a low-power mode longer. Therefore, the combination of Tanaka, Muthiah, Kumar et al., and Song et al. further disclose the limitation:
wherein the second threshold is at least two,
Regarding claim 19, Tanaka further discloses:
The memory controller according to claim 17, wherein the memory controller detects whether a read instruction or a write instruction is received from the host device ([0021] The controller 50 controls operations of the memory system 100 such as write control of data to which a write request has been made from the host 1, and a read control of data to which the read request has been made from the host 1); and
Tanaka and Muthiah do not appear to explicitly teach “when the read instruction or the write instruction is detected and at least one of the following conditions is satisfied, the memory controller is configured to determine that the host device is performing the access operation: if a volume of data read or written is greater than a first threshold after the read instruction or the write instruction is performed; or if a quantity of read instructions or write instructions continuously performed is greater than a second threshold after the read instruction or the write instruction is performed.” However, Kumar et al. disclose:
when the read instruction or the write instruction is detected and at least one of the following conditions is satisfied, the memory controller is configured to determine that the host device is performing the access operation:
if a volume of data read or written is greater than a first threshold after the read instruction or the write instruction is performed ([0028] commands for data transfer for each source-destination pair are tracked and are accumulated before generating read requests using the read request generator 104 and reading the data corresponding to the read requests from the corresponding source 107. The commands for data transfer may be accumulated in the command processing unit 102. When an amount of data corresponding to the accumulated commands for data transfer for a source-destination pair is below a predefined threshold, the corresponding read requests are not yet generated and therefore data corresponding to the read requests are not yet read from the data source 107. In addition, the RAM buffer corresponding to the source-destination pair is maintained in the power saving mode. When the amount of data corresponding to the accumulated commands for data transfer for the source-destination pair surpasses the threshold, the read requests corresponding to the commands for data transfer may be generated and data corresponding to the read requests may be read from the data source 107);
Tanaka, Muthiah, and Kumar et al. do not appear to explicitly teach “if a quantity of read instructions or write instructions continuously performed is greater than a second threshold after the read instruction or the write instruction is performed.” However, Song et al. disclose:
or if a quantity of read instructions or write instructions continuously performed is greater than a second threshold after the read instruction or the write instruction is performed ([0086] If the quantity of queued commands is less than a threshold quantity (e.g., if the quantity of queued commands is zero), the power mode controller 330 may transition the non-volatile memory 325 from a higher power mode (e.g., a standby mode, an active mode) to a lower power mode. Such a technique may reduce the power consumption of the non-volatile memory 325 by allowing the non-volatile memory 325 to transition to a lower power mode if there is a break in accessing the non-volatile memory 325).
Regarding claim 20, Kumar et al. further disclose:
The memory controller according to claim 19…and the first threshold is greater than or equal to 512Kb ([0034] The predefined threshold may be a configurable value and may be configured to ensure an optimal trade-off between power saving and delay in servicing of read requests due to accumulation of the commands for data transfer. The setting of the threshold is a design choice to ensure an optimal trade-off between power saving and delay in servicing of read requests due to accumulation of the commands for data transfer).
Song et al. further disclose that the second threshold is zero, see paragraph [0086]. However, it would be obvious to one skilled in the art before the effective filing date of the claimed invention to modify the threshold level taught by Song et al. to two. The setting of the threshold quantity is a design choice and setting the threshold to two would enable the system to avoid higher power consumption by remaining in a low-power mode longer. Therefore, the combination of Tanaka, Muthiah, Kumar et al., and Song et al. further disclose the limitation:
wherein the second threshold is at least two,
Response to Arguments
Applicant's arguments filed December 23, 2025 have been fully considered but they are not persuasive.
Regarding the substance of the examiner’s anticipation rejection as argued on pages 8-9 of the remarks, the requirements for anticipation are discussed in MPEP § 2131, the requirements for giving claims their broadest reasonable interpretation in lights of the specification are discussed in MPEP § 2111, and the requirements for determining the plain meaning of a terms are discussed in MPEP § 2111.01.
Applicant’s remarks have been fully considered. However, the rejection of claim 1 under 35 U.S.C. 102(a)(1) as unpatentable over Tanaka is determined to be proper and is, therefore, maintained.
Applicant argues that Tanaka does not disclose the limitations “determining whether the host device is performing an access operation; and setting the waiting time as a second time value in response to the host device being performing the access operation.” The examiner disagrees. Applicant appears to be arguing that Tanaka’s invention is different than the inventive concept taught in the instant specification because Tanaka employs a different logic (Remarks page 8, paragraphs 1-3). But the prior art is applied to the claims as recited. The claims require “determining whether the host device is performing an access operation; and setting the waiting time as a second time value in response to the host device being performing the access operation.” The teachings of Tanaka disclose that a timer is reset by a controller each time the command is received from a host (paragraph [0034]) which reads on the limitation “determining whether the host device is performing an access operation.” Tanaka further teaches that a second waiting time (FIG. 7 Tc) is set from the time the command is received (paragraph [0033]). Therefore, Tanaka anticipates the limitations “determining whether the host device is performing an access operation; and setting the waiting time as a second time value in response to the host device being performing the access operation.”
The rejection of claim 1 as anticipated over Tanaka is therefore maintained.
In response to applicant's argument that the technical objective of the present application is not the same as the technical objective that is achieved by Tanaka (Remarks page 8, paragraph 4), the fact that the inventor has recognized another advantage which would flow naturally from following the suggestion of the prior art cannot be the basis for patentability when the differences would otherwise be obvious. See Ex parte Obiaya, 227 USPQ 58, 60 (Bd. Pat. App. & Inter. 1985).
Conclusion
All claims are identical to or patentably indistinct from, or have unity of invention with claims in the application prior to the entry of the submission under 37 CFR 1.114 (that is, restriction (including a lack of unity of invention) would not be proper) and all claims could have been finally rejected on the grounds and art of record in the next Office action if they had been entered in the application prior to entry under 37 CFR 1.114. Accordingly, THIS ACTION IS MADE FINAL even though it is a first action after the filing of a request for continued examination and the submission under 37 CFR 1.114. See MPEP § 706.07(b). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/TRACY A WARREN/Primary Examiner, Art Unit 2137