DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
Claims 1, 10 and 16 have been amended. Claim 21 remains cancelled. Claims 1-20 remain pending and are ready for examination.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-2, 4-9 and 16-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jayaraman et al. (US Publication No. 2023/0236995 – “Jayaraman”) in view of Nam et al. (US Publication No. 2022/0147476 – “Nam”).
Regarding claim 1, Jayaraman teaches An operation method of a storage device which is connected to a compute express link (CXL) switch, the method comprising: receiving, by the storage device, a first access request from a first host through the CXL switch; (Jayaraman paragraph [0020], A recent solution to address computational overhead associated with moving/copying data from one system or processing node to other system or processing nodes can include shared fabric attached memory (FAM) as described in CXL 3.0. or subsequent CXL specifications. Shared FAM can allow coherent memory sharing of a host managed device memory (HDM) region of a memory device (e.g., Type 3 CXL device) that is connected behind a CXL switch. A host can communicate and perform processing with a storage/memory device through a CXL switch) performing, by the storage device, an operation corresponding to the first access request; (Jayaraman paragraph [0026], According to some examples, for CXL.mem based HDM-DB mapped shared memory, logic and/or features of an ECB such as CX: translation logic 133 of ECB 132 can convert incoming master to subordinate (M2S) request messages received from secondary nodes 120-S1, S2 or S3 to device to host (D2H) request messages (e.g., RdShared/RdOwn requests) to be relayed to primary node 110-P. The logic and/or features of ECB 132 such as CXL translation logic 133 can complete an M2S/D2H transaction by returning/writing the latest data after resolution of coherency. The operation on memory may be performed due to a host request) detecting, by the storage device, a change in first metadata managed by the first host, based on the first access request; (Jayaraman paragraph [0063], FIG. 7 illustrates an example flow 700. According to some examples, flow 700 shows an example of a core at CPU 122-1-S1 of secondary node 120-S1 writing to a shared memory region such as shared region 117 mapped to memory 114-P at primary node 110-P. For these examples, similar to flow 600, logic and/or features of ECB 132 translates or converts M2S/D2H, S2M/H2D requests/messages and H2D snoops generated by primary node 110-P or secondary nodes 120-S1, S2, S3 according to CXL 2.0, CXL 3.0 or subsequent CXL specification protocols. Flow 700 is not limited to the elements of system 100 shown in FIG. 7. For example, logic and/or features of ECB 132 such as CXL translation logic 133, snoop logic 135, device cache 136 or data buffer 137 can facilitate one or more aspects of translation/conversions of M2S/D2H requests or H2D snoops. Also, CXL links 130-1 to 130-4 can be used to exchange requests/messages. Metadata for the corresponding memory (such as address information) can be modified and updated based on access requests through the CXL switch) and transmitting first update information corresponding to the change in the first metadata to a second host sharing the storage device through the CXL switch (Jayaraman paragraph [0057], Moving to 6.11 (SF hit for Addr Y, updated to include CXL device), the CA of CPU 112-1-P that it has a cache line hit for its own, separately maintained SF table for Addr Y and updates that table to include a CXL device. According to some examples, the CXL device is based on the CA of CPU 112-1-P's impression that the D2H: RdShared Y message received at 6.7 from ECB 132 was sent by a CXL device but due to the conversion of the M2S message received by ECB 132 at 6.3 to the D2H: RdShared Y message, the request to read from Addr Y was actually made by another host (H) and not an CXL device (D). The access request may require updating metadata (i.e., address information) and can utilize a different host through the CXL switch).
Jayaraman does not teach in response to detecting the change in the first metadata, transmitting first update information…
However, Nam teaches in response to detecting the change in the first metadata, transmitting first update information… (Nam paragraph [0087], Moreover, the DCOH 440 may correspond to an agent that is arranged to solve coherency in relation to a device cache on a device. The DCOH 440 may perform a coherency-related function, such as the updating of metadata fields, based on processing results of the command executor 430 and the DMA engine 410 and provide update results to the command executor 430. The accelerator logic 450 may request access to the memory 420 through the memory controller and also, request access to a memory arranged outside the device 400 in a system. Nam teaches detecting a change to metadata and transmitting update information as part of a coherency operation).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Jayaraman with those of Nam. Nam teaches detecting an update to metadata and transmitting related update information, which assists in maintaining coherency in the storage device, and improve data transactions (i.e., see Nam paragraph [0038], According to the example embodiment as described above, data transfer efficiency between logical devices recognized as different devices in the same memory device may be improved. For example, a copy function may be performed using a DMA engine in a memory device without processing data read from a memory region, based on a predetermined protocol, to transmit the read data to a memory region. Accordingly, a latency of a data processing operation may be reduced, and data traffic of the interconnect may be reduced).
Regarding claim 2, Jayaraman in view of Nam teaches The method of claim 1, wherein the first access request includes a first address corresponding to a storage area of the storage device, and wherein the first update information includes the first address (Jayaraman paragraph [0025], According to some examples, as shown in FIG. 1, primary node 110-P includes a memory 114-P. For these examples, a system address memory map 115-P can represent a map of host physical addresses (HPAs) of memory 114-P. Primary node 110-P, in some examples, can earmark a region of memory 114-P from system address memory map 115-P and include that earmarked region in shared region 117. A mapping table may be used to indicate and update memory address information regarding the storage device connected to the host).
Regarding claim 4, Jayaraman in view of Nam teaches The method of claim 2, wherein the first access request is based on a CXL.mem protocol being a memory access protocol supporting a memory access, and wherein the first address is a memory physical address indicating an area of a system memory managed by the first host (Jayaraman paragraph [0025], According to some examples, as shown in FIG. 1, primary node 110-P includes a memory 114-P. For these examples, a system address memory map 115-P can represent a map of host physical addresses (HPAs) of memory 114-P. Primary node 110-P, in some examples, can earmark a region of memory 114-P from system address memory map 115-P and include that earmarked region in shared region 117. In some examples, shared region 117 can be shared with secondary nodes 120-S1, S2, S3 and mapped by these secondary systems in their respective system address memory maps 125-S1, S2, S3. System address memory maps 125-S1, S2, S3 can separately represent a map of HPAs of a respective memory 124-S1, S2, S3. Mapped shared memory for secondary node 120-S1, for example, is shown in FIG. 1 as shared map 127-S1. Shared maps 127-S1, S2, S3 can be mapped to regions of respective memories 124-S1, S2, S3 as a CXL.mem based HDM device coherent (HDM-D) as described by CXL 2.0 and/or CXL 3.0 or as a CXL.mem based HDM device coherent using back-invalidation (HDM-DB) as described by CXL 3.0 or subsequent CXL specifications. As described more below, logic and/or features of an ECB such as CXL translation logic 133 of ECB 132 can be arranged to use back invalidate flows to resolve coherency for shared maps 127-S1, S2, S3 of secondary nodes 120-S1, S2, S3 mapped using CXL.mem based HDM-DB. If shared maps 127-S1, S2, S3 are mapped using CXL.mem based HDM-D, shared maps 127-S1, S2, S3 can map to a non-cacheable region to avoid bias-flip. The access request may be a CXL.mem protocol using address information mapping via the host).
Regarding claim 5, Jayaraman in view of Nam teaches The method of claim 1, wherein the first host manages a storage area of the storage device, based on the first metadata, and wherein the second host manages the storage area of the storage device, based on second metadata (Jayaraman paragraph [0020], recent solution to address computational overhead associated with moving/copying data from one system or processing node to other system or processing nodes can include shared fabric attached memory (FAM) as described in CXL 3.0. or subsequent CXL specifications. Shared FAM can allow coherent memory sharing of a host managed device memory (HDM) region of a memory device (e.g., Type 3 CXL device) that is connected behind a CXL switch. The shared FAM, for example, may allow for sharing the HDM region between multiple hosts (system or processing nodes). Multiple hosts can utilize a shared managed device memory region. This can be done based on corresponding metadata responsive to the respective host requests, such as in Jayaraman paragraph [0026], According to some examples, for CXL.mem based HDM-DB mapped shared memory, logic and/or features of an ECB such as CX: translation logic 133 of ECB 132 can convert incoming master to subordinate (M2S) request messages received from secondary nodes 120-S1, S2 or S3 to device to host (D2H) request messages (e.g., RdShared/RdOwn requests) to be relayed to primary node 110-P. The logic and/or features of ECB 132 such as CXL translation logic 133 can complete an M2S/D2H transaction by returning/writing the latest data after resolution of coherency. CXL translation logic 133 can also convert host to device (H2D) snoops from primary node 110-P to back-invalidate snoops on secondary nodes 120-S1, S2 or S3 and completes an H2D transaction by returning the latest version of the requested data from secondary nodes 120-S1, S2, or S3. In some examples, CXL translation logic 133 in cooperation with snoop logic 135 can perform offset adjustments as transactions/messages flow between primary node 110-P and secondary nodes 120-S1, S2, or S3 and/or as transactions/messages flow between secondary nodes 120-S1, S2, or S3).
Regarding claim 6, Jayaraman in view of Nam teaches The method of claim 5, wherein the second host updates the second metadata, based on the first update information (Jayaraman paragraph [0026], According to some examples, for CXL.mem based HDM-DB mapped shared memory, logic and/or features of an ECB such as CX: translation logic 133 of ECB 132 can convert incoming master to subordinate (M2S) request messages received from secondary nodes 120-S1, S2 or S3 to device to host (D2H) request messages (e.g., RdShared/RdOwn requests) to be relayed to primary node 110-P. The logic and/or features of ECB 132 such as CXL translation logic 133 can complete an M2S/D2H transaction by returning/writing the latest data after resolution of coherency. CXL translation logic 133 can also convert host to device (H2D) snoops from primary node 110-P to back-invalidate snoops on secondary nodes 120-S1, S2 or S3 and completes an H2D transaction by returning the latest version of the requested data from secondary nodes 120-S1, S2, or S3. In some examples, CXL translation logic 133 in cooperation with snoop logic 135 can perform offset adjustments as transactions/messages flow between primary node 110-P and secondary nodes 120-S1, S2, or S3 and/or as transactions/messages flow between secondary nodes 120-S1, S2, or S3. The metadata can be updated based on operations/requests between the memory and the hosts).
Regarding claim 7, Jayaraman in view of Nam teaches The method of claim 1, further comprising: transmitting the first update information to a third host sharing the storage device through the CXL switch (Jayaraman paragraph [0020], A recent solution to address computational overhead associated with moving/copying data from one system or processing node to other system or processing nodes can include shared fabric attached memory (FAM) as described in CXL 3.0. or subsequent CXL specifications. Shared FAM can allow coherent memory sharing of a host managed device memory (HDM) region of a memory device (e.g., Type 3 CXL device) that is connected behind a CXL switch. The shared FAM, for example, may allow for sharing the HDM region between multiple hosts (system or processing nodes). The memory system can utilize a plurality hosts, including a third host, which receives update information through a CXL switch).
Regarding claim 8, Jayaraman in view of Nam teaches The method of claim 1, further comprising: receiving a second access request from the second host through the CXL switch; performing an operation corresponding to the second access request; (Jayaraman paragraph [0063], FIG. 7 illustrates an example flow 700. According to some examples, flow 700 shows an example of a core at CPU 122-1-S1 of secondary node 120-S1 writing to a shared memory region such as shared region 117 mapped to memory 114-P at primary node 110-P. For these examples, similar to flow 600, logic and/or features of ECB 132 translates or converts M2S/D2H, S2M/H2D requests/messages and H2D snoops generated by primary node 110-P or secondary nodes 120-S1, S2, S3 according to CXL 2.0, CXL 3.0 or subsequent CXL specification protocols. Flow 700 is not limited to the elements of system 100 shown in FIG. 7. For example, logic and/or features of ECB 132 such as CXL translation logic 133, snoop logic 135, device cache 136 or data buffer 137 can facilitate one or more aspects of translation/conversions of M2S/D2H requests or H2D snoops. Also, CXL links 130-1 to 130-4 can be used to exchange requests/messages. Metadata for the corresponding memory (such as address information) can be modified and updated based on access requests through the CXL switch) detecting a change in second metadata managed by the second host, based on the second access request; (Jayaraman paragraph [0063], FIG. 7 illustrates an example flow 700. According to some examples, flow 700 shows an example of a core at CPU 122-1-S1 of secondary node 120-S1 writing to a shared memory region such as shared region 117 mapped to memory 114-P at primary node 110-P. For these examples, similar to flow 600, logic and/or features of ECB 132 translates or converts M2S/D2H, S2M/H2D requests/messages and H2D snoops generated by primary node 110-P or secondary nodes 120-S1, S2, S3 according to CXL 2.0, CXL 3.0 or subsequent CXL specification protocols. Flow 700 is not limited to the elements of system 100 shown in FIG. 7. For example, logic and/or features of ECB 132 such as CXL translation logic 133, snoop logic 135, device cache 136 or data buffer 137 can facilitate one or more aspects of translation/conversions of M2S/D2H requests or H2D snoops. Also, CXL links 130-1 to 130-4 can be used to exchange requests/messages. Metadata for the corresponding memory (such as address information) can be modified and updated based on access requests through the CXL switch) and transmitting second update information corresponding to the change in the second metadata to the first host sharing the storage device through the CXL switch (Jayaraman paragraph [0057], Moving to 6.11 (SF hit for Addr Y, updated to include CXL device), the CA of CPU 112-1-P that it has a cache line hit for its own, separately maintained SF table for Addr Y and updates that table to include a CXL device. According to some examples, the CXL device is based on the CA of CPU 112-1-P's impression that the D2H: RdShared Y message received at 6.7 from ECB 132 was sent by a CXL device but due to the conversion of the M2S message received by ECB 132 at 6.3 to the D2H: RdShared Y message, the request to read from Addr Y was actually made by another host (H) and not an CXL device (D). The access request may require updating metadata (i.e., address information) and can utilize a different host through the CXL switch).
Regarding claim 9, Jayaraman in view of Nam teaches The method of claim 1, wherein the performing of the operation corresponding to the first access request includes: transmitting first data stored in the storage device to an external storage device through the CXL switch in response to the first access request (Jayaraman Fig. 5; see system address mapping via CXL switch and interface; also see Jayaraman paragraph [0044], FIG. 5 illustrates example system address maps 500. In some examples, system address maps 500 provides an example illustration of how shared region 117 of system address memory map 115-P for primary node 110-P memory 114-P can be mapped to system address memory maps 125, S1, S2, S3 of respective secondary nodes 120-S1, S2, S3 as mentioned above and shown in FIG. 1. For these examples, primary node 110-P earmarks 4 gigabytes (GB) of DDR memory (62 GB to 66 GB) from system address memory map 115-P and includes this earmarked DDR memory in shared region 117. Shared region 117 can then be mapped in system address memory maps 125-S1, S2, S3 of secondary nodes 120-S1, S2, S3, for example, by a memory hole covered by a CXL.mem related HDM-DB source address decoder (SAD) entry. Secondary nodes 120-S1 and 120-S2, for example, can allow access to this region of memory (127-S1, 127-S2) by providing an address ranged between 70 GB to 74 GB while secondary node 120-S3 can allow access to this region (127-S3) between 66 GB and 70 GB. Earmarked shared memory from primary node 110-P (4 GB between 62 GB and 66 GB) can be read or written by secondary nodes 120-S1 or 120-S2 using the 70 GB to 74 GB address range. This can allow multiple software threads to be spawned across primary node 110-P and secondary nodes 120-S1, S2, S3 with the shared memory region to pass-over data from producer threads to consumer threads without a need for double copying. Also, coherency semantics provided by, for example, CXL 3.0 can be leveraged to manage and resolve coherency aspects (described more below)).
Regarding claim 16, Jayaraman teaches An operation method comprising providing a storage system comprising: a compute express link (CXL) switch; a first storage device connected to the CXL switch; a first host connected to the CXL switch; and a second host connected to the CXL switch, the method comprising; (Jayaraman paragraph [0020], A recent solution to address computational overhead associated with moving/copying data from one system or processing node to other system or processing nodes can include shared fabric attached memory (FAM) as described in CXL 3.0. or subsequent CXL specifications. Shared FAM can allow coherent memory sharing of a host managed device memory (HDM) region of a memory device (e.g., Type 3 CXL device) that is connected behind a CXL switch. A plurality of hosts can communicate and perform processing with a storage/memory device through a CXL switch) transmitting, by the first host, a first access request corresponding to a storage area of the first storage device to the first storage device through the CXL switch (Jayaraman paragraph [0020], A recent solution to address computational overhead associated with moving/copying data from one system or processing node to other system or processing nodes can include shared fabric attached memory (FAM) as described in CXL 3.0. or subsequent CXL specifications. Shared FAM can allow coherent memory sharing of a host managed device memory (HDM) region of a memory device (e.g., Type 3 CXL device) that is connected behind a CXL switch. A host can communicate and perform processing with a storage/memory device through a CXL switch) and updating first metadata; (Jayaraman paragraph [0057], Moving to 6.11 (SF hit for Addr Y, updated to include CXL device), the CA of CPU 112-1-P that it has a cache line hit for its own, separately maintained SF table for Addr Y and updates that table to include a CXL device. According to some examples, the CXL device is based on the CA of CPU 112-1-P's impression that the D2H: RdShared Y message received at 6.7 from ECB 132 was sent by a CXL device but due to the conversion of the M2S message received by ECB 132 at 6.3 to the D2H: RdShared Y message, the request to read from Addr Y was actually made by another host (H) and not an CXL device (D). The access request may require updating metadata (i.e., address information) and can utilize a different host through the CXL switch) receiving, by the first storage device, the first access request through the CXL switch and performing an operation corresponding to the first access request; (Jayaraman paragraph [0020], A recent solution to address computational overhead associated with moving/copying data from one system or processing node to other system or processing nodes can include shared fabric attached memory (FAM) as described in CXL 3.0. or subsequent CXL specifications. Shared FAM can allow coherent memory sharing of a host managed device memory (HDM) region of a memory device (e.g., Type 3 CXL device) that is connected behind a CXL switch. A host can communicate and perform processing with a storage/memory device through a CXL switch) detecting, by the first storage device, a change in the first metadata and transmitting first update information corresponding to the change in the first metadata to the second host through the CXL switch; (Jayaraman paragraph [0063], FIG. 7 illustrates an example flow 700. According to some examples, flow 700 shows an example of a core at CPU 122-1-S1 of secondary node 120-S1 writing to a shared memory region such as shared region 117 mapped to memory 114-P at primary node 110-P. For these examples, similar to flow 600, logic and/or features of ECB 132 translates or converts M2S/D2H, S2M/H2D requests/messages and H2D snoops generated by primary node 110-P or secondary nodes 120-S1, S2, S3 according to CXL 2.0, CXL 3.0 or subsequent CXL specification protocols. Flow 700 is not limited to the elements of system 100 shown in FIG. 7. For example, logic and/or features of ECB 132 such as CXL translation logic 133, snoop logic 135, device cache 136 or data buffer 137 can facilitate one or more aspects of translation/conversions of M2S/D2H requests or H2D snoops. Also, CXL links 130-1 to 130-4 can be used to exchange requests/messages. Metadata for the corresponding memory (such as address information) can be modified and updated based on access requests through the CXL switch) and receiving, by the second host, the first update information through the CXL switch and updating second metadata based on the first update information, wherein the first and second hosts share the first storage device, (Jayaraman paragraph [0057], Moving to 6.11 (SF hit for Addr Y, updated to include CXL device), the CA of CPU 112-1-P that it has a cache line hit for its own, separately maintained SF table for Addr Y and updates that table to include a CXL device. According to some examples, the CXL device is based on the CA of CPU 112-1-P's impression that the D2H: RdShared Y message received at 6.7 from ECB 132 was sent by a CXL device but due to the conversion of the M2S message received by ECB 132 at 6.3 to the D2H: RdShared Y message, the request to read from Addr Y was actually made by another host (H) and not an CXL device (D). The access request may require updating metadata (i.e., address information) and can utilize a different host through the CXL switch).
Jayaraman does not teach detecting … a change in the first metadata and transmitting, in response to the detecting, first update information.
However, Nam teaches detecting … a change in the first metadata and transmitting, in response to the detecting, first update information. (Nam paragraph [0087], Moreover, the DCOH 440 may correspond to an agent that is arranged to solve coherency in relation to a device cache on a device. The DCOH 440 may perform a coherency-related function, such as the updating of metadata fields, based on processing results of the command executor 430 and the DMA engine 410 and provide update results to the command executor 430. The accelerator logic 450 may request access to the memory 420 through the memory controller and also, request access to a memory arranged outside the device 400 in a system. Nam teaches detecting a change to metadata and transmitting update information as part of a coherency operation).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Jayaraman with those of Nam. Nam teaches detecting an update to metadata and transmitting related update information, which assists in maintaining coherency in the storage device, and improve data transactions (i.e., see Nam paragraph [0038], According to the example embodiment as described above, data transfer efficiency between logical devices recognized as different devices in the same memory device may be improved. For example, a copy function may be performed using a DMA engine in a memory device without processing data read from a memory region, based on a predetermined protocol, to transmit the read data to a memory region. Accordingly, a latency of a data processing operation may be reduced, and data traffic of the interconnect may be reduced).
Regarding claim 17, Jayaraman in view of Nam teaches The method of claim 16, wherein the first access request is based on a CXL.io being a PCI-e-based non-coherent input/output protocol or a CXL.mem protocol being a memory access protocol supporting a memory access (Jayaraman paragraph [0025], According to some examples, as shown in FIG. 1, primary node 110-P includes a memory 114-P. For these examples, a system address memory map 115-P can represent a map of host physical addresses (HPAs) of memory 114-P. Primary node 110-P, in some examples, can earmark a region of memory 114-P from system address memory map 115-P and include that earmarked region in shared region 117. In some examples, shared region 117 can be shared with secondary nodes 120-S1, S2, S3 and mapped by these secondary systems in their respective system address memory maps 125-S1, S2, S3. System address memory maps 125-S1, S2, S3 can separately represent a map of HPAs of a respective memory 124-S1, S2, S3. Mapped shared memory for secondary node 120-S1, for example, is shown in FIG. 1 as shared map 127-S1. Shared maps 127-S1, S2, S3 can be mapped to regions of respective memories 124-S1, S2, S3 as a CXL.mem based HDM device coherent (HDM-D) as described by CXL 2.0 and/or CXL 3.0 or as a CXL.mem based HDM device coherent using back-invalidation (HDM-DB) as described by CXL 3.0 or subsequent CXL specifications. As described more below, logic and/or features of an ECB such as CXL translation logic 133 of ECB 132 can be arranged to use back invalidate flows to resolve coherency for shared maps 127-S1, S2, S3 of secondary nodes 120-S1, S2, S3 mapped using CXL.mem based HDM-DB. If shared maps 127-S1, S2, S3 are mapped using CXL.mem based HDM-D, shared maps 127-S1, S2, S3 can map to a non-cacheable region to avoid bias-flip. The access request may be a CXL.mem protocol using address information mapping via the host).
Regarding claim 18, Jayaraman in view of Nam teaches The method of claim 16, wherein the storage system further includes a second storage device connected to the CXL switch, and wherein the performing of the operation corresponding to the first access request by the first storage device includes transmitting first data stored in the first storage device to the second storage device through the CXL switch (Jayaraman paragraph [0020], A recent solution to address computational overhead associated with moving/copying data from one system or processing node to other system or processing nodes can include shared fabric attached memory (FAM) as described in CXL 3.0. or subsequent CXL specifications. Shared FAM can allow coherent memory sharing of a host managed device memory (HDM) region of a memory device (e.g., Type 3 CXL device) that is connected behind a CXL switch. The shared FAM, for example, may allow for sharing the HDM region between multiple hosts (system or processing nodes). The memory system can utilize a plurality hosts, including a third host, which receives update information through a CXL switch).
Regarding claim 19, Jayaraman in view of Nam teaches The method of claim 18 further comprises: storing, by the second storage device, the first data received from the first storage device in a second storage area of the second storage device; (Jayaraman paragraph [0063], FIG. 7 illustrates an example flow 700. According to some examples, flow 700 shows an example of a core at CPU 122-1-S1 of secondary node 120-S1 writing to a shared memory region such as shared region 117 mapped to memory 114-P at primary node 110-P. For these examples, similar to flow 600, logic and/or features of ECB 132 translates or converts M2S/D2H, S2M/H2D requests/messages and H2D snoops generated by primary node 110-P or secondary nodes 120-S1, S2, S3 according to CXL 2.0, CXL 3.0 or subsequent CXL specification protocols. Flow 700 is not limited to the elements of system 100 shown in FIG. 7. For example, logic and/or features of ECB 132 such as CXL translation logic 133, snoop logic 135, device cache 136 or data buffer 137 can facilitate one or more aspects of translation/conversions of M2S/D2H requests or H2D snoops. Also, CXL links 130-1 to 130-4 can be used to exchange requests/messages. Metadata for the corresponding memory (such as address information) can be modified and updated based on access requests through the CXL switch) detecting, by the second storage device, the change in the first metadata and transmitting second update information corresponding to the change in the first metadata to the second host through the CXL switch; (Jayaraman paragraph [0063], FIG. 7 illustrates an example flow 700. According to some examples, flow 700 shows an example of a core at CPU 122-1-S1 of secondary node 120-S1 writing to a shared memory region such as shared region 117 mapped to memory 114-P at primary node 110-P. For these examples, similar to flow 600, logic and/or features of ECB 132 translates or converts M2S/D2H, S2M/H2D requests/messages and H2D snoops generated by primary node 110-P or secondary nodes 120-S1, S2, S3 according to CXL 2.0, CXL 3.0 or subsequent CXL specification protocols. Flow 700 is not limited to the elements of system 100 shown in FIG. 7. For example, logic and/or features of ECB 132 such as CXL translation logic 133, snoop logic 135, device cache 136 or data buffer 137 can facilitate one or more aspects of translation/conversions of M2S/D2H requests or H2D snoops. Also, CXL links 130-1 to 130-4 can be used to exchange requests/messages. Metadata for the corresponding memory (such as address information) can be modified and updated based on access requests through the CXL switch) and updating, by the second host, the second metadata based on the second update information, wherein the first and second hosts share the second storage device, wherein the first host further manages the second storage area of the second storage device, based on the first metadata, (Jayaraman paragraph [0057], Moving to 6.11 (SF hit for Addr Y, updated to include CXL device), the CA of CPU 112-1-P that it has a cache line hit for its own, separately maintained SF table for Addr Y and updates that table to include a CXL device. According to some examples, the CXL device is based on the CA of CPU 112-1-P's impression that the D2H: RdShared Y message received at 6.7 from ECB 132 was sent by a CXL device but due to the conversion of the M2S message received by ECB 132 at 6.3 to the D2H: RdShared Y message, the request to read from Addr Y was actually made by another host (H) and not an CXL device (D). The access request may require updating metadata (i.e., address information) and can utilize a different host through the CXL switch) and wherein the second host further manages the second storage area of the second storage device, based on the second metadata (Jayaraman paragraph [0020], recent solution to address computational overhead associated with moving/copying data from one system or processing node to other system or processing nodes can include shared fabric attached memory (FAM) as described in CXL 3.0. or subsequent CXL specifications. Shared FAM can allow coherent memory sharing of a host managed device memory (HDM) region of a memory device (e.g., Type 3 CXL device) that is connected behind a CXL switch. The shared FAM, for example, may allow for sharing the HDM region between multiple hosts (system or processing nodes). Multiple hosts can utilize a shared managed device memory region. This can be done based on corresponding metadata responsive to the respective host requests, such as in Jayaraman paragraph [0026], According to some examples, for CXL.mem based HDM-DB mapped shared memory, logic and/or features of an ECB such as CX: translation logic 133 of ECB 132 can convert incoming master to subordinate (M2S) request messages received from secondary nodes 120-S1, S2 or S3 to device to host (D2H) request messages (e.g., RdShared/RdOwn requests) to be relayed to primary node 110-P. The logic and/or features of ECB 132 such as CXL translation logic 133 can complete an M2S/D2H transaction by returning/writing the latest data after resolution of coherency. CXL translation logic 133 can also convert host to device (H2D) snoops from primary node 110-P to back-invalidate snoops on secondary nodes 120-S1, S2 or S3 and completes an H2D transaction by returning the latest version of the requested data from secondary nodes 120-S1, S2, or S3. In some examples, CXL translation logic 133 in cooperation with snoop logic 135 can perform offset adjustments as transactions/messages flow between primary node 110-P and secondary nodes 120-S1, S2, or S3 and/or as transactions/messages flow between secondary nodes 120-S1, S2, or S3).
Regarding claim 20, Jayaraman in view of Nam teaches The method of claim 16, wherein the storage system is a disaggregated storage system (Jayaraman paragraph [0003], Complex software applications executed within a data center having a disaggregated architecture can be built based on partitioning involved computations as software processes (or threads). Software processes (or threads) can be assigned to multiple hardware core/threads across different system or processing nodes. A system or processing node can be defined as a single platform that can include multiple compute cores/threads and executes its own system or platform firmware. Hence, a system or processing node can set up a single execution environment for higher layer software. Since a number of hardware cores/threads available on a system or processing node is limited, shared memories across different system or processing nodes can become necessary to communicate intermediate results of computation for complex software applications that can aggregate computation resources across the different system or processing nodes. The shared memories and different system or processing nodes can be interconnected via a switch fabric that includes CXL links or CXL over UCIe links).
Claim(s) 10-13 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jayaraman et al. (US Publication No. 2023/0236995 – “Jayaraman”) in view of Nam et al. (US Publication No. 2022/0147476 – “Nam”) in further view of Lee (US Publication No. 2024/0004580 – “Lee”).
Regarding claim 10, Jayaraman teaches A storage device comprising: a nonvolatile memory device; a random access memory (DRAM) device; (Jayaraman paragraph [0041], Volatile types of memory may include, but are not limited to, random-access memory (RAM), Dynamic RAM (DRAM), DDR synchronous dynamic RAM (DDR SDRAM), GDDR, HBM, static random-access memory (SRAM), thyristor RAM (T-RAM) or zero-capacitor RAM (Z-RAM). Non-volatile types of memory may include byte or block addressable types of non-volatile memory having a 3-dimensional (3-D) cross-point memory structure that includes, but is not limited to, chalcogenide phase change material (e.g., chalcogenide glass) hereinafter referred to as “3-D cross-point memory”. Non-volatile types of memory may also include other types of byte or block addressable non-volatile memory such as, but not limited to, multi-threshold level NAND flash memory, NOR flash memory, single or multi-level phase change memory (PCM)) and a controller configured to control the nonvolatile memory device and the DRAM device in response to a first access request received from a first host among a plurality of hosts, (Jayaraman paragraph [0041], Volatile types of memory may include, but are not limited to, random-access memory (RAM), Dynamic RAM (DRAM). For controller usage in the performance of the memory operations, see Jayaraman paragraphs [0018-0019], Another solution to address computational overhead associated with moving/copying data from one system or processing node to other system or processing nodes can involve use of extended node controllers (xNCs) configured to operate using Intel® Corporations Quick Path Interconnect (QPI)/Ultra Path Interconnect (UPI) protocols) wherein the controller includes: a compute express link (CXL) interface circuit connected to a CXL switch and configured to receive the first access request from the first host through the CXL switch; (Jayaraman paragraph [0020], A recent solution to address computational overhead associated with moving/copying data from one system or processing node to other system or processing nodes can include shared fabric attached memory (FAM) as described in CXL 3.0. or subsequent CXL specifications. Shared FAM can allow coherent memory sharing of a host managed device memory (HDM) region of a memory device (e.g., Type 3 CXL device) that is connected behind a CXL switch. A host can communicate and perform processing with a storage/memory device through a CXL switch) a NAND interface circuit configured to control the nonvolatile memory device, based on the first access request; (Jayaraman paragraph [0026], According to some examples, for CXL.mem based HDM-DB mapped shared memory, logic and/or features of an ECB such as CX: translation logic 133 of ECB 132 can convert incoming master to subordinate (M2S) request messages received from secondary nodes 120-S1, S2 or S3 to device to host (D2H) request messages (e.g., RdShared/RdOwn requests) to be relayed to primary node 110-P. The logic and/or features of ECB 132 such as CXL translation logic 133 can complete an M2S/D2H transaction by returning/writing the latest data after resolution of coherency. The operation on memory may be performed due to a host request, see NAND memory above) a DRAM controller configured to control the DRAM device, based on the first access request; (Jayaraman paragraph [0026], According to some examples, for CXL.mem based HDM-DB mapped shared memory, logic and/or features of an ECB such as CX: translation logic 133 of ECB 132 can convert incoming master to subordinate (M2S) request messages received from secondary nodes 120-S1, S2 or S3 to device to host (D2H) request messages (e.g., RdShared/RdOwn requests) to be relayed to primary node 110-P. The logic and/or features of ECB 132 such as CXL translation logic 133 can complete an M2S/D2H transaction by returning/writing the latest data after resolution of coherency. The operation on memory may be performed due to a host request, see DRAM above in Jayaraman [0041]) and a coherence circuit configured to detect a change in first metadata managed by the first host in response to the first access request and to transmit, in response to detecting the change in the first metadata, first update information corresponding to the change in the first metadata to other hosts sharing the storage device from among the plurality of hosts through the CXL switch (Jayaraman paragraph [0057], Moving to 6.11 (SF hit for Addr Y, updated to include CXL device), the CA of CPU 112-1-P that it has a cache line hit for its own, separately maintained SF table for Addr Y and updates that table to include a CXL device. According to some examples, the CXL device is based on the CA of CPU 112-1-P's impression that the D2H: RdShared Y message received at 6.7 from ECB 132 was sent by a CXL device but due to the conversion of the M2S message received by ECB 132 at 6.3 to the D2H: RdShared Y message, the request to read from Addr Y was actually made by another host (H) and not an CXL device (D). The access request may require updating metadata (i.e., address information) and can utilize a different host through the CXL switch).
Jayaraman does not teach a flash translation layer (FTL) configured to manage address mapping of the nonvolatile memory device; transmit, in response to detecting the change in the first metadata, first update information.
However, Nam teaches transmit, in response to detecting the change in the first metadata, first update information (Nam paragraph [0087], Moreover, the DCOH 440 may correspond to an agent that is arranged to solve coherency in relation to a device cache on a device. The DCOH 440 may perform a coherency-related function, such as the updating of metadata fields, based on processing results of the command executor 430 and the DMA engine 410 and provide update results to the command executor 430. The accelerator logic 450 may request access to the memory 420 through the memory controller and also, request access to a memory arranged outside the device 400 in a system. Nam teaches detecting a change to metadata and transmitting update information as part of a coherency operation).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Jayaraman with those of Nam. Nam teaches detecting an update to metadata and transmitting related update information, which assists in maintaining coherency in the storage device, and improve data transactions (i.e., see Nam paragraph [0038], According to the example embodiment as described above, data transfer efficiency between logical devices recognized as different devices in the same memory device may be improved. For example, a copy function may be performed using a DMA engine in a memory device without processing data read from a memory region, based on a predetermined protocol, to transmit the read data to a memory region. Accordingly, a latency of a data processing operation may be reduced, and data traffic of the interconnect may be reduced).
Jayaraman in view of Nam does not teach a flash translation layer (FTL) configured to manage address mapping of the nonvolatile memory device.
However, Lee teaches a flash translation layer (FTL) configured to manage address mapping of the nonvolatile memory device (Lee paragraph [0059], The FTL 620 may perform an NVM control operation in response to the control signal received through the CXL IO 610. For example, the FTL 620 may control an operation to write or program the data to the nonvolatile memory 125 in response to the received write request and may control an operation to read the data from the nonvolatile memory 125 in response to the read request. The FTL 620 may transmit the corresponding control signals to the NVM interface 630. The FTL 620 may perform an address mapping operation that maps the logical address of the host 20 to the physical address of the nonvolatile memory 125, in order to control the read operation or the write operation. The FTL may manage address mapping for commands from the host to the nonvolatile memory device).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Jayaraman and Nam with those of Lee. Lee teaches using a flash translation layer (FTL) for address mapping for NVM device command operations, which can improve address reliability and memory storage utilization (i.e., see Lee paragraphs [0050] and [0052], The nonvolatile memory 125 may store a logical to physical (L2P) map. The L2P map may include mapping information between a logical address in which the host 20 recognizes data as being stored and a physical address of the nonvolatile memory 125 in which the corresponding data is actually stored. When power is applied to the storage memory 120, the NVMC 121 may execute firmware (FW). When the nonvolatile memory 125 is a flash memory device, the NVMC 121 may execute firmware such as a flash translation layer (FTL) for data processing between the host 20 and the nonvolatile memory 125).
Regarding claim 11, Jayaraman in view of Nam in further view of Lee teaches The storage device of claim 10, wherein the coherence circuit includes a share table, and wherein the share table includes a port identifier and a callback parameter of each of the other hosts sharing the storage device (Jayaraman Fig. 4; see share table for identifiers and parameters, regarding callback parameters of other hosts, also see Jayaraman paragraph [0050], Moving to 6.4 (SF check; offset adj X->Y for P, offset adj X->Z for S2), logic and/or features of ECB 132 such as snoop logic 135 can check a snoop filter (SF) table (e.g., snoop filter table 400) to determine which nodes may have the cache line associated with the mapped shared region corresponding to Addr X. According to some examples, snoop logic 135 arrives at a result that indicates an SF hit for Addr X at primary node 110-P that has an offset adjustment to Addr X to arrive at Addr Y and also an SF hit for Addr X at secondary node 120-S2 that has an offset adjustment to Addr X to arrive at Addr Z).
Regarding claim 12, Jayaraman in view of Nam in further view of Lee teaches The storage device of claim 11, wherein the coherence circuit transmits the first update information to each of the other hosts, based on the port identifier and the callback parameter of the share table (Jayaraman Fig. 4; see share table for identifiers and parameters, regarding callback parameters of other hosts, also see Jayaraman paragraph [0050], Moving to 6.4 (SF check; offset adj X->Y for P, offset adj X->Z for S2), logic and/or features of ECB 132 such as snoop logic 135 can check a snoop filter (SF) table (e.g., snoop filter table 400) to determine which nodes may have the cache line associated with the mapped shared region corresponding to Addr X. According to some examples, snoop logic 135 arrives at a result that indicates an SF hit for Addr X at primary node 110-P that has an offset adjustment to Addr X to arrive at Addr Y and also an SF hit for Addr X at secondary node 120-S2 that has an offset adjustment to Addr X to arrive at Addr Z).
Regarding claim 13, Jayaraman in view of Nam in further view of Lee teaches The storage device of claim 10, wherein the first access request includes a first address corresponding to a storage area of the storage device, and wherein the first update information includes the first address (Jayaraman paragraph [0025], According to some examples, as shown in FIG. 1, primary node 110-P includes a memory 114-P. For these examples, a system address memory map 115-P can represent a map of host physical addresses (HPAs) of memory 114-P. Primary node 110-P, in some examples, can earmark a region of memory 114-P from system address memory map 115-P and include that earmarked region in shared region 117. A mapping table may be used to indicate and update memory address information regarding the storage device connected to the host).
Regarding claim 15, Jayaraman in view of Nam in further view of Lee teaches The storage device of claim 13, wherein the first access request is based on a CXL.mem protocol being a memory access protocol supporting a memory access, and wherein the first address is a memory physical address indicating an area of a system memory managed by the first host (Jayaraman paragraph [0025], According to some examples, as shown in FIG. 1, primary node 110-P includes a memory 114-P. For these examples, a system address memory map 115-P can represent a map of host physical addresses (HPAs) of memory 114-P. Primary node 110-P, in some examples, can earmark a region of memory 114-P from system address memory map 115-P and include that earmarked region in shared region 117. In some examples, shared region 117 can be shared with secondary nodes 120-S1, S2, S3 and mapped by these secondary systems in their respective system address memory maps 125-S1, S2, S3. System address memory maps 125-S1, S2, S3 can separately represent a map of HPAs of a respective memory 124-S1, S2, S3. Mapped shared memory for secondary node 120-S1, for example, is shown in FIG. 1 as shared map 127-S1. Shared maps 127-S1, S2, S3 can be mapped to regions of respective memories 124-S1, S2, S3 as a CXL.mem based HDM device coherent (HDM-D) as described by CXL 2.0 and/or CXL 3.0 or as a CXL.mem based HDM device coherent using back-invalidation (HDM-DB) as described by CXL 3.0 or subsequent CXL specifications. As described more below, logic and/or features of an ECB such as CXL translation logic 133 of ECB 132 can be arranged to use back invalidate flows to resolve coherency for shared maps 127-S1, S2, S3 of secondary nodes 120-S1, S2, S3 mapped using CXL.mem based HDM-DB. If shared maps 127-S1, S2, S3 are mapped using CXL.mem based HDM-D, shared maps 127-S1, S2, S3 can map to a non-cacheable region to avoid bias-flip. The access request may be a CXL.mem protocol using address information mapping via the host).
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jayaraman in view of Nam as applied to claim 2 above, and further in view of Guim Bernat et al. (US Publication No. 2023/0036751 – “Bernat”).
Regarding claim 3, Jayaraman in view of Nam in further view of Bernat teaches The method of claim 2, wherein the first access request is based on a CXL.io protocol being a PCI-e-based non-coherent input/output protocol, (Bernat paragraph [0043], A CXL link may be a low-latency, high-bandwidth discrete or on-package link that supports dynamic protocol multiplexing of coherency, memory access, and input/output (I/O) protocols. Among other applications, a CXL link may enable an accelerator to access system memory as a caching agent and/or host system memory, among other examples. CXL is a dynamic multi-protocol technology designed to support a vast spectrum of accelerators. CXL provides a rich set of sub-protocols that include I/O semantics similar to PCIe (CXL.io), caching protocol semantics (CXL.cache), and memory access semantics (CXL.mem) over a discrete or on-package link. A CXL.io protocol may be utilized as a PCIe input/output) and wherein the first address is a logical block address managed by a file system of the first host (Jayaraman paragraph [0026], According to some examples, for CXL.mem based HDM-DB mapped shared memory, logic and/or features of an ECB such as CX: translation logic 133 of ECB 132 can convert incoming master to subordinate (M2S) request messages received from secondary nodes 120-S1, S2 or S3 to device to host (D2H) request messages (e.g., RdShared/RdOwn requests) to be relayed to primary node 110-P. The logic and/or features of ECB 132 such as CXL translation logic 133 can complete an M2S/D2H transaction by returning/writing the latest data after resolution of coherency).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Jayaraman and Nam with those of Bernat. Bernat teaches using a CXL.io protocol through a PCIe based input/output, which enables dynamic protocol usage as well as more efficiently allowing memory coherency and use of advanced protocols (i.e., see Bernat paragraph [0043], A CXL link may be a low-latency, high-bandwidth discrete or on-package link that supports dynamic protocol multiplexing of coherency, memory access, and input/output (I/O) protocols. Among other applications, a CXL link may enable an accelerator to access system memory as a caching agent and/or host system memory, among other examples. CXL is a dynamic multi-protocol technology designed to support a vast spectrum of accelerators. CXL provides a rich set of sub-protocols that include I/O semantics similar to PCIe (CXL.io), caching protocol semantics (CXL.cache), and memory access semantics (CXL.mem) over a discrete or on-package link. Based on the particular accelerator usage model, all of the CXL protocols or only a subset of the protocols may be enabled. In some implementations, CXL may be built upon the well-established, widely adopted PCIe infrastructure (e.g., PCIe 5.0), leveraging the PCIe physical and electrical interface to provide advanced protocol in areas include I/O, memory protocol (e.g., allowing a host processor to share memory with an accelerator device), and coherency interface).
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jayaraman in view of Nam in further view of Lee as applied to claim 13 above, and further in view of Guim Bernat et al. (US Publication No. 2023/0036751 – “Bernat”).
Regarding claim 14, Jayaraman in view of Nam in further view of Lee and further in view of Bernat teaches The storage device of claim 13, wherein the first access request is based on a CXL.io being a PCI-e-based non-coherent input/output protocol, (Bernat paragraph [0043], A CXL link may be a low-latency, high-bandwidth discrete or on-package link that supports dynamic protocol multiplexing of coherency, memory access, and input/output (I/O) protocols. Among other applications, a CXL link may enable an accelerator to access system memory as a caching agent and/or host system memory, among other examples. CXL is a dynamic multi-protocol technology designed to support a vast spectrum of accelerators. CXL provides a rich set of sub-protocols that include I/O semantics similar to PCIe (CXL.io), caching protocol semantics (CXL.cache), and memory access semantics (CXL.mem) over a discrete or on-package link. A CXL.io protocol may be utilized as a PCIe input/output) and wherein the first address is a logical block address managed by a file system of the first host (Jayaraman paragraph [0026], According to some examples, for CXL.mem based HDM-DB mapped shared memory, logic and/or features of an ECB such as CX: translation logic 133 of ECB 132 can convert incoming master to subordinate (M2S) request messages received from secondary nodes 120-S1, S2 or S3 to device to host (D2H) request messages (e.g., RdShared/RdOwn requests) to be relayed to primary node 110-P. The logic and/or features of ECB 132 such as CXL translation logic 133 can complete an M2S/D2H transaction by returning/writing the latest data after resolution of coherency).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Jayaraman, Nam and Lee with those of Bernat. Bernat teaches using a CXL.io protocol through a PCIe based input/output, which enables dynamic protocol usage as well as more efficiently allowing memory coherency and use of advanced protocols (i.e., see Bernat paragraph [0043], A CXL link may be a low-latency, high-bandwidth discrete or on-package link that supports dynamic protocol multiplexing of coherency, memory access, and input/output (I/O) protocols. Among other applications, a CXL link may enable an accelerator to access system memory as a caching agent and/or host system memory, among other examples. CXL is a dynamic multi-protocol technology designed to support a vast spectrum of accelerators. CXL provides a rich set of sub-protocols that include I/O semantics similar to PCIe (CXL.io), caching protocol semantics (CXL.cache), and memory access semantics (CXL.mem) over a discrete or on-package link. Based on the particular accelerator usage model, all of the CXL protocols or only a subset of the protocols may be enabled. In some implementations, CXL may be built upon the well-established, widely adopted PCIe infrastructure (e.g., PCIe 5.0), leveraging the PCIe physical and electrical interface to provide advanced protocol in areas include I/O, memory protocol (e.g., allowing a host processor to share memory with an accelerator device), and coherency interface).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONAH C KRIEGER whose telephone number is (571)272-3627. The examiner can normally be reached Monday - Friday 8 AM - 5 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Rocio Del Mar Perez-Velez can be reached at (571)-270-5935. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/J.C.K./Examiner, Art Unit 2133
/ROCIO DEL MAR PEREZ-VELEZ/Supervisory Patent Examiner, Art Unit 2133
Prosecution Insights