Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lyu et al., NPL V (hereinafter referred to as Lyu).
In regards to claim 19, Lyu teaches a power switch comprising short circuit protection circuitry (Ultrafast Short-Circuit Protection Method; [Title]), the power switch comprising: a cascode (cascode; [Fig. 3]) operable to provide a load (I_D; [Fig. 3]) with pulsed power from a power source (V_plv; [Fig. 3]), the cascode having a first transistor (lower transistor; [Fig. 3]) connected in series (implicit; [Fig. 3]) at an intermediate node to a second transistor (upper transistor; [Fig. 3]); a gate driver (IN/OUT box within Desaturation Soft Turn-off; [Fig. 3]) that generates gate driver voltage pulses (PWM; [Fig. 3]) responsive to which a gate, of the first transistor is biased to turn the first transistor ON and OFF (implicit; [Fig. 3]) and provide pulsed power to the load (implicit; [Fig. 3]); and short circuit protection circuitry comprising: a comparator (comparator in Ultra-Fast Detection; [Fig. 3]) connected to the second transistor (implicit; [Fig. 3]) via a high pass filter (Cf and Rf1 in the Ultra-Fast Detection; [Fig. 3]) that receives voltage generated by current flowing through the second transistor (implicit; [Fig. 3]) and stray inductance of the second transistor and generates a comparator output signal (output of comparator; [Fig. 3]) that indicates (Examiner’s Note: The circuit indicates -V_EE when the voltage exceeds the threshold voltage.) when the received voltage filtered by the filter exceeds a threshold voltage (Vscthr; [Fig. 3]); and voltage pulse control circuitry (pulse generator in Active Gate Clamping; [Fig. 3]) that controls the driver voltage pulses responsive to the comparator output signal (implicit; [Fig. 3]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 12-13, and 15-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al., NPL U (hereinafter referred to as Kim) and in view of Chen et al., US20190140630 (hereinafter referred to as Chen).
In regards to claim 1, Kim teaches a short circuit protection circuitry (Short-Circuit Protection Circuits; [Title]) comprising: a HEMT (high electron mobility transistor) (GaN HEMT; [title]) comprising a source (lower mosfet S; [Fig. 11]), drain (lower mosfet D; [Fig. 11]), and gate (lower mosfet G; [Fig. 11]) controllable to be turned ON and OFF by voltage applied to the gate (implicit of voltage or lack of voltage on a gate); a comparator (comparator in Judging Circuit; [Fig. 11]) having an input (+input; [Fig. 11]) coupled (implicit; [Fig. 11]) to a high-pass filter (C1 and R1 in the Detection Circuit; [Fig. 11]) and an output (output of comparator in Judging Circuit; [Fig. 11]) at which the comparator generates an output signal (voltage on output of comparator; [Fig. 11]) responsive to a voltage (V_L_Stray1 or Vsense; [Pg. 4, Eq. (1)]) induced across an inductance (stray inductance; [Pg. 2, Para. 3]) if the voltage after filtering by the filter exhibits a voltage surge (instantaneous drop; [Pg. 12, Para. 2]) greater than a threshold voltage (Vth; [Fig. 11]) (Examiner’s Note: It is an engineering design choice to trigger on the voltage dip of the Vsense curve or increasing voltage. The design trade off would be reliability vs. detection speed.)
Kim does not teach a voltage divider controllable to be turned ON and turned OFF to control voltage provided to the gate of the HEMT, and wherein the voltage divider is turned ON responsive to the output signal from the comparator to provide the gate with a reduced voltage that is less than an ON-threshold voltage of the HEMT.
Chen teaches a voltage divider (Rgate & R1; [Fig. 1]) controllable to be turned ON and turned OFF (transistor Q1; [Fig. 1]) to control voltage provided to the gate of the HEMT (implicit; [Fig. 1]), and wherein the voltage divider is turned ON (turned on; [0044]) responsive to the output signal from the comparator (implicit; [Fig. 1]) to provide the gate with a reduced voltage (2V; [0021] & [0044]) that is less than an ON-threshold voltage (5V or gate threshold voltage; [0021] & [Fig. 3B]) of the HEMT.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Kim in order to incorporate a voltage divider controllable to be turned ON and turned OFF to control voltage provided to the gate of the HEMT, and wherein the voltage divider is turned ON responsive to the output signal from the comparator to provide the gate with a reduced voltage that is less than an ON-threshold voltage of the HEMT as taught by Chen. The motivation for doing so would be to improve upon the gate drive circuitry.
In regards to claim 12, Kim does not teach wherein the reduced voltage is less than an ON-threshold of the HEMT by a voltage difference that is equal to between 10% and 50% of an absolute value of the ON-threshold voltage.
Chen teaches wherein the reduced voltage (2V; [Fig. 3, Plot B]) is less than an ON-threshold (5V; [Fig. 3, Plot B]) of the HEMT by a voltage difference that is equal to between 10% and 50% (40%; [Fig. 3, Plot B]) of an absolute value of the ON-threshold voltage (Examiner’s Note: Plot B shows a max ON of 5V while the reduced voltage is 2V which is 40% of the max ON voltage.).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Kim in order to incorporate wherein the reduced voltage is less than an ON-threshold of the HEMT by a voltage difference that is equal to between 10% and 50% of an absolute value of the ON-threshold voltage as taught by Chen. The motivation for doing so would be to improve upon the gate drive circuitry.
In regards to claim 13, Kim teaches wherein voltage that biases the gate of the HEMT comprises voltage pulses (PWM; [Fig. 11]).
In regards to claim 15, INVENTOR teaches wherein the HEMT is an E-Mode HEMT (E-mode gallium nitride high-electron-mobility transistors; [Abstract]).
In regards to claim 16, Kim teaches wherein the HEMT is a first transistor (lower transistor; [Fig. 11]) comprised in a cascode (cascode to the left of the detection circuit; [Fig. 11]) and is connected in series with a second transistor (upper transistor; [Fig. 11]) of the cascode.
In regards to claim 17, Kim teaches wherein the inductance is a stray inductance (stray inductance; [Pg. 2, Para. 3]) of the second transistor (power semiconductor package; [Pg. 2, Para. 3]).
In regards to claim 18, Kim teaches a power switch (power conversion device; [Abstract]) comprising the short circuit protection circuitry according to claim 1.
Claim(s) 2-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al., NPL U (hereinafter referred to as Kim) in view of Chen et al., US20190140630 (hereinafter referred to as Chen) and in further view of Li et al., US20190379374 (hereinafter referred to as Li).
In regards to claim 2, Kim and Chen do not teach the short circuit protection circuitry comprising a buffer (amplifier 114; [Fig. 1]) that is connected to the voltage divider (implicit for adding the buffer directly to the gate, the voltage divider will be ahead of the buffer) and biases the gate to turn ON and turn OFF the HEMT with voltage responsive to voltage that the buffer receives from the voltage divider (implicit for adding the buffer directly to the gate, the voltage divider will be ahead of the buffer).
Li teaches the short circuit protection circuitry comprising a buffer that is connected to the voltage divider and biases the gate to turn ON and turn OFF the HEMT with voltage responsive to voltage that the buffer receives from the voltage divider.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Kim and Chen in order to incorporate the short circuit protection circuitry comprising a buffer that is connected to the voltage divider and biases the gate to turn ON and turn OFF the HEMT with voltage responsive to voltage that the buffer receives from the voltage divider as taught by Li. The motivation for doing so would be to improve the signal strength at the gate of the power transistor.
In regards to claim 3, Kim does not teach wherein the voltage divider is connected in series with a gate driver to receive voltage from the gate driver and generate responsive thereto the voltage received by the buffer.
Chen teaches wherein the voltage divider is connected in series (implicit; [Fig. 1]) with a gate driver (amplifier 212 in gate driver 210; [Fig. 1]) to receive voltage from the gate driver and generate responsive thereto the voltage received by the buffer (implicit; [Fig. 1]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Kim in order to incorporate wherein the voltage divider is connected in series with a gate driver to receive voltage from the gate driver and generate responsive thereto the voltage received by the buffer. The motivation for doing so would be to improve upon the gate drive circuitry.
In regards to claim 4, Kim does not teach the short circuit protection circuitry comprising an enabling circuit that generates enable and disable signals to respectively enable and disable the gate driver and disables the gate driver responsive to the comparator output signal.
Chen teaches the short circuit protection circuitry comprising an enabling circuit (AND gate 216; [Fig. 1]) that generates enable (gate drive signal input IN; [0033]) and disable signals (output signal; [Fig. 1])to respectively enable and disable the gate driver and disables the gate driver responsive to the comparator output signal (implicit; [Fig. 1]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Kim in order to incorporate the short circuit protection circuitry comprising an enabling circuit that generates enable and disable signals to respectively enable and disable the gate driver and disables the gate driver responsive to the comparator output signal as taught by Chen. The motivation for doing so would be to improve upon the gate drive circuitry.
In regards to claim 5, Kim teaches the short circuit protection circuitry comprising a latch (latch circuit; [Fig. 11]) that receives and generates at least one output signal responsive to the comparator output signal (implicit; [Fig. 11]).
In regards to claim 6, Kim does not teach wherein the voltage divider is connected to the latch and receives a signal of the at least one signal that turns ON the voltage divider
Chen teaches wherein the voltage divider is connected to the latch (implicit; [Fig. 1]) and receives a signal (Q of latch 222 signal; [Fig. 1]) of the at least one signal that turns ON the voltage divider.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Kim in order to incorporate wherein the voltage divider is connected to the latch and receives a signal of the at least one signal that turns ON the voltage divider as taught by Chen. The motivation for doing so would be to improve upon the gate drive circuitry.
In regards to claim 7, Kim does not teach wherein the voltage divider comprises a transistor which the signal from the latch turns ON to connect the voltage divider to a ground and thereby to turn ON the voltage divider.
Chen teaches wherein the voltage divider comprises a transistor (transistor Q1; [Fig. 1]) which the signal from the latch turns ON to connect the voltage divider to a ground (implicit; [Fig. 1]) and thereby to turn ON the voltage divider (implicit; [Fig. 1]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Kim in order to incorporate wherein the voltage divider comprises a transistor which the signal from the latch turns ON to connect the voltage divider to a ground and thereby to turn ON the voltage divider as taught by Chen. The motivation for doing so would be to improve upon the gate drive circuitry.
In regards to claim 8, Kim does not teach wherein the enabling circuit is connected to the latch and receives a signal of the at least one signal from the latch causes the enabling circuit to generate a disable signal that disables the gate driver.
Chen teaches wherein the enabling circuit (AND gate 216; [Fig. 1]) is connected to the latch (implicit; [Fig. 1]) and receives a signal (fault signal FLT; [0034] & [Fig. 1]) of the at least one signal from the latch causes the enabling circuit to generate a disable signal (fully turn-off; [0034]) that disables the gate driver.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Kim in order to incorporate wherein the enabling circuit is connected to the latch and receives a signal of the at least one signal from the latch causes the enabling circuit to generate a disable signal that disables the gate driver as taught by Chen. The motivation for doing so would be to improve upon the gate drive circuitry.
In regards to claim 9, Kim does not teach wherein the disable signal disables the gate driver at a second time delayed from a first time at which the voltage divider is turned ON.
Chen teaches wherein the disable signal disables the gate driver at a second time (second stage turn-off; [0034]) delayed from a first time (first stage turn-off; [0034]) at which the voltage divider is turned ON.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Kim in order to incorporate wherein the disable signal disables the gate driver at a second time delayed from a first time at which the voltage divider is turned ON as taught by Chen. The motivation for doing so would be to improve upon the gate drive circuitry.
In regards to claim 10, Kim does not teach wherein the first time is delayed by between 25 ns -50 ns (nanoseconds) from a time at which the voltage surge exceeds the comparator threshold voltage.
Chen teaches wherein the first time is delayed by between 25 ns -50 ns (nanoseconds) (tens of nanoseconds; [0034]) from a time at which the voltage surge exceeds the comparator threshold voltage.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Kim in order to incorporate wherein the first time is delayed by between 25 ns -50 ns (nanoseconds) from a time at which the voltage surge exceeds the comparator threshold voltage as taught by Chen. 25ns-50ns is within the range of tens of nanoseconds which would be 10-90ns. The motivation for doing so would be to improve upon the gate drive circuitry.
In regards to claim 11, Kim does not teach wherein the second time is delayed from the first time by between 200 ns and 400 ns.
Chen teaches wherein the second time is delayed from the first time by between 200 ns and 400 ns (~500ns; [0034] & [Fig. 4]).
Chen discloses the claimed invention except for the second time is delayed by between 200ns and 400ns. It would have been obvious to one of ordinary skill in the art at the time the invention was made to set the delay time between 200ns and 400ns, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al., NPL U (hereinafter referred to as Kim) in view of Chen et al., US20190140630 (hereinafter referred to as Chen) and in further view of Chandrasekar et al., US20250389595 (hereinafter referred to as Chandrasekar).
In regards to claim 14, Kim and Chen do not teach wherein the HEMT is a D-mode HEMT.
Chandrasekar teaches wherein the HEMT is a D-mode HEMT (D-Mode; [0019]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Kim and Chen in order to incorporate wherein the HEMT is a D-mode HEMT as taught by Chandrasekar. The motivation for doing so would be an engineering design choice to use a normally ON or OFF transistor.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Chen, US11909384, is a relevant art for the cascode configuration of an HEMT.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMANTHA L FAUBERT whose telephone number is (703)756-1311. The examiner can normally be reached Monday - Friday 8AM - 5PM.
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SAMANTHA LYNETTE FAUBERT
Examiner
Art Unit 2836
/CRYSTAL L HAMMOND/ Supervisory Primary Examiner, Art Unit 2838