Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 10 and 11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Takahashi (20120242418).
Regarding claim 10, Takahashi (Figs. 10 and 12) discloses a circuit comprising: an amplifier circuit (Q1, Q2) including a first node (X1) to which a first input signal (X1) is input and a second node via its collector, as an output node; and generating an amplified signal having peaking characteristics according to the first input signal in the output node; an adjustment circuit (SC1/SC2) including a third node (a node, which is not grounded), and see Figure 12, a first series circuit connected between the third node and a ground wiring and having a first capacitor (Ca1-Ca(n)) and transistor(s) (MN1-MN9n)) operable as a first variable resistance element connected in series with each other; and a follower circuit (Q3, Q4) including a fourth node via emitter terminal, as an output node, and a first source follower circuit (Q3) connected between the third node and the fourth node, wherein the first variable resistance element has a first resistance value that changes according to a first setting signal (Ccont1-Ccont(n)).
Regarding claim 11, Takahashi (Figs. 10 and 12) discloses a circuit comprising: an amplifier circuit (Q1, Q2) including a first node (X1) to which a first input signal (X1) is input, a fifth node (X2) to which a second input signal (X2) is input, and a second node and a sixth node as output nodes, via its respective collector terminal, and generating an amplified signal having peaking characteristics according to the first input signal and the second input signal in the output node; an adjustment circuit (SC1/SC2) including a third node and a seventh node as output nodes (a node, which is not grounded), and see Figure 12, a first series circuit connected between the third node and a ground wiring and having a first capacitor (Ca1) and a first variable resistance element (MN1) connected in series with each other, and a second series circuit connected between the seventh node and the ground wiring and having a second capacitor (Ca2) and a second variable resistance element (MN2) connected in series with each other; and a follower circuit including a fourth node and an eighth node as output nodes, a first source follower circuit (Q3) connected between the third node and the fourth node, and a second source follower circuit (Q4) connected between the seventh node and the eighth node, wherein the first variable resistance element has a first resistance value that changes according to a first setting signal (Ccont1), and the second variable resistance element has a second resistance value that changes according to a second setting signal (Ccont2).
Allowable Subject Matter
Claims 1-9 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding claims 1-9, prior art(s) does not disclose an adjustment circuit including a third node as an output node, a first inductor connected between the second node and the third node, and a first series circuit connected between the third node and a ground wiring and having a first capacitor and a first variable resistance element connected in series with each other.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior arts made of record and not relied upon is considered pertinent to applicant's disclosure.
Takaso (20100102884), which is considered to be the closest prior art to the claimed invention. Takaso (Fig. 2) discloses a circuit comprising an amplifier (DA1) and a follower circuit (EF1) coupled to the output of the amplifier (DA1). However, Takaso does not disclose details of an adjustment circuit as claimed, including an inductor and a series connected capacitor and variable resistance element.
Miyashita et al. (5,652,545) also does not disclose details of an adjustment circuit as claimed, including an inductor and a series connected capacitor and variable resistance element.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Khanh V. Nguyen whose telephone number is (571) 272-1767. The examiner can normally be reached from 8:30 AM – 5:00 PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JESSICA HAN can be reached on (571) 272-2078. The fax phone numbers for the organization where this application or proceeding is assigned is 571-273-8300.
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/KHANH V NGUYEN/ Primary Examiner, Art Unit 2843
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