DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is responsive to RCE filed on 04/09/2026. Claims 2, 4-8, 10, 12-16, 18, and 20 were canceled. Claims 1, 3, 9, 11, 17, 19, and 21-23 have been examined and are pending in this application.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 04/09/2026 has been entered.
Response to Arguments
Applicant’s arguments (see remarks of 03/09/2026) with respect to claims 1, 3, 9, 11, 17, 19, and 21-23 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
A new reference Welch et al. US 2023/0367511 is cited in this Office Action necessitated by the amendment.
In view of the new reference, independent claims 1, 9, and 17 are not in a condition for allowance. Claims depending therefrom, either directly or indirectly, are also not in a condition for allowance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 9, 11, 17, 19, and 21-23 are rejected under 35 U.S.C. 103 as being unpatentable over Kale US 2021/0173577 (“Kale”) in view of Welch et al. US 2023/0367511 (“Welch”).
As per independent claim 1, Kale teaches A memory system (“a memory sub-system 110” para 0014 and FIG. 1), comprising:
a non-volatile memory (“memory sub-system 110 can be a storage device, … Examples of a storage device include a solid-state drive (SSD),” para 0015 and FIG. 1) that comprises a plurality of logical areas (“memory sub-system can be segmented into two or more partitions.” Para 0010);
a controller (“The memory sub-system controller 115 (or controller 115 for simplicity)” para 0024 and FIG. 1) configured to:
control access to each logical area of the plurality of logical areas (“the memory sub-system controller 115 can receive commands or operations from the host system 120 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory devices 130.” Para 0027), wherein each of the plurality of logical areas is associated with a respective purpose (“one partition, such as partition 1, can be used to store video data, and another partition, such as partition 2, can be used to store analytic data.” Para 0039) and a respective command priority (“a priority parameter can indicate that partition 2 has a higher priority than partition 1. Writes to partition 2 are to be performed before any writes to partition 1.” Para 0044),
receive, from a host system, one or more commands, each command of the one or more commands designating a respective logical area of the plurality of logical areas (“a user can select one or more parameters that are indicative of a request to segment the memory device 210 in multiple partitions for use by the host system 120.” Para 0040. “to receive the one or more parameters indicative of the request to segment the memory device into multiple partitions for use by the host system, processing logic receives an indication of a memory size parameter of the first partition.” Para 0064 and FIG. 3),
maintain an execution an execution queue in which the one or more commands are stored in an execution order (“if partition 2 (P2) has a higher priority than partition 1 (P1), for a memory operation, such as a write operation, partition manager 113B can write all the data in the queue 212 destined to partition 2 before any of the data destined to partition 1 is written.” Para 0045),
determine, for each command of the one or more commands, an execution order position within the execution queue based on the command priority associated with the respective logical area designated by the command (“if partition 2 (P2) has a higher priority than partition 1 (P1), for a memory operation, such as a write operation, partition manager 113B can write all the data in the queue 212 destined to partition 2 before any of the data destined to partition 1 is written.” Para 0045),
execute the one or more commands stored in the execution queue sequentially according to the updated execution order (“if partition 2 (P2) has a higher priority than partition 1 (P1), for a memory operation, such as a write operation, partition manager 113B can write all the data in the queue 212 destined to partition 2 before any of the data destined to partition 1 is written.” Para 0045).
Kale discloses all of the claim limitations from above, but does not explicitly teach “upon receiving a new command from the host system while one or more previously received commands remain stored in the execution queue, insert the new command into the execution queue at a position immediately after a last queued command having a same command priority as the command priority associated with the logical area designated by the new command to update the execution order of the one or more previously received commands stored in the execution queue”.
However, in an analogous art in the same field of endeavor, Welch teaches upon receiving a new command from the host system while one or more previously received commands remain stored in the execution queue, insert the new command into the execution queue at a position immediately after a last queued command having a same command priority as the command priority associated with the logical area designated by the new command to update the execution order of the one or more previously received commands stored in the execution queue (“requests 124 of a highest priority may be added to the top of the queue 122 (or at a position near the top of the queue, behind earlier received requests 124 of the highest priority).” Para 0038).
Given the teaching of Welch, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Kale with “upon receiving a new command from the host system while one or more previously received commands remain stored in the execution queue, insert the new command into the execution queue at a position immediately after a last queued command having a same command priority as the command priority associated with the logical area designated by the new command to update the execution order of the one or more previously received commands stored in the execution queue”. The motivation would be that the invention allows lower priority requests to be addressed in a timely manner, para 0038 of Welch, which improves efficiency.
As per dependent claim 3, Kale in combination with Welch discloses the system of claim 1. Kale teaches wherein the controller is further configured to set the command priority, when dividing the non-volatile memory into the plurality of logical areas (“the partitioning of memory sub-system 110 can be based on one or more parameters, such as … a priority parameter.” Para 0032).
As per claims 9 and 11, these claims are respectively rejected based on arguments provided above for similar rejected claims 1 and 3.
As per claims 17 and 19, these claims are respectively rejected based on arguments provided above for similar rejected claims 1 and 3. Kale discloses processor and memory where the processor may execute instructions stored in the memory.
As per dependent claim 21, Kale in combination with Welch discloses the system of claim 1. Kale teaches wherein the controller is further configured to set the purpose for each logical area, when dividing the non-volatile memory into the plurality of logical areas (“the partitioning of memory sub-system 110 can be based on one or more parameters, such as a memory size parameter, a data retention parameter, an endurance parameter, or a priority parameter.” Para 0032).
As per dependent claims 22-23, these claims are rejected based on arguments provided above for similar rejected dependent claim 21.
Conclusion
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/ZUBAIR AHMED/Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132
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