DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
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Status of claim(s) to be treated in this office action:
Independent: 1, 10 and 17.
Pending: 1-20.
Information Disclosure Statement
Applicant’s IDS(s) submitted on 7/3/2024 is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has/have considered by the examiner and made of record.
Specification
The disclosure is objected to because of the following informalities:
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: SEMICONDUCTOR PACKAGE WITH NON-UNIFORM PROTECTIVE LAYERS AND CONDUCTIVE PADS.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3-9 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Suk et al., US Patent 10522471 B2.
Re: Independent Claim 1, Suk discloses a plurality of semiconductor chips (100, fig. 10b) that are sequentially stacked,
wherein respective ones of the semiconductor chips (100, fig. 10b) comprise:
a substrate (350, fig. 10b) that has a front surface (surface facing chip 100, fig. 10b) and a rear surface (surface facing solder bump 400, fig. 10b);
an interlayer dielectric layer (510, fig. 10b) on the front surface (surface facing chip 100, fig. 10b) of the substrate (350, fig. 10b);
a lower protection layer (310, fig. 10b) on a bottom surface of the interlayer dielectric layer (510, fig. 10b);
a plurality of lower conductive pads (110 and 521, fig. 10b) in the lower protection layer (310, fig. 10b);
an upper protection layer (340, fig. 10b) on the rear surface (surface facing solder bump 400, fig. 10b) of the substrate (350, fig. 10b); and
a plurality of upper conductive pads (330, fig. 10b) in the upper protection layer (340, fig. 10b),
wherein the upper conductive pads (330, fig. 10b) of a first one of the respective ones of the semiconductor chips (100, fig. 10b) are respectively in contact with the lower conductive pads (110 and 521, fig. 10b) of an adjacent one of the respective ones of the semiconductor chips (100, fig. 10b),
wherein each of the upper protection layer (340, fig. 10b) and the lower protection layer (310, fig. 10b) has a non-uniform thickness (as shown in figure 10b the protection layer 340 and 310 has different thickness), and
Suk is silent regarding: wherein ones of the lower conductive pads (110 and 521, fig. 10b) have respective thicknesses that are different from each other.
However, thickness range it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention because, absent evidence of disclosure of criticality for the range giving unexpected results, it is not inventive to discover optimal or workable ranges by routine experimentation. In re Aller, 220 F.2d 454, 105 USPQ 223, 235 (CCPA 1955). Furthermore, the specification contains no disclosure of either the critical nature of the claimed dimensions of any unexpected results arising therefrom. Where patentability is aid to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. See In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2sd 1934, 1936 (Fed. Cir. 1990). It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the system of Suk et al., as modified above to include thickness conductive pads have respective thicknesses that are different from each other since such modification to make those layer to have different thickness of conductive pad can use for improving chip to chip bonding, with different pad heights can compensate for variations in dielectric thickness warpage.
Re: Claim 3, Suk discloses all the limitations of claim 1 on which this claim depends. Suk further discloses: wherein the respective ones of the semiconductor chips (100, fig. 10b) further comprise a through via (523, fig. 10b).
Re: Claim 4, Suk discloses all the limitations of claim 3 on which this claim depends. Suk further discloses: wherein a respective one of the upper conductive pads (330, fig. 10b) is in contact with the through via (523, fig. 10b; electrical contact with conductive pads 330).
Re: Claim 5, Suk discloses all the limitations of claim 1 on which this claim depends. Suk further discloses: wherein a bottom surface of the upper protection layer (340, fig. 10b) of the first one of the respective ones of the semiconductor chips (100, fig. 10b) is curved (as shown in figure 13b protection layer 310/340 bent up or bent down), wherein a top surface of the lower protection layer (310, fig. 10b) of the adjacent one of the respective ones of the semiconductor chips (100, fig. 10b) is curved (as shown in figure 13b protection layer 310/340 bent up or bent down), and wherein an interface between the upper protection layer (340, fig. 10b) of the first one of the respective ones of the semiconductor chips (100, fig. 10b) and the lower protection layer (310, fig. 10b) of the adjacent one of the respective ones of the semiconductor chips (100, fig. 10b) is flat.
Re: Claim 6, Suk discloses all the limitations of claim 1 on which this claim depends. Suk is silent regarding: wherein the non-uniform thickness of each of the upper protection layer (340, fig. 10b) and the lower protection layer (310, fig. 10b) is in a range of about 100 angstroms (Å) to about 5,000 Å.
However, thickness range it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention because, absent evidence of disclosure of criticality for the range giving unexpected results, it is not inventive to discover optimal or workable ranges by routine experimentation. In re Aller, 220 F.2d 454, 105 USPQ 223, 235 (CCPA 1955). Furthermore, the specification contains no disclosure of either the critical nature of the claimed dimensions of any unexpected results arising therefrom. Where patentability is aid to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. See In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2sd 1934, 1936 (Fed. Cir. 1990). It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the system of Suk et al., as modified above to include thickness of each of the protection layer is in a range of about 100 angstroms (Å) to about 5,000 Å since such modification to make those layer to have a thinner thickness to achieve the predictable result of miniaturization the display device thereby improve the high-density integration.
Re: Claim 7, Suk discloses all the limitations of claim 1 on which this claim depends. Suk further discloses: wherein the upper conductive pads (330, fig. 10b) include a same material as the lower conductive pads (110 and 521, fig. 10b).
Re: Claim 8, Suk discloses all the limitations of claim 1 on which this claim depends. Suk further discloses: wherein each of the upper protection layer (340, fig. 10b) and the lower protection layer (310, fig. 10b) includes silicon oxide or silicon carbonitride (column 6, lines 58-61).
Re: Claim 9, Suk discloses all the limitations of claim 1 on which this claim depends. Suk further discloses: wherein a minimum thickness of the upper protection layer (340, fig. 10b) is in a range of about 0.1 times to about 0.9 times (column 12, lines 7-24) a maximum thickness of the upper protection layer (340, fig. 10b), and wherein a minimum thickness of the lower protection layer (310, fig. 10b) is in a range of about 0.1 times to about 0.9 times (column 12, lines 7-24) a maximum thickness of the lower protection layer (310, fig. 10b).
Claim(s) 2 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Suk et al., US Patent 10522471 B2;in view of Heo et al., US PG pub. 20210091045 A1.
Re: Claim 2, Suk discloses all the limitations of claim 1 on which this claim depends. Suk is silent regarding: wherein the plurality of semiconductor chips (100, fig. 10b) include first, second, third, fourth, and fifth semiconductor chips (100, fig. 10b), and wherein a first width of the first semiconductor chip (720, fig. 10b) is greater than a second width of each of the second, third, fourth, and fifth semiconductor chips (100, fig. 10b).
Heo teaches in figure 1B, the plurality of semiconductor chips (100 and 200) include first, second, third, fourth, and fifth semiconductor chips and wherein a first width of the first semiconductor chip (100) is greater than a second width of each of the second, third, fourth, and fifth semiconductor chips (200).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include multiple chip stack on top of each other since this can improve high-density of integration of chips stack and with the bottom chip wider than the top chip this can provide the stack structure to have a sturdy structure.
Claim(s) 17-20 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Suk et al., US Patent 10522471 B2; in view of Sohn et al., US PG pub. 20220107890 A1.
Re: Independent Claim 17, Suk discloses wherein respective ones of the semiconductor chips (100, fig. 10b) comprise:
a substrate (350, fig. 10b) that has a front surface (surface facing chip 100, fig. 10b) and a rear surface (surface facing solder bump 400, fig. 10b);
an interlayer dielectric layer (510, fig. 10b) on the front surface (surface facing chip 100, fig. 10b) of the substrate (350, fig. 10b);
a lower protection layer (310, fig. 10b) on a bottom surface of the interlayer dielectric layer (510, fig. 10b);
a plurality of lower conductive pads (110 and 521, fig. 10b) in the lower protection layer (310, fig. 10b);
an upper protection layer (340, fig. 10b) on the rear surface (surface facing solder bump 400, fig. 10b) of the substrate (350, fig. 10b); and
a plurality of upper conductive pads (330, fig. 10b) in the upper protection layer (340, fig. 10b),
wherein the upper conductive pads (330, fig. 10b) of a first one of the respective ones of the semiconductor chips (100, fig. 10b) are respectively in contact with the lower conductive pads (110 and 521, fig. 10b) of an adjacent one of the respective ones of the semiconductor chips (100, fig. 10b),
wherein each of the upper protection layer (340, fig. 10b) and the lower protection layer (310, fig. 10b) has a non-uniform thicknesses (as shown in figure 10b the protection layer 340 and 310 has different thickness).
Suk is silent regarding: a package substrate (3n50, fig. 10b); an interposer substrate (350, fig. 10b) on the package substrate (350, fig. 10b); a plurality of first chip structures on the interposer substrate (350, fig. 10b); and a second chip structure on the interposer substrate (350, fig. 10b), wherein each of the plurality of first chip structures includes a plurality of semiconductor chips (100, fig. 10b) that are sequentially stacked, wherein the non-uniform thickness of each of the upper protection layer (340, fig. 10b) and the lower protection layer (310, fig. 10b) is in a range of about 100 angstroms (Å) to about 5,000 Å.
Sohn teaches in figure 3A, a multiple chip stacking structure wherein a package substrate (310) an interposer substrate (320) on the package substrate (310) a plurality of first chip structures (SID1) on the interposer substrate (320) and a second chip structure (MD2) on the interposer substrate (320) wherein each of the plurality of first chip structures (SID1) includes a plurality of semiconductor chips (MD1,MD3, MD7) that are sequentially stacked.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include multiple stack chip on to a single package substrate since can improve high-density of integration of chips stack with miniaturization.
Suk and Sohn did not teach the wherein the non-uniform thickness of each of the upper protection layer (340, fig. 10b) and the lower protection layer (310, fig. 10b) is in a range of about 100 angstroms (Å) to about 5,000 Å.
However, thickness range it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention because, absent evidence of disclosure of criticality for the range giving unexpected results, it is not inventive to discover optimal or workable ranges by routine experimentation. In re Aller, 220 F.2d 454, 105 USPQ 223, 235 (CCPA 1955). Furthermore, the specification contains no disclosure of either the critical nature of the claimed dimensions of any unexpected results arising therefrom. Where patentability is aid to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. See In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2sd 1934, 1936 (Fed. Cir. 1990). It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the system of Suk et al., as modified above to include thickness of each of the protection layer is in a range of about 100 angstroms (Å) to about 5,000 Å since such modification to make those layer to have a thinner thickness to achieve the predictable result of miniaturization the display device thereby improve the high-density integration.
Re: Claim 18, Suk and Sohn discloses all the limitations of claim 17 on which this claim depends. Suk further discloses: wherein a bottom surface of the upper protection layer (340, fig. 10b) of the first one of the respective ones of the semiconductor chips (100, fig. 10b) and a top surface of the lower protection layer (310, fig. 10b) of the adjacent one of the respective ones of the semiconductor chips (100, fig. 10b) are both curved (as shown in figure 13b protection layer 310/340 bent up or bent down), and wherein an interface between the upper protection layer (340, fig. 10b) of the first one of the respective ones of the semiconductor chips (100, fig. 10b) and the lower protection layer (310, fig. 10b) of the adjacent one of the respective ones of the semiconductor chips (100, fig. 10b) is flat.
Re: Claim 19, Suk and Sohn discloses all the limitations of claim 17 on which this claim depends. Suk is silent regarding: wherein ones of the lower conductive pads (110 and 521, fig. 10b) have respective thicknesses that are different from each other.
However, thickness range it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention because, absent evidence of disclosure of criticality for the range giving unexpected results, it is not inventive to discover optimal or workable ranges by routine experimentation. In re Aller, 220 F.2d 454, 105 USPQ 223, 235 (CCPA 1955). Furthermore, the specification contains no disclosure of either the critical nature of the claimed dimensions of any unexpected results arising therefrom. Where patentability is aid to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. See In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2sd 1934, 1936 (Fed. Cir. 1990). It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the system of Suk et al., as modified above to include thickness conductive pads have respective thicknesses that are different from each other since such modification to make those layer to have a thinner thickness to achieve the predictable result of miniaturization the display device thereby improve the high-density integration.
Re: Claim 20, Suk and Sohn discloses all the limitations of claim 17 on which this claim depends. Suk further discloses: wherein a minimum thickness of the upper protection layer (340, fig. 10b) is in a range of about 0.1 times to about 0.9 times (column 12, lines 7-24) a maximum thickness of the upper protection layer (340, fig. 10b), and wherein a minimum thickness of the lower protection layer (310, fig. 10b) is in a range of about 0.1 times to about 0.9 times (column 12, lines 7-24) a maximum thickness of the lower protection layer (310, fig. 10b).
Prior art made of record and not relied upon are considered pertinent to current application disclosure.
* (“Lee US Patent 10256215 B2”) Discloses a semiconductor package includes a first semiconductor chip including a through silicon via in the first semiconductor chip and a first trench portion in an upper portion of the first semiconductor chip, a second semiconductor chip on an upper surface of the first semiconductor chip and being electrically connected to the first semiconductor chip through the through silicon via of the first semiconductor chip, and an insulating bonding layer between the first semiconductor chip and the second semiconductor chip. The insulating bonding layer fills the first trench portion.
* (“Huang US Patent 11328989 B2”) discloses a wiring structure and a method for manufacturing the same are provided. The wiring structure includes an upper conductive structure, a lower conductive structure and a redistribution structure. The upper conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The lower conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The redistribution structure is disposed between the upper conductive structure and the lower conductive structure to electrically connect the upper conductive structure and the lower conductive structure. The redistribution structure includes a dielectric structure and a redistribution layer embedded in the dielectric structure. The redistribution layer includes at least one circuit layer. A line width of the circuit layer of the redistribution layer is less than a line width of the circuit layer of the upper conductive structure and a line width of the circuit layer of the lower conductive structure.
* (“Daubenspeck et al., US PG pub. 20140239457 A1”) discloses a three dimensional integrated circuit (3D-IC) structure, method of manufacturing the same and design structure thereof are provided. The 3D-IC structure includes two chips having a dielectric layer, through substrate vias (TSVs) and pads formed on the dielectric layer. The dielectric layer is formed on a bottom surface of each chip. Pads are electrically connected to the corresponding TSVs. The chips are disposed vertically adjacent to each other. The bottom surface of a second chip faces the bottom surface of a first chip. The pads of the first chip are electrically connected to the pads of the second chip through a plurality of conductive bumps. The 3D-IC structure further includes a thermal via structure vertically disposed between the first chip and the second chip and laterally disposed between the corresponding conductive bumps. The thermal via structure has an upper portion and a lower portion.
Allowable Subject Matter
Claims 10-16 are allowed.
Re: Independent Claim 10 (and its dependent claim(s) 11-16), the prior art of record do not disclose or suggest, in combination with all other limitations in the claim: a first semiconductor chip; and second to fifth semiconductor chips that are sequentially stacked on the first semiconductor chip, wherein respective ones of the second to fifth semiconductor chips comprise: a second substrate that has a second front surface and a second rear surface opposite to each other; a second interlayer dielectric layer on the second front surface of the second substrate; a plurality of second lower protection layers that are stacked below the second interlayer dielectric layer; a plurality of second lower conductive pads in a lowermost one of the second lower protection layers; a plurality of second upper protection layers that are stacked on the second rear surface of the second substrate; and a plurality of second upper conductive pads in an uppermost one of the second upper protection layers, wherein the second upper conductive pads of a first one of the respective ones of the second to fifth semiconductor chips are respectively in contact with the second lower conductive pads of an adjacent one of the respective ones of the second to fifth semiconductor chips, wherein the second upper conductive pads include a same material as the second lower conductive pads, wherein the uppermost one of the second upper protection layers has a non-uniform thickness, wherein the lowermost one of the second lower protection layers has a non-uniform thickness, wherein a first interface between the uppermost one of the second upper protection layers and an underlying one of the second upper protection layers is curved, and wherein a second interface between the lowermost one of the second lower protection layers and an overlying one of the second lower protection layers is curved.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TSZ CHIU whose telephone number is 571-272-8656. The examiner can normally be reached on M-F, 9:00AM to 5:00PM (EST).
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/TSZ K CHIU/Examiner, Art Unit 2898 Tsz.Chiu@uspto.gov
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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