Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-7, 14-18, 43 are rejected under 35 U.S.C. 103 as being unpatentable over US 20230419159 A1-HEO et al (Hereinafter referred to as “HEO”), in view of HASTINGS, et al., "Dynamically Generated Logical Qubits", arXiv:2107.02194v2, October 12, 2021, 19 pages)
Regarding claim 1, HEO discloses a method of modifying a quantum error correction code for a quantum computing system (Fig 2-3), the method comprising, by operation of one or more classical computing systems:
obtaining target values of logical errors associated with logical qubits of the quantum computing system ([0067], target);
obtaining observed values of the logical errors associated with applying the operations on the logical qubits ([0060], physical error rate);
HEO fails to disclose updating the quantum error correction code based on the target values and the observed values of the logical errors, wherein updating the quantum error correction code comprises modifying a quantum error correction pattern for one or more of the logical qubits; and causing the quantum computing system to apply the quantum error correction code while executing a quantum computing routine, wherein the quantum error correction code is applied using the modified quantum error correction pattern for the one or more of the logical qubits.
However, in the same field of endeavor, Hastings discloses a method of modifying a quantum error correction code for a quantum computing system (abstract), the method comprising, by operation of one or more classical computing systems (section 2.2); obtaining target values of logical errors associated with logical qubits of the quantum computing system (page 1, 2nd paragraph); updating the quantum error correction code based on the target values and the observed values of the logical errors, wherein updating the quantum error correction code comprises modifying a quantum error correction pattern for one or more of the logical qubits (section 1.3, 1.4, 3.1, 2.2); and causing the quantum computing system to apply the quantum error correction code while executing a quantum computing routine, wherein the quantum error correction code is applied using the modified quantum error correction pattern for the one or more of the logical qubits (section 2.2, 5th paragraph).
Therefore, it would have been obvious to one of ordinary skilled in the art before the effective filing date of the claimed invention to disclose a method disclosed by HEO to disclose updating the quantum error correction code based on the target values and the observed values of the logical errors, wherein updating the quantum error correction code comprises modifying a quantum error correction pattern for one or more of the logical qubits; and causing the quantum computing system to apply the quantum error correction code while executing a quantum computing routine, wherein the quantum error correction code is applied using the modified quantum error correction pattern for the one or more of the logical qubits as taught by Hastings, to provide a simplified error model (3.2, Hastings).
Regarding claim 2, HEO discloses the method of claim 1, wherein modifying the quantum error correction pattern for the one or more of the logical qubits comprises modifying a relative weight of stabilizer measurements for the one or more of the logical qubits ([0035]).
Regarding claim 3, Hastings discloses the method of claim 2, wherein updating the quantum error correction code comprises performing an iterative process over an initial relative weight of stabilizer measurements for the one or more of the logical qubits based on the target values and the observed values of the logical errors, and the modified relative weight of stabilizer measurements is determined by the iterative process (Section 1.4).
Regarding claim 4, Hastings discloses the method of claim 1, wherein updating the quantum error correction code comprises modifying a code distance of one or more of the logical qubits or modifying a code distance of one or more of the operations on the logical qubits based on the target values and the observed values of the logical errors ([0026]).
Regarding claim 5, Hastings discloses the method of claim 1, wherein updating the quantum error correction code comprises modifying the relative dimensions of one or more of the logical qubits based on the target values and the observed values of the logical errors ([0036]).
Regarding claim 7, HEO discloses the method of claim 1, wherein the quantum error correction code comprises a plurality of planar code patches, the plurality of planar code patches comprises X-type stabilizer patches and Z-type stabilizer patches, and modifying the quantum error correction pattern comprises determining an updated value of a weight of the X-type stabilizer patches relative to the Z-type stabilizer patches ([0033]).
Regarding claim 14, analyses are analogous to those presented for claim 1 and are applicable for claim 14.
Regarding claim 15, analyses are analogous to those presented for claim 2 and are applicable for claim 15.
Regarding claim 16, analyses are analogous to those presented for claim 4 and are applicable for claim 16.
Regarding claim 17, analyses are analogous to those presented for claim 3 and are applicable for claim 17.
Regarding claim 18, analyses are analogous to those presented for claim 4 and are applicable for claim 18.
Regarding claim 43, analyses are analogous to those presented for claim 1 and are applicable for claim 43.
Claim(s) 6 and 19 rejected under 35 U.S.C. 103 as being unpatentable over US 20230419159 A1-HEO et al (Hereinafter referred to as “HEO”), in view of HASTINGS, et al., "Dynamically Generated Logical Qubits", arXiv:2107.02194v2, October 12, 2021, 19 pages), in further view of US 20190165244 A1-Hertzberg et al (hereinafter referred to as “Hertz”).
Regarding claim 6, HEO discloses the method of claim 1 (See claim 1),
HEO and Hastings fail to disclose wherein updating the quantum error correction code comprises tuning dimensions of physical qubit devices over qudits based on the target values and the observed values of the logical errors.
However, in the same field of endeavor, Hertz discloses wherein updating the quantum error correction code comprises tuning dimensions of physical qubit devices over qudits based on the target values and the observed values of the logical errors ([0009]-0016]).
Therefore, it would have been obvious to one of ordinary skilled in the art before the effective filing date of the claimed invention to disclose a method disclosed by HEO and Hastings to disclose wherein updating the quantum error correction code comprises tuning dimensions of physical qubit devices over qudits based on the target values and the observed values of the logical errors as taught by Hertz, to improved coherence time of the multi-qubit chip ([0018], Hertz)
Regarding claim 19, analyses are analogous to those presented for claim 6 and are applicable for claim 19.
Claim(s) 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over US 20230419159 A1-HEO et al (Hereinafter referred to as “HEO”), in view of HASTINGS, et al., "Dynamically Generated Logical Qubits", arXiv:2107.02194v2, October 12, 2021, 19 pages), in view of Us 20210194507 A1-Delfosse.
Regarding claim 8, HEO discloses the method of claim 7 ( see claim 7),
HEO and Hastings fail to disclose wherein the quantum computing system comprises a superconducting quantum processing unit comprising coupling elements between respective pairs of qubit devices, and applying the quantum error correction code comprises operating a subset of the coupling elements.
However, in the same field of endeavor, Delfosse discloses wherein the quantum computing system comprises a superconducting quantum processing unit comprising coupling elements between respective pairs of qubit devices, and applying the quantum error correction code comprises operating a subset of the coupling elements ([0092-0093]).
Therefore, it would have been obvious to one of ordinary skilled in the art before the effective filing date of the claimed invention to disclose a method disclosed by HEO and Hastings to disclose wherein the quantum computing system comprises a superconducting quantum processing unit comprising coupling elements between respective pairs of qubit devices, and applying the quantum error correction code comprises operating a subset of the coupling elements as taught by Delfosse, to improving qubit quality (e.g., into the 10.sup.−4 or 10.sup.−5 range) to scale up quantum hardware and its classical control to reach the regime of practical applications for the isolated fault decoder ([0085], Delfosse)
Regarding claim 9, Delfosse discloses the method of claim 8, wherein each of the plurality of planar code patches comprises a respective stabilizer check qubit, and applying the quantum error correction code comprises activating a coupling element communicably coupled between a stabilizer check qubit in an X-type stabilizer patch and a stabilizer check qubit in a Z-type stabilizer patch ([0039]).
Allowable Subject Matter
Claims 10-13 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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LERON . BECK
Examiner
Art Unit 2487
/LERON BECK/ Primary Examiner, Art Unit 2487
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