DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
However, should applicant desire to obtain the benefit of foreign priority under 35U.S.C. 119(a)-(d) prior to declaration of an interference, a certified English translation of the foreign application must be submitted in reply to this action. 37 CFR 41.154(b) and 41.202(e). Failure to provide a certified translation may result in no benefit being accorded for the non-English application.
Information Disclosure Statement
The information disclosure statements (IDS) filed on July 3rd, 2024 and June 24th, 2026, is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following suggested title is just one possibility: “Semiconductor Device for Non-Volatile Memory With Specific Ratio of Sidewall Widths and Gate Length”.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 4 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 4, the claim recites “the second insulating film is a TEOS oxide film.” While this limitation draws exact-matching support from paragraph [0109] of the instant specification, it is unclear what, exactly, is meant by “a TEOS oxide film.” From paragraph [0091] of the instant specification, it becomes clear that TEOS (tetraethyl orthosilicate: Si(OC2H5)4) is a precursor used in a chemical vapor deposition (CVD) process. Indeed, one can easily find reference to and support for the use of gaseous TEOS in CVD of SiO2 films (such as in Lowe et al., US PGPub 2003/0203577 A1).
Therefore, it remains unclear what is meant by “a TEOS oxide film” when TEOS is an established gaseous precursor, and particularly with respect to the claim upon which claim 4 depends, wherein there is introduced the limitation that “the second insulating film is made of SiO2.” Is the second insulating film made of SiO2? Is it some gaseous film, somehow, and so no longer SiO2 but now Si(OC2H5)4?
For purposes of examination, the Examiner has interpreted Claim 4 as to mean that the second insulating film is SiO2 formed by a CVD method using TEOS (paragraph [0091] of the instant specification), and so has been interpreted as follows:
Claim 4: The semiconductor device according to claim 3, wherein the first insulating film is a thermal oxide film of polysilicon, and the second insulating film is a TEOS-formed silicon oxide film.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 5-7, and 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Ema et al., US PGPub 2016/0284720 A1 (hereinafter referred to as “Ema”).
Regarding Claim 1, Ema discloses A semiconductor device comprising (FIG. 13, semiconductor device 1C, [0168]):
a semiconductor layer having a main surface (FIG. 13, semiconductor substrate 2, [0168]);
a well region formed in a surface portion of the main surface of the semiconductor layer (FIG. 13, well region 6 of a p-type conductivity; [0157]);
a first region and a second region formed in a surface portion of the well region to be spaced from each other in a first direction, the first region and the second region having a first conductivity type, the well region having a second conductivity type (FIG. 13, impurity regions 14a, 14b of an n-type conductivity spaced in a first direction from each other, well region 6 of a p-type conductivity; [0087, 0091, 0105, 0157]);
a planar gate structure including a gate insulating film and a gate electrode formed to be stacked on the main surface of the semiconductor layer in a second direction so as to face a channel region between the first region and the second region (FIG. 13, gate insulating film 11, gate electrode 12, wherein the gate insulating film 11 and gate electrode 12 taken together form the planar gate structure, stacked on semiconductor substrate 2 stacked in a second direction thereby facing the channel region 16 between impurity regions 14a, 14b);
and a sidewall structure disposed adjacent to a lateral side in the first direction of the planar gate structure disposed on a side of the first region, wherein the sidewall structure includes a first insulating film and a second insulating film, and a charge storage film disposed between the first insulating film and the second insulating film, the first insulating film is adjacent to the planar gate structure in the first direction (FIG. 13, sidewall insulating film 13, which includes insulating oxide film 13a and charge storage film 13b and “the sidewall insulating film 13 may be made to have a three-layer structure obtained by further providing an oxide film” [0090], and which is adjacent to the gate insulating film 11 and gate electrode 12),
The third embodiment of Ema, semiconductor device 1C, does not explicitly disclose a gate length or sidewall width, as in and a ratio between a gate length of the planar gate structure along the first direction and a width of the sidewall structure along the first direction is less than or equal to 300/75.
However, the planar gate structure of 1C and the second embodiment 1D are identical and 1D does disclose a range of gate lengths and sidewall widths. Of particular importance, 1D uses the same materials, transistor structure, sidewall structure, and composition of said sidewall as taught in 1C ([0130-0133, 0145]), with the only main differences between the two embodiments is the provision of an impurity region 47 (either in place of, or in addition to, well region 6) and lightly doped drain regions 45a, 45b, neither of which would have an impact on chosen and disclosed gate length and sidewall width ranges being the same between embodiments. That is, there would be no unexpected results or lack of performance of the device which would prevent the disclosed gate length and sidewall widths of the second embodiment from applying to the third embodiment, wherein the impact of such dimensions would result in the same predictable result and effect on device parameters (such as the gate length impact on the Id/Vg curves as seen in FIGs. 5B-5C and the sidewall width impact on hot electron injection and charge accumulation).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the same dimension parameters disclosed in the second embodiment 1D to the third embodiment 1C, i.e., and a ratio between a gate length of the planar gate structure along the first direction and a width of the sidewall structure along the first direction is less than or equal to 300/75 (FIG. 5A, gate length Lg of 0.1µm to 0.5µm and sidewall width W1 of 74nm [0145], which results in a ratio of Lg/W1 of (0.1µm/74nm = 1.3) which is less than or equal to (300/75 = 4), for the same expected and predictable effect of allowing for control of/adjusting of the Id/Vg curve and hot electron/carrier injection and charge accumulation.
Regarding Claim 5, Ema discloses the semiconductor device according to claim 1 as discussed above.
Ema further discloses wherein, when the gate length is less than or equal to 0.3 µm, the width of the sidewall structure is more than or equal to 75 nm (FIG. 5A, gate length Lg of 0.1µm to 0.5µm and sidewall width W1 of 74nm, wherein Lg range includes such less than or equal to 0.3µm and the sidewall width W1 is substantially equal to 75nm).
Regarding Claim 6, Ema discloses the semiconductor device according to claim 1 as discussed above.
Ema further discloses wherein the first conductivity type is an n type, and the second conductivity type is a p type (FIG. 13, impurity regions 14a, 14b of an n-type conductivity, spaced in a first direction well region of a p-type conductivity; [0087, 0091, 0105, 0157]).
Regarding Claim 7, Ema discloses the semiconductor device according to claim 1 as discussed above.
Ema further discloses wherein the semiconductor device is configured to inject hot electrons into the charge storage film during a write operation (FIG. 1, 13, hot electrons flowing from channel region 16 to impurity region 14b become hot electrons due to the electric field from positive voltage applied to gate electrode 12 and impurity region 14b during a write operation; hot electrons are then injected and accumulate in the sidewall insulating film 13, in the charge accumulating nitride film 13b when in a three-layer sidewall structure as previously discussed; [0094, 0106]).
Regarding Claim 8, Ema discloses a semiconductor device comprising (FIG. 13, semiconductor device 1C; [0168]):
a semiconductor layer having a main surface (FIG. 13, semiconductor substrate 2; [0168]);
a memory element formed in the semiconductor layer (FIG. 13, memory transistor 10; [0155, 0168]);
and a transistor formed in the semiconductor layer (FIG. 13, logic transistor 20; [0168]),
wherein the memory element includes a first region and a second region formed in a surface portion of a first well region formed in a surface portion of the main surface of the semiconductor layer, to be spaced from each other in a first direction (FIG. 13, impurity regions 14a, 14b in well region 6 spaced from each other in a horizontal direction; [0155, 0157, 0168]),
the first region and the second region having a first conductivity type, the first well region having a second conductivity type (FIG. 13, impurity regions 14a, 14b of an n-type conductivity; [0091, 0105]),
a first planar gate structure including a first gate insulating film and a first gate electrode formed to be stacked on the main surface of the semiconductor layer in a second direction intersecting the main surface so as to face a channel region between the first region and the second region (FIG. 13, gate insulating film 11, gate electrode 12, wherein the gate insulating film 11 and gate electrode 12 taken together form the planar gate structure, stacked on semiconductor substrate 2 in a second direction, i.e., vertically, thereby facing the channel region 16 between the impurity regions 14a, 14b; [0158-0159]),
and a first sidewall structure disposed adjacent to a lateral side in the first direction of the first planar gate structure disposed on a side of the first region, the first sidewall structure includes a first insulating film and a second insulating film, and a charge storage film disposed between the first insulating film and the second insulating film, the first insulating film is adjacent to the first planar gate structure in the first direction (FIG. 13, sidewall insulating film 13 which includes insulating oxide film 13a adjacent to the planar gate structure in the first direction, i.e., horizontally, charge storage nitride film 13b, and “the sidewall insulating film 13 may be made to have a three-layer structure obtained by further providing an oxide film”; [0090]),
the transistor includes a third region and a fourth region formed in a surface portion of a second well region formed in the surface portion of the main surface of the semiconductor layer so as to be spaced from each other in a third direction (FIG. 13, logic transistor 20, impurity regions 24a, 24b spaced from each other in a third direction, e.g., horizontally, well region 6, semiconductor substrate 2; [0167]),
the third region and the fourth region having the first conductivity type, the second well region having the second conductivity type (FIG. 13, n-type impurity regions 24a, 24b, p-type well region 6; [0157, 0167]),
a second planar gate structure including a second gate insulating film and a second gate electrode formed to be stacked on the main surface of the semiconductor layer in the second direction so as to face a channel region between the third region and the fourth region, the second direction intersecting the main surface (FIG. 13, gate insulating film 21, gate electrode 22, which taken together form the planar gate structure, stacked in the second direction, i.e., vertically, thereby facing the channel region 26 between n-type impurity regions 24a, 24b; [0158, 0163]),
and a second sidewall structure disposed adjacent to a lateral side in the third direction of the second planar gate structure disposed on a side of the third region (FIG. 13, sidewall insulating film 23 on a side of the n-type impurity regions 24a, 24b and adjacent to a lateral side in the third direction, e.g., horizontally, gate insulating film 22, gate electrode 23; [0165]),
the second sidewall structure includes a third insulating film and a fourth insulating film, and a fifth insulating film disposed between the third insulating film and the fourth insulating film, the third insulating film is adjacent to the second planar gate structure in the third direction (FIG. 13, sidewall insulating film 23 may be made of a stacked, or laminate, structure same as sidewall 13, wherein the sidewall has a third insulating film of silicon oxide adjacent to the planar gate structure, a fifth insulating film of silicon nitride, and a fourth insulating film of silicon oxide similar to the third insulating film; [0090, 0098]),
The third embodiment of Ema, semiconductor device 1C, does not explicitly disclose a gate length or sidewall width, as in and a ratio between a first gate length of the first planar gate structure along the first direction and a first width of the first sidewall structure along the first direction is less than or equal to 300/75.
However, the planar gate structure of 1C and the second embodiment 1D are identical and 1D does disclose a range of gate lengths and sidewall widths. Of particular importance, 1D uses the same materials, transistor structure, sidewall structure, and composition of said sidewall as taught in 1C ([0130-0133, 0145]), with the only main differences between the two embodiments is the provision of an impurity region 47 (either in place of, or in addition to, well region 6) and lightly doped drain regions 45a, 45b, neither of which would have an impact on chosen and disclosed gate length and sidewall width ranges being the same between embodiments. That is, there would be no unexpected results or lack of performance of the device which would prevent the disclosed gate length and sidewall widths of the second embodiment from applying to the third embodiment, wherein the impact of such dimensions would result in the same predictable result and effect on device parameters (such as the gate length impact on the Id/Vg curves as seen in FIGs. 5B-5C and the sidewall width impact on hot electron injection and charge accumulation).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the same dimension parameters disclosed in the second embodiment 1D to the third embodiment 1C, i.e., and a ratio between a first gate length of the first planar gate structure along the first direction and a first width of the first sidewall structure along the first direction is less than or equal to 300/75 (FIG. 5A, gate length Lg of 0.1µm to 0.5µm and sidewall width W1 of 74nm [0145], which results in a ratio of Lg/W1 of (0.1µm/74nm = 1.3) which is less than or equal to (300/75 = 4), for the same expected and predictable effect of allowing for control of/adjusting of the Id/Vg curve and hot electron/carrier injection and charge accumulation.
Regarding Claim 9, Ema discloses the semiconductor device according to claim 8 as discussed above.
Ema further discloses wherein the first width of the first sidewall structure is larger than a second width of the second sidewall structure along the third direction (FIG. 13, sidewall width W1 is larger than sidewall width W2; [0090]).
Regarding Claim 10, Ema discloses the semiconductor device according to claim 9 as discussed above.
Ema further discloses wherein a ratio between a second gate length of the second planar gate structure along the third direction and the second width of the second sidewall structure is more than 300/75 (FIG. 13, sidewall width W1 is larger than sidewall width W2; FIG. 5A, as discussed above, discloses a gate length range and sidewall width W1 of 74nm. One of ordinary skill in the art would easily understand that a width of the second sidewall W2, which is disclosed as “smaller than a first sidewall width W1” of 74nm as taught by Ema, includes a sidewall width W2 of, for example, 24nm which is less than 74nm and thus, wherein the ratio of the second planar gate structure (of 0.1µm, for example) and the second width of the second sidewall W2 (of 24nm, for example) would be a ratio of (0.1µm/24nm = 4.16) which is more than (300/75 = 4).
Claims 2-4 are rejected under 35 U.S.C. 103 as being unpatentable over Ema as applied to Claim 1 above, and further in view of Yuda, US PGPub 2007/0126025 A1 (hereinafter referred to as Yuda).
Regarding Claim 2, Ema discloses the semiconductor device according to claim 1 as discussed above.
Ema discloses a thickness of the first insulating film but is silent on a thickness of the second insulating film, wherein a thickness of the first insulating film is thinner than a thickness of the second insulating film.
However, Yuda, which is directed to a similar semiconductor device with memory element and sidewall structures of multi-layer structure (such as oxide-nitride-oxide sidewalls), does disclose wherein the first insulating film of the sidewall structure is thinner than the second insulating film, or to put it another way, that the first oxide which is formed adjacent to the gate structure is thinner than the second oxide on the outside of the sidewall structure.
The sidewalls of both Ema and Yuda are composed of the same materials (silicon oxide and silicon nitride) in multi-layer laminates of at least three layers (silicon oxide-silicon nitride-silicon oxide) and for the same purpose of providing isolation and protection to the sidewall of the gates while also functioning as charge-trapping films for memory purposes. Although Ema does not explicitly disclose a thickness of the second insulating film, i.e., a thickness of the third layer silicon oxide in the oxide-nitride-oxide sandwich structure of both references, Yuda discloses thickness for the two oxide layers in the sidewall, in FIG. 3C, silicon oxide film 109 with a thickness of 10nm, silicon oxide film 111 with a thickness of 50nm, [0070-0071, 0098-0099] for the benefit of controlling contact wiring (“conductive films”) widths which lay between adjacent sidewall structures [0016].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the sidewall laminate structure of Ema with the more explicit thickness teachings of Yuda wherein a thickness of the first insulating film is thinner than a thickness of the second insulating film for the benefit of further controlling the conductive films thicknesses used as contact wiring
Regarding Claim 3, Ema discloses the semiconductor device according to claim 1 as discussed above.
Ema discloses wherein the charge storage film is made of SiN, and each of the first insulating film…is made of SiO2 (FIG. 13, oxide film 13a, nitride film 13b, silicon oxide is used for the oxide film 13a, silicon nitride is used for the nitride film 13b; [0090] but while implied and one of ordinary skill in the art would easily understand it as so, does not explicitly disclose that the second insulating film is made of SiO2.
However, Yuda, which is directed to a similar semiconductor device with memory element and sidewall structures of multi-layer structure (such as oxide-nitride-oxide sidewalls), does disclose does explicitly disclose that the second insulating film is made of SiO2 (FIG. 3C, side wall 131 comprising silicon oxide film 109, charge storage film 110 of silicon nitride, and silicon oxide film 111, [0070, 0098-0099]) for the known purposes of acting as a dielectric and charge barrier and enabling the sidewall in its function as an aid to performance and reliability ([0070-0071, 0098-0099, 0111]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Ema with the explicit sidewall laminate composition of Yuda to achieve the expected and predictable results of SiO2 functioning as an “oxide” as needed and disclosed in Ema, that is, acting as a dielectric and charge barrier in the ONO sidewall structure and resulting in the sidewall structure fulfilling its varied purposes of electrical isolation and improved performance of the semiconductor device.
Regarding Claim 4, Ema in view of Yuda (Ema/Yuda) discloses the semiconductor device according to claim 3 as discussed above.
Ema/Yuda further discloses wherein the first insulating film is a thermal oxide film of polysilicon, and the second insulating film is a TEOS oxide film (Yuda FIGs. 3A-3C, silicon oxide film 109 whereby “the silicon oxide film 109 is formed by means of the CVD method or thermal oxidation,” the second silicon oxide film 111 whereby “the silicon oxide film 111 is formed by depositing non-doped silicate glass (NSG) by means of the CVD method, for instance” using a “gas flow rate of TEOS”; [0098-0099]. Although Yuda discloses the first and second insulating films be SiO2 and the methods for which those are formed clearly read on that of the instant application, the current claim language can only be interpreted as a product-by-process and the Applicant is respectfully reminded that “even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985) and MPEP § 2113).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lin et al., US PGPub 2011/0244640 A1, which is directed to a method of manufacturing semiconductive devices with both memory and logic regions and, specifically, oxide-nitride-oxide spacers as sidewalls on the gate structures.
Shinohara, US PGPub 2017/0221917 A1, which is directed to a semiconductor device containing both a memory and logic region and similarly complex sidewall compositions and width to control performance and reliability as seen in previously cited references and the instant specification.
Sakagami et al., US Patent No. 5838041 A, which is directed to non-volatile semiconductor memory devices with memory transistors of a similar structure and function as disclosed in both the instant specification and Ema.
Lowe et al., US PGPub 2003/0203577 A1, which is directed to sidewall spacer formation in semiconductive devices, specifically detailing the use of TEOS as a precursor in CVD methods.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Austin T. Woodard whose telephone number is (571)270-1958. The examiner can normally be reached M-F, 8am to 5pm ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at (571) 272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Austin T Woodard/Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893
Prosecution Insights