DETAILED ACTION
Claims 1, 3-4, 6-9, 11-12, 14-17, 19-21 and 23 are present for examination.
Claims 1, 6, 9, 14, 17 and 20 have been amended.
Claims 2, 5, 10, 13, 18-19 and 22 have been canceled.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Amendment
Applicant's request for reconsideration of the finality of the rejection of the last Office action is persuasive and, therefore, the finality of that action is withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3-4, 6-9 11-12 and 14-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Haas Costa et al. (US 2018/0225059) in view of Molnar et al. (US10,114,760).
With respect claim 1, Hass Costa et al. teaches a memory configured to store data (see Fig. 3 and paragraph 38; non-volatile memory 322 may comprise a portion associated with read-only memory (ROM) 324 and a portion associated with storage 326); and
a controller (see Fig. 3 and paragraph 38; memory controller 318) configured to receive first address data based on multi-level paging from a processing unit (see paragraph 40; memory controller 318 receives module physical address from MMM 306 in CPU 302), convert the first address data into second address data by performing a page table walk on at least one of levels of the multi-level paging (see paragraphs 40-42; module controller 318 may translate the module physical address 332 to a physical memory address 334), and access the memory using the second address data (see paragraphs 40-42; module controller 318 may translate the module physical address 332 to a physical memory address 334, where the physical memory address 334 may correspond to a particular physical memory location of the volatile memory 320 or the non-volatile memory 322),
wherein, when a page table walk on a portion of the levels of the multi-level paging is performed by the processing unit (see paragraph 40; CPU 302 includes a TLB 310 that stores page table entries 312 with which the MMU 306 may translate a virtual address… the virtual address is first translated to a module physical address 332. In other words, the system 300 does not directly translate the virtual address to the physical memory address, instead, the virtual address is translated to an intermediate address (which in this case is referred to as the module physical address)), a remaining level of the page table walk of the multi-level paging is performed by the controller (see paragraph 40; at the memory module 316, the module controller 318 may translate the module physical address 332 to a physical memory address 334, where the physical memory address 334 may correspond to a particular physical memory location).
Haas Costa et al. does not teach wherein, when a page table walk on a portion of the levels of the multi-level paging is performed on a virtual address by the processing unit, the first address data comprises a conversion result of the portion of the levels of the page table walk, a remaining index of a remaining level of the multi-level paging, and a page offset.
However, Molnar et al. teaches wherein, when a page table walk on a portion of the levels of the multi-level paging is performed on a virtual address by the processing unit (see column 13, lines 10-30; IVA 504 is then translated in a similar fashion to generate the PA 506), the first address data comprises a conversion result of the portion of the levels of the page table walk (see Fig. 5B and column 13, lines 10-30; IVA 504), a remaining index of a remaining level of the multi-level paging (see Fig. B and column 13, lines 10-30; IVA 504 may comprise a number of portions used for the translation. In one embodiment, a first portion 541 is used as an index into a first level page table… second portion 542 of the IVA 504 is used as an index into the second level page table. Based on the second portion 542, a page table entry 545 from the second level page table is selected), and a page offset (see Fig. 5B and column 13, lines 10-30; base address 546 of the PA 506 is combined with an offset 547 represented by the third portion 543 of the IVA 504).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the device taught by Haas Costa et al. to include the above mentioned to improve translation of virtual addresses into physical addresses in the memory (see Molnar, column 6, lines 60-64).
With respect claim 3, Haas Costa et al. teaches wherein a virtual address is converted into the first address data by the page table walk on the portion of the levels (see paragraph 40; CPU 302 includes a TLB 310 that stores page table entries 312 with which the MMU 306 may translate a virtual address… the virtual address is first translated to a module physical address 332. In other words, the system 300 does not directly translate the virtual address to the physical memory address, instead, the virtual address is translated to an intermediate address (which in this case is referred to as the module physical address)), and
the first address data is converted into the second address data corresponding to a physical address by the remaining level of the page table walk (see paragraph 40; at the memory module 316, the module controller 318 may translate the module physical address 332 to a physical memory address 334, where the physical memory address 334 may correspond to a particular physical memory location).
With respect claim 4, Haas Costa et al. teaches wherein the controller is different from a memory management unit (MMU) of the processing unit (see Fig. 3 and paragraphs 38-39; controller 318 is different from MMU 306).
With respect claim 6, Haas Costa et al. does not teach wherein the controller is configured to determine the second address data by performing the remaining level of the page table walk of the multi-level paging based on the conversion result, the remaining index, and the page offset.
However, Molnar et al. teaches wherein the controller is configured to determine the second address data by performing the remaining level of the page table walk of the multi-level paging based on the conversion result (see Fig. 5B and column 13, lines 10-30; IVA 504… Based on the second portion 542, a page table entry 545 from the second level page table is selected and a base address 546 of the PA 506 is read from the page table entry 545), the remaining index (see Fig. B and column 13, lines 10-30; IVA 504 may comprise a number of portions used for the translation. In one embodiment, a first portion 541 is used as an index into a first level page table… second portion 542 of the IVA 504 is used as an index into the second level page table. Based on the second portion 542, a page table entry 545 from the second level page table is selected), and the page offset (see column 13, lines 10-30; base address 546 of the PA 506 is combined with an offset 547 represented by the third portion 543 of the IVA 504).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the device taught by Haas Costa et al. to include the above mentioned to improve translation of virtual addresses into physical addresses in the memory (see Molnar, column 6, lines 60-64).
With respect claim 7, Haas Costa et al. teaches a page table manager (see paragraph 40; CPU 302 includes a TLB 310 that stores page table entries 312),
wherein the controller is configured to convert the first address data into the second address data using the page table manager (see paragraph 40; CPU 302 includes a TLB 310 that stores page table entries 312 with which the MMU 306 may translate a virtual address).
Haas Costa et al. does not teach wherein a page table manager comprising a table cache storing recent page table data and a table walker performing a page table walk for searching for page table data required for the table cache when the page table data does not exist.
However, Molnar et al. teaches wherein MMU 390 receives a memory request including a virtual address in a first address space. At step 604, the MMU 390 determines whether a copy of a page table entry associated with the virtual address is stored in a TLB of the MMU 390. If the TLB does not store a copy of the page table entry associated with the virtual address, then, at step 606, the MMU 390 fetches the copy of the page table entry from the memory (see column 13, lines 64-67 and column 14, lines 1-17).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the device taught by Haas Costa et al. to include the above mentioned to improve translation of virtual addresses into physical addresses in the memory (see Molnar, column 6, lines 60-64).
With respect claim 8, Haas Costa et al. does not teach wherein the first address data indicates a huge page having a larger size than a regular page.
However, Molnar et al. teaches wherein page tables used for the first translation may be associated with pages that are larger than the pages required by the operating system. For example, the first translation of the AVA to the IVA may utilize page tables associated with 64 KB pages (see column 2, lines 39-45).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the device taught by Haas Costa et al. to include the above mentioned to improve translation of virtual addresses into physical addresses in the memory (see Molnar, column 6, lines 60-64).
With respect claim 9, Haas Costa et al. teaches receiving first address data based on multi-level paging from a processing unit (see paragraph 40; memory controller 318 receives module physical address from MMM 306 in CPU 302);
converting the first address data into second address data by performing a page table walk on at least one of levels of the multi-level paging (see paragraphs 40-42; module controller 318 may translate the module physical address 332 to a physical memory address 334); and
accessing the memory using the second address data (see paragraphs 40-42; module controller 318 may translate the module physical address 332 to a physical memory address 334, where the physical memory address 334 may correspond to a particular physical memory location of the volatile memory 320 or the non-volatile memory 322),
wherein, when a page table walk on a portion of the levels of the multi-level paging is performed by the processing unit (see paragraph 40; CPU 302 includes a TLB 310 that stores page table entries 312 with which the MMU 306 may translate a virtual address… the virtual address is first translated to a module physical address 332. In other words, the system 300 does not directly translate the virtual address to the physical memory address, instead, the virtual address is translated to an intermediate address (which in this case is referred to as the module physical address)), in an operation of converting the first address data into the second address data, a remaining level of the page table walk of the multi-level paging is performed by the memory device (see paragraph 40; at the memory module 316, the module controller 318 may translate the module physical address 332 to a physical memory address 334, where the physical memory address 334 may correspond to a particular physical memory location).
Haas Costa et al. does not teach wherein, when a page table walk on a portion of the levels of the multi-level paging is performed on a virtual address by the processing unit, the first address data comprises a conversion result of the portion of the levels of the page table walk, a remaining address data of a remaining level of the multi-level paging.
However, Molnar et al. teaches wherein, when a page table walk on a portion of the levels of the multi-level paging is performed on a virtual address by the processing unit (see column 13, lines 10-30; IVA 504 is then translated in a similar fashion to generate the PA 506), the first address data comprises a conversion result of the portion of the levels of the page table walk (see Fig. 5B and column 13, lines 10-30; IVA 504… Based on the second portion 542, a page table entry 545 from the second level page table is selected and a base address 546 of the PA 506 is read from the page table entry 545), a remaining address data of a remaining level of the multi-level paging (see column 10, lines 10-30; base address 546 of the PA 506 is combined with an offset 547 represented by the third portion 543 of the IVA 504. Again, the PA 506 may be n-bits or a different number of bits from either the AVA 502 or the IVA 504).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the device taught by Haas Costa et al. to include the above mentioned to improve translation of virtual addresses into physical addresses in the memory (see Molnar, column 6, lines 60-64).
With respect claim 11, Haas Costa et al. teaches wherein a virtual address is converted into the first address data by the page table walk on the portion of the levels (see paragraph 40; CPU 302 includes a TLB 310 that stores page table entries 312 with which the MMU 306 may translate a virtual address… the virtual address is first translated to a module physical address 332. In other words, the system 300 does not directly translate the virtual address to the physical memory address, instead, the virtual address is translated to an intermediate address (which in this case is referred to as the module physical address)), and the first address data is converted into the second address data corresponding to a physical address by the remaining level of the page table walk (see paragraph 40; at the memory module 316, the module controller 318 may translate the module physical address 332 to a physical memory address 334, where the physical memory address 334 may correspond to a particular physical memory location).
With respect claim 12, Haas Costa et al. teaches wherein the converting of the first address data into the second address data is performed by another component different from a memory management unit (MMU) of the processing unit (see Fig. 3 and paragraphs 38-39; controller 318 is different from MMU 306).
With respect claim 14, Haas Costa et al. does not teach wherein the converting of the first address data into the second address data comprises determining the second address data by performing the remaining level of the page table walk of the multi-level paging based on the conversion result and the remaining address data.
However, Molnar et al. teaches wherein the converting of the first address data into the second address data comprises determining the second address data by performing the remaining level of the page table walk of the multi-level paging based on the conversion result (see Fig. 5B and column 13, lines 10-30; IVA 504… Based on the second portion 542, a page table entry 545 from the second level page table is selected and a base address 546 of the PA 506 is read from the page table entry 545) and the remaining address data (see column 13, lines 10-30; base address 546 of the PA 506 is combined with an offset 547 represented by the third portion 543 of the IVA 504. Again, the PA 506 may be n-bits or a different number of bits from either the AVA 502 or the IVA 504).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Haas Costa et al. to include the above mentioned to improve translation of virtual addresses into physical addresses in the memory (see Molnar, column 6, lines 60-64).
With respect claim 15, Haas Costa et al. teaches wherein the converting of the first address data into the second address data comprises: converting the first address data into the second address data using a page table manager (see paragraph 40; CPU 302 includes a TLB 310 that stores page table entries 312 with which the MMU 306 may translate a virtual address).
Haas Costa et al. does not teach a page table manager comprising a table cache storing recent page table data and a table walker performing a page table walk for searching for page table data required for the table cache when the page table data does not exist.
However, Molnar et al. teaches wherein MMU 390 receives a memory request including a virtual address in a first address space. At step 604, the MMU 390 determines whether a copy of a page table entry associated with the virtual address is stored in a TLB of the MMU 390. If the TLB does not store a copy of the page table entry associated with the virtual address, then, at step 606, the MMU 390 fetches the copy of the page table entry from the memory (see column 13, lines 64-67 and column 14, lines 1-17).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Haas Costa et al. to include the above mentioned to improve translation of virtual addresses into physical addresses in the memory (see Molnar, column 6, lines 60-64).
With respect claim 16, Haas Costa et al. does not teach wherein the first address data indicates a huge page having a larger size than a regular page.
However, Molnar et al. teaches wherein page tables used for the first translation may be associated with pages that are larger than the pages required by the operating system. For example, the first translation of the AVA to the IVA may utilize page tables associated with 64 KB pages (see column 2, lines 39-45).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Haas Costa et al. to include the above mentioned to improve translation of virtual addresses into physical addresses in the memory (see Molnar, column 6, lines 60-64).
Claim(s) 17 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Haas Costa et al. (US 2018/0225059) in view of Kounavis et al. (US2021/0406199) and in further view of Molnar et al. (US10,114,760).
With respect claim 17, Haas Costa et al. teaches a memory configured to store data (see Fig. 3 and paragraph 38; non-volatile memory 322 may comprise a portion associated with read-only memory (ROM) 324 and a portion associated with storage 326); and
a controller (see Fig. 3 and paragraph 38; memory controller 318) configured to receive first address data based on multi-level paging from a host device (see paragraph 40; memory controller 318 receives module physical address from MMM 306 in CPU 302), convert the first address data into second address data by performing a page table walk on at least one of levels of the multi-level paging (see paragraphs 40-42; module controller 318 may translate the module physical address 332 to a physical memory address 334), and access the memory using the second address data (see paragraphs 40-42; module controller 318 may translate the module physical address 332 to a physical memory address 334, where the physical memory address 334 may correspond to a particular physical memory location of the volatile memory 320 or the non-volatile memory 322)’
wherein, when a page table walk on a portion of the levels of the multi-level paging is performed by the host device (see paragraph 40; CPU 302 includes a TLB 310 that stores page table entries 312 with which the MMU 306 may translate a virtual address… the virtual address is first translated to a module physical address 332. In other words, the system 300 does not directly translate the virtual address to the physical memory address, instead, the virtual address is translated to an intermediate address (which in this case is referred to as the module physical address)), a remaining level of the page table walk of the multi-level paging is performed by the controller (see paragraph 40; at the memory module 316, the module controller 318 may translate the module physical address 332 to a physical memory address 334, where the physical memory address 334 may correspond to a particular physical memory location).
Haas Costa et al. does not teach wherein a compute express link (CXL) memory device; and a controller configured to receive first address data based on multi-level paging from a host device using a CXL connection; and wherein, when a page table walk on a portion of the levels of the multi-level paging is performed on a virtual address by the processing unit, the first address data comprises a conversion result of the portion of the levels of the page table walk, a remaining index of a remaining level of the multi-level paging, and a page offset.
However, Kounavis et al. teaches wherein operation 310 an address translation request is received from a remote device via a host-to-device link, wherein the address translation request comprises a virtual address (VA) (see paragraph 42), examples of host-to-device link 142a-c include a PCIe link or a cache-coherent link (e.g., CXL) (see paragraph 28).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the device taught by Haas Costa et al. to include the above mentioned to to provide an access control mechanism which ensures that a remote device communicatively coupled to a host device via a protocol such as PCIe can only access HPAs that were explicitly assigned to a context of the device (see Kounavis, paragraph 37).
Haas Costa et al. does not teach wherein, when a page table walk on a portion of the levels of the multi-level paging is performed on a virtual address by the processing unit, the first address data comprises a conversion result of the portion of the levels of the page table walk, a remaining address data of a remaining level of the multi-level paging.
However, Molnar et al. teaches wherein, when a page table walk on a portion of the levels of the multi-level paging is performed on a virtual address by the processing unit (see column 13, lines 10-30; IVA 504 is then translated in a similar fashion to generate the PA 506), the first address data comprises a conversion result of the portion of the levels of the page table walk (see Fig. 5B and column 13, lines 10-30; IVA 504… Based on the second portion 542, a page table entry 545 from the second level page table is selected and a base address 546 of the PA 506 is read from the page table entry 545), a remaining address data of a remaining level of the multi-level paging (see column 10, lines 10-30; base address 546 of the PA 506 is combined with an offset 547 represented by the third portion 543 of the IVA 504. Again, the PA 506 may be n-bits or a different number of bits from either the AVA 502 or the IVA 504).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the device taught by Haas Costa et al. and Kounavis et al. to include the above mentioned to improve translation of virtual addresses into physical addresses in the memory (see Molnar, column 6, lines 60-64).
With respect claim 20, Haas Costa et al. and Kounavis et al. do not teach wherein the converting of the first address data into the second address data comprises determining the second address data by performing the remaining level of the page table walk of the multi-level paging based on the conversion result and the remaining address data.
However, Molnar et al. teaches wherein the converting of the first address data into the second address data comprises determining the second address data by performing the remaining level of the page table walk of the multi-level paging based on the conversion result (see Fig. 5B and column 13, lines 10-30; IVA 504… Based on the second portion 542, a page table entry 545 from the second level page table is selected and a base address 546 of the PA 506 is read from the page table entry 545) and the remaining address data (see column 13, lines 10-30; base address 546 of the PA 506 is combined with an offset 547 represented by the third portion 543 of the IVA 504. Again, the PA 506 may be n-bits or a different number of bits from either the AVA 502 or the IVA 504).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Haas Costa et al. and Kounavis et al. to include the above mentioned to improve translation of virtual addresses into physical addresses in the memory (see Molnar, column 6, lines 60-64).
Claim(s) 21 and 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Matsudaira et al. (US 2015/0339223) in view of Molnar et al. (US10,114,760).
With respect claim 21, Matsudaira et al. teaches a memory device including a memory (see Fig. 1 and paragraph 20; memory system including memory 20 and 30) and a controller (see Fig. 1 and paragraph 20; memory system 20 including controller 10); and
a processing unit configured to perform at least one of a plurality of levels of a page table walk on a first virtual address to output a second virtual address to the memory device (see paragraph 33; the first logical address is translated into the second logical address using a predetermined translation algorithm such as shifting the first logical address rightward by the amount corresponding to the size of a cluster),
wherein the controller is configured to perform at least one remaining level among the plurality of levels of the page table walk on the second virtual address to generate a third virtual address to access data stored in the memory (see paragraph 33; the first logical address is translated into the second logical address using a predetermined translation algorithm such as shifting the first logical address rightward by the amount corresponding to the size of a cluster. The processing unit translates the second logical address into a third logical address including a logical block number based on the first translation information 31).
Matsudaira et al. does not teach wherein the controller adds a page offset to the third virtual address to generate a physical address and accesses the data using the physical address.
However, Molnar et al. teaches wherein the controller adds a page offset to the third virtual address to generate a physical address and accesses the data using the physical address (see column 13, lines 10-30; base address 546 of the PA 506 is combined with an offset 547 represented by the third portion 543 of the IVA 504. Again, the PA 506 may be n-bits or a different number of bits from either the AVA 502 or the IVA 504).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the device taught by Matsudaira et al. to include the above mentioned to improve translation of virtual addresses into physical addresses in the memory (see Molnar, column 6, lines 60-64).
With respect claim 23, Matsudaira et al. does not teach wherein the memory is configured to store regular pages having a first size, huge pages having a second size larger than the first size, and the first virtual address corresponds to one of the huge pages.
However, Molnar et al. teaches wherein page tables used for the first translation may be associated with pages that are larger than the pages required by the operating system. For example, the first translation of the AVA to the IVA may utilize page tables associated with 64 KB pages (see column 2, lines 39-45).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the device taught by Matsudaira et al. to include the above mentioned to improve translation of virtual addresses into physical addresses in the memory (see Molnar, column 6, lines 60-64).
Response to Arguments
Applicant’s reply, filed 02/12/2026, amending the claims to include previously indicated allowable subject matter have been fully considered. However, upon further consideration, a ground(s) of rejection is made in view of Molnar et al. (US10,114,760).
Claim 1: Molnar et al. teaches wherein, when a page table walk on a portion of the levels of the multi-level paging is performed on a virtual address by the processing unit (see column 13, lines 10-30; IVA 504 is then translated in a similar fashion to generate the PA 506), the first address data comprises a conversion result of the portion of the levels of the page table walk (see Fig. 5B and column 13, lines 10-30; IVA 504), a remaining index of a remaining level of the multi-level paging (see Fig. B and column 13, lines 10-30; IVA 504 may comprise a number of portions used for the translation. In one embodiment, a first portion 541 is used as an index into a first level page table… second portion 542 of the IVA 504 is used as an index into the second level page table. Based on the second portion 542, a page table entry 545 from the second level page table is selected), and a page offset (see Fig. 5B and column 13, lines 10-30; base address 546 of the PA 506 is combined with an offset 547 represented by the third portion 543 of the IVA 504).
Claims 9 and 17: Molnar et al. also teaches wherein, when a page table walk on a portion of the levels of the multi-level paging is performed on a virtual address by the processing unit (see column 13, lines 10-30; IVA 504 is then translated in a similar fashion to generate the PA 506), the first address data comprises a conversion result of the portion of the levels of the page table walk (see Fig. 5B and column 13, lines 10-30; IVA 504… Based on the second portion 542, a page table entry 545 from the second level page table is selected and a base address 546 of the PA 506 is read from the page table entry 545), a remaining address data of a remaining level of the multi-level paging (see column 10, lines 10-30; base address 546 of the PA 506 is combined with an offset 547 represented by the third portion 543 of the IVA 504. Again, the PA 506 may be n-bits or a different number of bits from either the AVA 502 or the IVA 504).
Claim 21: Molnar et al. teaches wherein the controller adds a page offset to the third virtual address (i.e., an intermediate address created as the original virtual address is translated) to generate a physical address and accesses the data using the physical address (see column 13, lines 10-30; base address 546 of the PA 506 is combined with an offset 547 represented by the third portion 543 of the IVA 504. Again, the PA 506 may be n-bits or a different number of bits from either the AVA 502 or the IVA 504).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the device taught by Matsudaira et al. to include the above mentioned to improve translation of virtual addresses into physical addresses in the memory (see Molnar, column 6, lines 60-64).
Conclusion
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/ARACELIS RUIZ/ Primary Examiner, Art Unit 2139