DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 11 June 2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 8-20, and 22-23 are rejected under 35 U.S.C. 103 as being unpatentable over Kawashima et al. (hereinafter “Kawashima” US 2024 / 0420626) in view of Richter et al. (hereinafter “Richter” US 2021 / 0335218).
As pertaining to Claim 1, Kawashima discloses (see Fig. 1, Figs. 12A and 12B, and Fig. 15) a display device (see Page 10, Para. [0165]) comprising:
a first sub-pixel (see any (10) in Fig. 15) including a first light emitting element (see (110) in Fig. 1), a first pixel driving circuit (see (11, 12) in Fig. 1) that drives the first light emitting element (110), and a fourth light emitting element (again, see (110) in Fig. 1) that fails to emit light (i.e., arbitrarily) even when driving power (i.e., an arbitrary driving power) is applied (i.e., to any arbitrary row, column, and/or portion of (11, 12) in any row/column; see Page 10, Para. [0167] and note that driving power is sequentially applied to rows/columns of sub-pixels such that some light emitting elements emit light and some light emitting elements fail to emit light even when driving power is applied to arbitrary portions of the display device); and
a second sub-pixel (see any other (10) in Fig. 15) including a second light emitting element (again, see (110) in Fig. 1), a second pixel driving circuit (again, see (11, 12) in Fig. 1) that drives the second light emitting element (110), a third light emitting element (again, see (110) in Fig. 1) and a third pixel driving circuit (again, see (11, 12) in Fig. 1) that drives the third light emitting element (110; see Page 3, Para. [0060]-[0063]),
wherein the first pixel driving circuit (see (11, 12) in Fig. 1) controls the first light emitting element (110) to emit light in a first control mode (i.e., a first current control mode; see Figs. 12A and 12B), when a target luminance of the first sub-pixel (10) is included in a high luminance section (again, see Figs. 12A and 12B), and
wherein the second pixel driving circuit (see (11, 12) in Fig. 1) controls the second light emitting element (110) to emit light in a second control mode (i.e., a second current control mode; see Figs. 12A and 12B), when a target luminance of the second sub-pixel (10) is included in the high luminance section (again, see Figs. 12A and 12B; see Page 4, Para. [0068] and [0070]; and Page 9 through Page 10, Para. [0157]-[0161]).
Kawashima discloses a display device architecture (see Fig. 21B) comprising a backplane (282, 283) as a pixel driving circuit portion and a pixel portion (284) disposed on the pixel driving circuit portion (282, 283), wherein each sub-pixel is disposed in the pixel portion (284; see Page 15, Para. [0249]-[0250]). However, Kawashima does not explicitly show that a second electrode, namely a cathode of the first to fourth light emitting elements, is disposed on the first to fourth light emitting elements, wherein the second electrode is commonly connected to a plurality of sub-pixels, namely as a common cathode. Further, Kawashima does not explicitly disclose that the second light emitting element and the third light emitting element of the second sub-pixel, as redundant light emitting elements, emit light of a same color.
However, in the same field of endeavor, Richter discloses (see Fig. 9) a display device architecture implementing sub-pixel redundancy comprising at least a first sub-pixel (21) including a first light emitting element (31) and a fourth light emitting element (32) that, as an arbitrary defective light emitting element, fails to emit light even when driving power is applied, and a second sub-pixel (22) including a second light emitting element (31) and a third light emitting element (32), wherein each sub-pixel (21, 22) comprises a respective pixel driving circuit (4, 5, 52). Richter discloses that the display device architecture further comprises a second electrode (62), namely a common cathode of the first to fourth light emitting elements (31, 32), that is disposed on the first to fourth light emitting elements (31, 32), wherein the second light emitting element (31) and the third light emitting element (32), as redundant light emitting elements, emit light of a same color (see (22)), and wherein the second electrode (62) is commonly connected to a plurality of sub-pixels (see (21, 22, 23); and see Page 4, Para. [0075]-[0078]; and Page 6, Para. [0118]). It is a goal of Richter to provide a display device architecture in which display sub-pixels comprise redundant light emitting elements of the same color, such that a defective sub-pixel can be detected and efficiently corrected to reduce the impact of the defective sub-pixel on display quality (see Page 1, Para. [0005]-[0007], [0011], [0014], and [0016]). That is, Richter discloses that, for example, for an arbitrary fourth light emitting element (32) that fails to emit light even when driving power is applied directly to the fourth light emitting element (32), display quality can be improved and the effects of the defective light emitting element can be mitigated by providing each sub-pixel with a redundant light emitting element of a same color and a respective pixel driving circuit wherein the sub-pixels have a common cathode configuration (see Page 2, Para. [0024]-[0027] and [0030]; and Page 3, Para. [0038]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kawashima with the teachings of Richter, such that the display device of Kawashima is implemented using the display device architecture suggested by Richter, in which a second electrode, namely a cathode of the first to fourth light emitting elements, is disposed on the first to fourth light emitting elements, wherein the second electrode is commonly connected to a plurality of sub-pixels, namely as a common cathode, and the second light emitting element and the third light emitting element of the second sub-pixel, as redundant light emitting elements, emit light of a same color, in order to provide a means for improving display quality and mitigating the effects of defective light emitting elements as suggested by Richter.
As pertaining to Claim 2, Kawashima discloses (see Fig. 1, Figs. 12A and 12B, and Fig. 15) that a magnitude of a data signal (i.e., (DATAA) at (122) in Fig. 1) is changed to adjust a luminance of a light emitting element (110), in the first control mode (i.e., the first current control mode; again, see Figs. 12A and 12B), and
wherein the magnitude of the data signal (i.e., (DATAA) at (122) in Fig. 1) is maintained (i.e., for any arbitrary period of time), in the second control mode (i.e., the second current control mode; again, see Page 4, Para. [0068] and [0070]; and Page 9 through Page 10, Para. [0157]-[0161] and Figs. 12A and 12B).
As pertaining to Claim 3, Kawashima discloses (see Fig. 1, Figs. 12A and 12B, and Fig. 15) that the first sub-pixel (see any (10) in Fig. 15) and the second sub-pixel (see any other (10) in Fig. 15) implement the same color (i.e., arbitrarily; see Page 13, Para. [0217]-[0218]).
As pertaining to Claim 4, Kawashima discloses (see Fig. 1, Figs. 12A and 12B, and Fig. 15) that the first pixel driving circuit (see (11, 12) in Fig. 1) controls the first light emitting element (110) to emit light in the first control mode (i.e., the first current control mode; see Figs. 12A and 12B), when the target luminance of the first sub-pixel (10) is included in a low luminance section (again, see Figs. 12A and 12B), and
wherein the second pixel driving circuit (see (11, 12) in Fig. 1) controls the second light emitting element (110) to emit light in the first control mode (i.e., the first current control mode; see Figs. 12A and 12B), when the target luminance of the second sub-pixel (10) is included in the low luminance section (again, see Figs. 12A and 12B; see Page 4, Para. [0068] and [0070]; and Page 9 through Page 10, Para. [0157]-[0161]).
As pertaining to Claim 5, Kawashima discloses (see Fig. 1, Figs. 12A and 12B, and Fig. 15) that the first pixel driving circuit (see (11, 12) in Fig. 1) controls the first light emitting element (110) to emit light in the second control mode (i.e., the second current control mode; see Figs. 12A and 12B) and adjusts a luminance of the first light emitting element (110) by changing an emission time (i.e., (DATAW) at (121) in Fig. 1) of the first light emitting element (110), when the target luminance of the first sub-pixel (10) is included in a medium luminance section between the low luminance section and the high luminance section (again, see Figs. 12A and 12B), and
wherein the second pixel driving circuit (see (11, 12) in Fig. 1) controls the second light emitting element (110) to emit light in the second control mode (i.e., the second current control mode; see Figs. 12A and 12B) and adjusts a luminance of the second light emitting element (110) by changing an emission time (i.e., (DATAW) at (121) in Fig. 1) of the second light emitting element (110), when the target luminance of the second sub-pixel (10) is included in the medium luminance section (again, see Figs. 12A and 12B; see Page 4, Para. [0068] and [0070]; and Page 9 through Page 10, Para. [0157]-[0161]).
As pertaining to Claim 8, Kawashima discloses (see Fig. 1, Figs. 12A and 12B, and Fig. 15) that the third pixel driving circuit (again, see (11, 12) in Fig. 1) controls the third light emitting element (110) to emit light, when the target luminance of the second sub-pixel (10) is included in the high luminance section (again, see Figs. 12A and 12B; see Page 4, Para. [0068] and [0070]; and Page 9 through Page 10, Para. [0157]-[0161]; and note that the light emitting elements (110) are separately controllable).
As pertaining to Claim 9, Kawashima discloses (see Fig. 1, Figs. 12A and 12B, and Fig. 15) that the third pixel driving circuit (again, see (11, 12) in Fig. 1) adjusts a luminance of the third light emitting element (110) by changing a magnitude of a data signal (again, see Figs. 12A and 12B; see Page 4, Para. [0068] and [0070]; and Page 9 through Page 10, Para. [0157]-[0161]).
As pertaining to Claim 10, Kawashima discloses (see Fig. 1, Figs. 12A and 12B, and Fig. 15) that the third pixel driving circuit (again, see (11, 12) in Fig. 1) adjusts a luminance of the third light emitting element (110) by changing an emission time of the third light emitting element (110; again, see Figs. 12A and 12B; see Page 4, Para. [0068] and [0070]; and Page 9 through Page 10, Para. [0157]-[0161]).
As pertaining to Claim 11, Kawashima discloses (see Fig. 1, Figs. 12A and 12B, and Fig. 15) that each of the first pixel driving circuit (see (11, 12)), the second pixel driving circuit (see (11, 12)), and the third pixel driving circuit (again, see (11, 12)) includes:
a driving transistor (105) which supplies a driving circuit for driving the light emitting element (110) based on the data signal (see (DATAA) at (122)); and
a light emitting transistor (104) which applies the driving current to the light emitting element (110) based on a light emitting control signal (see (DATAW) at (121); and see Page 3, Para. [0060]-[0063]; Page 4, Para. [0068] and [0070]; and Page 9 through Page 10, Para. [0157]-[0161]).
As pertaining to Claim 12, Kawashima discloses (see Fig. 1, Figs. 12A and 12B, and Fig. 15) that the data signal (see (DATAA) at (122)) includes a pulse amplitude modulation (PAM) signal in an analog form (i.e., an arbitrary voltage form), and
wherein the light emitting control signal (see (DATAW) at (121)) includes a pulse width modulation (PWM) signal in a digital form (i.e., an arbitrary on/off voltage form; again, see Page 4, Para. [0068] and [0070]; and Page 9 through Page 10, Para. [0157]-[0161]).
As pertaining to Claim 13, Kawashima discloses (see Fig. 1, Figs. 12A and 12B, and Fig. 15) that the light emitting control signal (see (DATAW) at (121)) having a minimum pulse width (i.e., an arbitrary pulse width) is applied to the first pixel driving circuit (see (11, 12)) when the target luminance of the first sub-pixel (10) is a maximum luminance (i.e., an arbitrary luminance) of the low luminance section (see Figs. 12A and 12B for a low luminance section), and
wherein the light emitting control signal (see (DATAW) at (121)) having the minimum pulse width (i.e., an arbitrary pulse width) is applied to the second pixel driving circuit (see (11, 12)) when the target luminance of the second sub-pixel (10) is the maximum luminance (i.e., an arbitrary luminance) of the low luminance section (again, see Figs. 12A and 12B for a low luminance section; and again, see Page 4, Para. [0068] and [0070]; and Page 9 through Page 10, Para. [0157]-[0161]).
As pertaining to Claim 14, Kawashima discloses (see Fig. 1, Figs. 12A and 12B, and Fig. 15) that the light emitting control signal (see (DATAW) at (121)) having a minimum pulse width (i.e., an arbitrary pulse width) is applied to the first pixel driving circuit (see (11, 12)) when the target luminance of the first sub-pixel (10) is a minimum luminance (i.e., an arbitrary luminance) of the medium luminance section (see Figs. 12A and 12B for a medium luminance section), and
wherein the light emitting control signal (see (DATAW) at (121)) having the minimum pulse width (i.e., an arbitrary pulse width) is applied to the second pixel driving circuit (see (11, 12)) when the target luminance of the second sub-pixel (10) is the minimum luminance (i.e., an arbitrary luminance) of the medium luminance section (again, see Figs. 12A and 12B for a medium luminance section; and again, see Page 4, Para. [0068] and [0070]; and Page 9 through Page 10, Para. [0157]-[0161]).
As pertaining to Claim 15, Kawashima discloses (see Fig. 1, Figs. 12A and 12B, and Fig. 15) that the light emitting control signal (see (DATAW) at (121)) having a maximum pulse width (i.e., an arbitrary pulse width) is applied to the first pixel driving circuit (see (11, 12)) when the target luminance of the first sub-pixel (10) is a maximum luminance (i.e., an arbitrary luminance) of the medium luminance section (see Figs. 12A and 12B for a medium luminance section; and again, see Page 4, Para. [0068] and [0070]; and Page 9 through Page 10, Para. [0157]-[0161]).
As pertaining to Claim 16, Kawashima discloses (see Fig. 1, Figs. 12A and 12B, and Fig. 15) that the light emitting control signal (see (DATAW) at (121)) having the maximum pulse width (i.e., an arbitrary pulse width) includes a duty ratio of 100% (i.e., arbitrarily; see Page 1, Para. [0010]; and again, see Page 4, Para. [0068] and [0070]; and Page 9 through Page 10, Para. [0157]-[0161] and note that the duty ratio of the light emitting control signal can include any arbitrary duty ratio).
As pertaining to Claim 17, Kawashima discloses (see Fig. 1, Figs. 12A and 12B, and Fig. 15) that the light emitting control signal (see (DATAW) at (121)) having the maximum pulse width (i.e., an arbitrary pulse width) is applied to the first pixel driving circuit (see (11, 12)) when the target luminance of the first sub-pixel (10) is included in the high luminance section (see Figs. 12A and 12B for a high luminance section; and again, see Page 4, Para. [0068] and [0070]; and Page 9 through Page 10, Para. [0157]-[0161]).
As pertaining to Claim 18, Kawashima discloses (see Fig. 1, Figs. 12A and 12B, and Fig. 15) that the light emitting control signal (see (DATAW) at (121)) having a maximum pulse width (i.e., an arbitrary pulse width) is applied to the second pixel driving circuit (see (11, 12)) when the target luminance of the second sub-pixel (10) is a maximum luminance of the high luminance section (see Figs. 12A and 12B for a high luminance section; and again, see Page 4, Para. [0068] and [0070]; and Page 9 through Page 10, Para. [0157]-[0161]).
As pertaining to Claim 19, Kawashima discloses (see Fig. 1, Figs. 12A and 12B, and Fig. 15) that a duty ratio of the light emitting control signal (see (DATAW) at (121)) applied to the first pixel driving circuit (see (11, 12)) increases as the target luminance of the first sub-pixel (110) increases when the target luminance of the first sub-pixel (110) is included in the medium luminance section (see Figs. 12A and 12B for a medium luminance section), and
wherein a duty ratio of the light emitting control signal (see (DATAW) at (121)) applied to the second pixel driving circuit (see (11, 12)) increases as the target luminance of the second sub-pixel (110) increases when the target luminance of the second sub-pixel (110) is included in the medium luminance section (see Figs. 12A and 12B for a medium luminance section; again, see Page 4, Para. [0068] and [0070]; and Page 9 through Page 10, Para. [0157]-[0161]).
As pertaining to Claim 20, Kawashima discloses (see Fig. 1, Figs. 12A and 12B, and Fig. 15) that the first pixel driving circuit (see (11, 12)) and the second pixel driving circuit (see (11, 12)) are applied with a same light emitting control signal (i.e., any arbitrary (DATAW) at (121); again, see Page 4, Para. [0068] and [0070]; and Page 9 through Page 10, Para. [0157]-[0161]).
As pertaining to Claim 22, Kawashima discloses (see Fig. 1, Figs. 12A and 12B, and Fig. 15) that at least one of the first light emitting element (110), the second light emitting element (110) and the third light emitting element (110) includes an inorganic light emitting diode (LED; see Page 3, Para. [0062]).
As pertaining to Claim 23, Kawashima discloses (see Fig. 18A) a second optical layer (118) disposed on a light emitting element (110) as a support layer (see Page 12, Para. [0201]).
One of ordinary skill in the art would have recognized, given the combined teachings of Kawashima and Richter, that the second optical layer (118) of Kawashima is necessarily disposed on the second electrode, namely the common cathode of the light emitting element (see (62) in Fig. 9 of Richter corresponding to the cathode of the light emitting element of Kawashima), such that the second optical layer (118) covers at least a portion of the second electrode (again, see (62) in Fig. 9 of Richter corresponding to the cathode of the light emitting element (110) in Fig. 18A of Kawashima), and wherein an upper surface of the second optical layer (118) and an upper surface of the second electrode (again, see (62) in Fig. 9 of Richter corresponding to the cathode of the light emitting element of Kawashima) form a same plane (i.e., a horizontal plane).
Claims 6-7 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Kawashima in view of Richter and further in view of Lopez et al. (hereinafter “Lopez” US 2021 / 0059027).
As pertaining to Claim 6, neither Kawashima nor Richter explicitly discloses that at least one of the first light emitting element and the second light emitting element has a maximum external quantum efficiency (EQE) in the medium luminance section.
However, in the same field of endeavor, Lopez discloses (see Fig. 1A and Fig. 2B, for example) that it was well-known in the art before the effective filing date of the claimed invention to rely upon a combination of pulse-width modulation (PWM) and pulse-amplitude modulation (PAM) modes to provide a maximum (see (Q) in Fig. 1A) external quantum efficiency (EQE) to light emitting elements of a display device (see Page 2, Para. [0026]-[0028]; and Page 3, Para. [0032] and [0036]). It is a goal of Lopez to provide a means of implementing PWM and PAM driving control in a light emitting display device in a manner that improves image performance (see Page 1, Para. [0002]). Further, Lopez suggests that by tailoring PWM and PAM driving techniques based on luminance, such that light emitting elements have a maximum (i.e., Q-Point) external quantum efficiency (EQE), the display device can be driven with optimum operating current, reduced power losses, and increased current range (see Page 2, Para. [0025]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kawashima and Richter with the teachings of Lopez, such that at least one of the first light emitting element and the second light emitting element has a maximum external quantum efficiency (EQE) in the medium luminance section, in order to provide a display device with improved image performance that can be driven with optimum operating current, reduced power losses, and increased current range, as suggested by Lopez.
As pertaining to Claim 7, Lopez discloses (see Fig. 1A and Fig. 2B, for example) that, in the second control mode (i.e., the second current control mode), the magnitude of the data signal is maintained (i.e., the PAM voltage is maintained) to correspond to the maximum (i.e., Q-Point) external quantum efficiency (again, see Page 2, Para. [0026]-[0028]; and Page 3, Para. [0032] and [0036]; and note that Lopez suggests maintaining an amplitude modulation voltage, corresponding to the data signal of Kawashima, in order to correspond to maximum EQE for a light emitting element).
As pertaining to Claim 21, neither Kawashima nor Richter explicitly discloses that in the high luminance section, an average value of the external quantum efficiencies of the second light emitting element and the third light emitting element included in the second pixel driving circuit is greater than the external quantum efficiency of the first light emitting element included in the first pixel driving circuit.
However, in the same field of endeavor, Lopez discloses (see Fig. 1A and Fig. 2B, for example) that it was well-known in the art before the effective filing date of the claimed invention to rely upon a combination of pulse-width modulation (PWM) and pulse-amplitude modulation (PAM) modes to provide a maximum (see (Q) in Fig. 1A) external quantum efficiency (EQE) to light emitting elements of a display device based on an average current of an arbitrary group of pixels (see Page 2, Para. [0026]-[0028]; and Page 3, Para. [0032] and [0036]). It is a goal of Lopez to provide a means of implementing PWM and PAM driving control in a light emitting display device in a manner that improves image performance (see Page 1, Para. [0002]). Further, Lopez suggests that by tailoring PWM and PAM driving techniques based on luminance and an average current of an arbitrary group of pixels, the display device can be driven with optimum operating current, reduced power losses, and increased current range (see Page 2, Para. [0025]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kawashima and Richter with the teachings of Lopez, such that external quantum efficiencies of the light emitting elements of the display device are controlled, in order to provide a display device with improved image performance that can be driven with optimum operating current, reduced power losses, and increased current range, as suggested by Lopez. In this regard, one of ordinary skill in the art would have recognized, given the combined teachings of Kawashima, Richter, and Lopez, that in the high luminance section, an average value of the external quantum efficiencies of the second light emitting element and the third light emitting element included in the second pixel driving circuit is greater than the external quantum efficiency of the first light emitting element included in the first pixel driving circuit, simply as an arbitrary result of controlling the external quantum efficiency (EQE) of light emitting elements of the display device based on an average current of the pixels.
Response to Arguments
Applicant’s arguments with respect to Claims 1-23 have been considered but are moot because the new ground of rejection does not rely on a combination of references applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. The applicant has argued that none of the references relied upon by the examiner in the prior Office Action, namely Kawashima and Lopez, teach or fairly suggest the claimed display device comprising the claimed sub-pixels and further comprising, as newly recited, “a second electrode disposed on the first to fourth light emitting elements, wherein the second light emitting element and the third light emitting element emit light of a same color” and “wherein the second electrode is commonly connected to a plurality of sub-pixels” (see Remarks at Pages 7 and 8). In addition, the applicant has asserted that the teachings of Kawashima do not suggest the claimed “fourth light emitting element that fails to emit light even when driving power is applied” as a “defective element” (see Remarks at Page 8). The applicant has further asserted that the teachings of Kawashima do not provide for the driving of “different control modes” as recited in the claims, and further do not suggest the implementation of redundant light emitting elements of a same color.
Respectfully, the applicant’s argument is moot in view of the combined teachings of Kawashima and Richter, as newly relied upon in the above rejections. That is, the combined teachings of Kawashima and Richter provide for the claimed display device architecture implementing both sub-pixel redundancy and a common cathode configuration. Further, the applicant is again respectfully reminded that the claims must be given their broadest reasonable interpretation in view of the Specification without reading features from the Specification into the claims. In this regard, the examiner respectfully maintains that Kawashima expressly provides for a first pixel driving circuit (see (11, 12) in Fig. 1) that controls the first light emitting element (110) to emit light in a first current control mode (see Figs. 12A and 12B) when a target luminance of the first sub-pixel (10) is included in a high luminance section, and a second pixel driving circuit (see (11, 12) in Fig. 1) that controls the second light emitting element (110) to emit light in a second current control mode (again, see Figs. 12A and 12B) when a target luminance of the second sub-pixel (10) is included in the high luminance section (see Page 4, Para. [0068] and [0070]; and Page 9 through Page 10, Para. [0157]-[0161]). There is nothing recited in the claims to distinguish the claimed “control modes” from the current control modes disclosed by Kawashima.
For at least these reasons, the rejection of Claims 1-23 is maintained.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kawashima et al. (US 2025 / 0061833) discloses (see Figs. 16A and 16B) means for controlling PAM and PWM driving modes based on high, medium, and low luminance sections.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON M MANDEVILLE whose telephone number is (571)270-3136. The examiner can normally be reached Mon - Fri 7:30AM-4:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh Nguyen can be reached at 571-272-7772. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JASON M MANDEVILLE/Primary Examiner, Art Unit 2623
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