DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on June 1, 2026 has been entered.
Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged.
Claim Objections/Recommendations
Claims 2-3, 9-11 and 13-15 are objected to because of the following informalities:
Claim 2, line 4: Insert “of the starting instruction” after “address” for clarity/consistency.
Claim 9, line 2: A comma after “microcontroller” is missing and should be inserted.
Claim 13, last line: Delete the space before the period.
Claims 3, 10-11, and 13-15 are objected to for inheriting the objection of the claims in which they depend on.
Appropriate correction is required.
Examiner makes the following recommendation(s):
Examiner recommends that Applicant either 1) have claim 15 be dependent on claim 10 since claim 15 indicates an “enabling” step that seems to correspond to the “enabling” step in claim 10, or 2) amend claim 15 to indicate where the enabling step comes from.
Claim Interpretation
The following is a quotation of MPEP 2111.04(II):
The broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met. For example, assume a method claim requires step A if a first condition happens and step B if a second condition happens. If the claimed invention may be practiced without either the first or second condition happening, then neither step A or B is required by the broadest reasonable interpretation of the claim. If the claimed invention requires the first condition to occur, then the broadest reasonable interpretation of the claim requires step A. If the claimed invention requires both the first and second conditions to occur, then the broadest reasonable interpretation of the claim requires both steps A and B.
The broadest reasonable interpretation of a system (or apparatus or product) claim having structure that performs a function, which only needs to occur if a condition precedent is met, requires structure for performing the function should the condition occur. The system claim interpretation differs from a method claim interpretation because the claimed structure must be present in the system regardless of whether the condition is met and the function is actually performed.
Claim 9 recites the contingent limitation “at least partially responsive to a write operation by the processor to a control bit of the peripheral” in lines 5-6. The limitation suggests, under BRI, that if the “write operation by the processor to a control bit of the peripheral” does not occur, then the “setting” step in lines 4-5 does not occur. The claim additionally recites the contingent limitation “at least partially responsive to a state of the internal signal of the microcontroller” in lines 8-9. The limitation suggests, under BRI, that if the “internal signal” is not at a specific state, then the “setting” step in lines 7-8 does not occur. In the case that the claim becomes allowable, over the prior art, Applicant is advised to insert “positively occurring” actions within the method claim so that the conditional of the contingent limitations may be satisfied. Note that this does not indicate that the claim is allowable and should not be interpreted in that regard.
Regarding claims 10 and 13, the claims recite limitations which are conditional on the contingent limitation “at least partially responsive to a state of the internal signal of the microcontroller” being satisfied.
Claim 10 recites the contingent limitation “at least partially responsive to the set internal signal” in lines 8-9. The limitation suggests, under BRI, that if the “internal signal” is not “set”, then the “enabling” step in line 8 does not occur. In the case that the claim becomes allowable, over the prior art, and is moved into the independent claim, Applicant is advised to insert “positively occurring” actions within the method claim so that the conditional of the contingent limitation may be satisfied. Note that this does not indicate that the claim is allowable and should not be interpreted in that regard.
Claim 14 recites the contingent limitation “at least partially responsive to the state of the internal signal of the microcontroller or completing execution of code stored at the second memory” in lines 3-4. The limitation suggests, under BRI, that if the “state of the internal signal of the microcontroller” is not at a specific state or “execution of code stored at the second memory” is not completed, then the “setting” step in lines 2-3 does not occur. In the case that the claim becomes allowable, over the prior art, and is moved into the independent claim, Applicant is advised to insert “positively occurring” actions within the method claim so that the conditional of the contingent limitation may be satisfied. Note that this does not indicate that the claim is allowable and should not be interpreted in that regard.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 9-11 and 13-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 9 recites the limitation "the microcontroller system" in lines 4-5. There is insufficient antecedent basis for this limitation in the claim. There was no prior recitation of “a microcontroller system” within the claim. For the sake of examination, Examiner will interpret “an internal signal of the microcontroller system” to be “an internal signal of the microcontroller” in line 4 and “a peripheral of the microcontroller system” to be “a peripheral of the microcontroller” in lines 4-5. These changes also addresses the antecedent basis issues for the element “the internal signal of the microcontroller” in claim 9, lines 8-9, claim 10, line 6, claim 13, lines 1-2, and claim 14, lines 3-4.
Claims 10-11 and 13-15 are rejected for inheriting the rejection of claim 9.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1, 4-6, 8-10, and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Katsuhiko et al. (JPH04145542A, see IDS filed 04/14/2025 (Note: Examiner uses EPO machine translation for mapping)) in view of Wikipedia (“Microcontroller”, see Non-Final Office Action mailed 08/01/2025), Stack Exchange (“p-channel MOSFET switch”), and Foss (US 20200401407 A1).
“Spinning Numbers” (see Final Office Action mailed 12/31/2025) is used as extrinsic evidence to explain how signals are asserted.
Brown “Microcontrollers: Memory-mapped peripherals” (see Final Office Action mailed 12/31/2025) is used as extrinsic evidence to explain the details of how memory-mapped peripherals are modified and that the GPIO pins are memory-mapped peripherals.
Regarding claim 1, Katsuhiko teaches an apparatus, comprising:
a first memory associated with a first address space (Fig. 6 and Page 7, line 10:“The first ROM 31 stores a regular program (first program) including an initialization program”. ROM 31 is a read-only memory with its own address space);
a second memory associated with a second address space (Fig. 6 and Page 7, line 11: “the second ROM 32 stores a debug program (second program)”. ROM 32 is a read-only memory with its own address space, separate from ROM 31), wherein the first address space and the second address space include like addresses (Page 7, lines 10-11: ROM 31 and ROM 32 contain addresses for a first program and a second program. Since memories are separated, they will have similar addresses (i.e., like addresses), which is why ROM 31 and ROM 32 have ROM 33 and ROM 34, respectively, to indicate the starting address of each program);
a processor including circuitry to disable execution of instructions from first memory and enable execution of instructions from second memory at least partially responsive to an internal signal (Fig. 6, Claims 2-4, Page 7, last line and Page 8, lines 1-10 : In response to the access change signal, the memory switching signal is set, which then switches memory for reading to memory group B (i.e., reading from ROM 32 using the address stored in ROM 34) from memory group A (which comprises of ROM 31 and ROM 33). In other words, execution of instructions is disabled from ROM 31 and the execution of instructions from ROM 32 is enabled. The access change signal as the internal signal); and
a peripheral to set the internal signal (Figs. 6 and 7, Page 8, lines 1-13: The AUTO signal is set by an external switch. The AUTO signal input go through the control unit 40a (which can be implemented as a peripheral circuit of the CPU 40) and helps output the access change signal. Therefore, the memories are switched from the first memory to the second memory and vice-versa. The control unit as the peripheral).
Katsuhiko does not teach that the internal signal is part of a microcontroller, that the peripheral is a peripheral of the microcontroller, or that the processor and memories are part of a microcontroller.
However, Wikipedia teaches a microcontroller, consisting of a CPU and memory (“A microcontroller contains one or more CPUs (processor cores) along with memory and programmable input/output peripherals.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Katsuhiko with the teachings of Wikipedia to implement a processing system, which includes elements such as a processor and processor storage, onto a microcontroller. Implementing the processor and its memory onto a microcontroller allows one of ordinary skill to use the microcontroller as part of an embedded system, which would be cost-effective and a reduction in size compared to a microprocessor with various components (3rd paragraph).
Katsuhiko, in view of Wikipedia, does not teach that the peripheral of the microcontroller to set the internal signal at least partially responsive to a write operation by the processor.
Note that a microcontroller comprises of GPIO pins to drive external signals (See Wikipedia, Page 6, under “Other microcontroller features”). Furthermore, note that the AUTO switch of Katsuhiko is part of an electronic system, and therefore, is an electronic switch. Additionally, note that the AUTO switch provides the AUTO reset signal, which helps set the access change signal (See Katsuhiko, page 7, last line to page 8, line 5).
Stack Exchange teaches to drive an electronic switch using a GPIO pin (MCG’s answer: The drawing shows the IRF530 MOSFET switch (i.e., an electronic switch) is set by a GPIO signal).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Katsuhiko, in view of Wikipedia, with the teachings of Stack Exchange to have the GPIO of the microcontroller set the electronic switch. By having the switch be set by GPIO pins, one of ordinary skill would have the flexibility of controlling the switch electrically through the microcontroller instead of having to control the switch through other means, such as a button to set the electronic switch.
However, Katsuhiko, in view of Wikipedia and Stack Exchange, does not teach that the GPIO pin is set in response to a write operation by the processor.
Note that GPIO pins are memory-mapped peripherals (see Brown, Page 3, paragraph 1).
Foss teaches a microcontroller with memory-mapped peripherals, which can be triggered/set by a store instruction (i.e., a write operation) executed by a processor (Fig. 1 and [0020]: Function registers of the peripherals may be memory mapped to the data memory. Memory-mapped peripherals can be modified by using a programming language (such as C) to set a value at a specified address (see Brown pages 1-2, programming-level code setting memory mapped peripherals). When translating to machine code, this could be interpreted as a store instruction (such as a MOV instruction in x86), to store data in memory. The store instruction, which would require a processor to be processed, as the specific instruction).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Katsuhiko, in view of Wikipedia and Stack Exchange, with the teachings of Foss to have the processor execute a store instruction to set the memory-mapped GPIO peripheral, resulting in the AUTO signal being set. By having the processor control and set GPIO pins using an instruction, the processor would have better control over the microcontroller, which may be appreciated in the area of embedded systems.
Regarding claim 4, Katsuhiko, in view of Wikipedia, Stack Exchange, and Foss, teaches the apparatus of claim 1, wherein the peripheral includes a logic circuit to set the internal signal (Katsuhiko, Page 8, lines 3-5: The control unit asserts the “access change” signal. For a signal to be asserted, some type of logic, such as logic gates, would be needed to assert the signal. Therefore, the logic gate(s) to assert the “access change” signal as the logic circuit; see Spinning Numbers, under Assertion and gate symbols)).
Regarding claim 5, Katsuhiko, in view of Wikipedia, Stack Exchange, and Foss, teaches the apparatus of claim 4, wherein the logic circuit includes a control bit (Katsuhiko, Fig. 6, Page 7, last line and Page 8, lines 1-5: The AUTO reset signal as the control bit, which is set by the AUTO switch 39), and a value of the internal signal is responsive to a write operation to the control bit (Katsuhiko, Fig. 6, Page 7, last line and Page 8, lines 1-5: When the AUTO switch is set, the AUTO reset signal is asserted (i.e., written to HIGH or “1”). When the AUTO reset signal is set and the internal signal is already set, the access change signal is asserted (i.e., the value of the signal changes)).
Regarding claim 6, Katsuhiko, in view of Wikipedia, Stack Exchange, and Foss, teaches the apparatus of claim 1, wherein the first memory is a program memory and the second memory is a data memory (Katsuhiko, Fig. 6 and Page 7, lines 10-11: ROM 31 stores a first program. Therefore, ROM 31 is a program memory. The debug program is considered to be data stored in ROM 32. Therefore, ROM 32 is a data memory).
Regarding claim 8, Katsuhiko, in view of Wikipedia, Stack Exchange, and Foss, teaches the apparatus of claim 6, wherein the program memory and the data memory are in physically separate memories (Katsuhiko, Fig. 6: ROM 31 and ROM 32 are physically separated, as seen in the figure).
Regarding claim 9, the claim recites a method similar to the apparatus of claim 1, therefore the claim is mostly rejected on the same premises. Katsuhiko, in view of Wikipedia, Stack Exchange, and Foss, also teaches to set an internal signal of the microcontroller system via a peripheral of the microcontroller system at least partially responsive to a write operation by the processor to a control bit of the peripheral (In the current combination, the GPIO pin that’s connected to the electronic switch (i.e., the AUTO switch) must be written to set the GPIO pin such that the electronic switch is set. The GPIO pin as the control bit of the peripheral).
Claims 10 and 13 are rejected for the same reasons as claim 9 because, as discussed in the “Claim Interpretation” section, the limitation(s) of claims 10 and 13 are contingent and not required.
Regarding claim 10, Katsuhiko, in view of Wikipedia, Stack Exchange, and Foss, teaches the method of claim 9, wherein setting the processor of the microcontroller to execute instructions from the second memory of the microcontroller comprises:
executing a specific instruction fetched from the first memory, the specific instruction designed to trigger memory source change (In the current combination, ROM 31 storing the first program would comprise of a store instruction directed towards the memory-mapped register to be able to trigger the GPIO pin set the AUTO reset signal, which helps set the access change signal. The store instruction as the specific instruction);
setting the internal signal of the microcontroller in response to execution of a specific instruction designed to trigger memory source change (Katsuhiko, Fig. 6, Claims 2-4, Page 7, last line and Page 8, lines 1-10: In the current combination, as a result of setting the AUTO switch and the internal reset signal is set, the processor would set the access change signal, which performs a type of memory source change (using memory group B instead of memory group A)); and
enabling fetching instructions from the second memory at least partially responsive to the set internal signal (Katsuhiko, Fig. 6, Claims 2-4, Page 7, last line and Page 8, lines 1-10 : When the access change signal is set, instructions are fetched from the second program (i.e., from ROM 32)).
Regarding claim 14, Katsuhiko, in view of Wikipedia, Stack Exchange, and Foss, teaches the method of claim 9, comprising:
setting the processor of the microcontroller to execute instructions from the first memory of the microcontroller at least partially responsive to the state of the internal signal of the microcontroller or completing execution of code stored at the second memory (Katsuhiko, Fig. 6, Page 12 (Claims Page 3), lines 4-7, Page 7, last line, and Page 8, lines 1-5: When AUTO is not asserted, the access change signal won’t be asserted. Therefore, instructions are to be fetched from the first program memory); and
executing, by the processor of the microcontroller, instructions fetched from the first memory of the microcontroller (Katsuhiko, Fig. 6 and Page 7, lines 10-13: Instructions fetched from the program memory (ROM 31) into CPU core 40b would be processed and executed).
Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Katsuhiko et al. (JPH04145542A, see IDS filed 04/14/2025 (Note: Examiner uses EPO machine translation for mapping)) in view of Wikipedia (“Microcontroller”, see Non-Final Office Action mailed 08/01/2025), Stack Exchange (“p-channel MOSFET switch”), Foss (US 20200401407 A1), and Shiota et al. (US 20110034124 A1).
Regarding claim 2, Katsuhiko, in view of Wikipedia, Stack Exchange, and Foss, teaches the apparatus of claim 1, comprising:
a ROM to store an address of a starting instruction of the instructions at from the second memory (Katsuhiko, Page 7, lines 12-13: The ROM 34 stores the starting address of the debug program stored in ROM 32),
wherein the processor is to update a program counter of the processor with the address when it enables execution of instructions from the second memory (Katsuhiko, Page 7, lines 12-13: CPU 40 would need a register to hold the address of the debug program stored in ROM 32 in order to read the instructions stored in that memory. The register as the program counter).
Katsuhiko, in view of Wikipedia, Stack Exchange, and Foss, does not teach to use a register writable by the processor to store an address of a starting instruction of the instructions from the second memory.
Note that the ROM 34 stores a start address that’s able to update the program counter register. Therefore, ROM 34 may be a register-sized memory. Furthermore, a register that can be written into can be writable by a processor.
Shiota teaches registers to store a starting address of a program, wherein the registers are writeable registers ([0082]: The first start address register and second start address register both store start addresses of a first program and a second program, respectively. Both registers may have their respective address information changeable)
It would have been obvious to one of ordinary skill in the art before the effective filing date to have substituted the ROM of Katsuhiko, in view of Wikipedia, Stack Exchange, and Foss, with the writable register of Shiota and achieve similar results. A writable register performs the same function as a ROM of storing a starting address of a program, with the added function that the data of the register can be changed. Since the data of a writable register can be changed, it provides one of ordinary skill the flexibility to modify the register to execute the program at a different address. Given that Katsuhiko does not provide a reason as to why ROMs are used to store a starting address, one of ordinary skill would see a writable register as an acceptable alternative to a ROM (See KSR Int'l Co. V. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007)).
Regarding claim 3, Katsuhiko, in view of Wikipedia, Stack Exchange, Foss, and Shiota, teaches the apparatus of claim 2, wherein the register is a memory-mapped register accessible to the processor (Katsuhiko, Fig. 6 and Page 7, lines 12-13: The writable register (currently substituting ROM 34) holds a memory address mapped to the debug memory, hence a memory-mapped register. The read-only register connects to CPU 40 directly. Therefore, the register is accessible to the processor).
Claims 7 is rejected under 35 U.S.C. 103 as being unpatentable over Katsuhiko et al. (JPH04145542A, see IDS filed 04/14/2025 (Note: Examiner uses EPO machine translation for mapping)) in view of Wikipedia (“Microcontroller”, see Non-Final Office Action mailed 08/01/2025), Stack Exchange (“p-channel MOSFET switch”), Foss (US 20200401407 A1), Toshiba (“Flash ROM”, see Final Office Action mailed 12/31/2025), and Tremblay-Munger et al. (US 20150057111 A1)
Regarding claim 7, Katsuhiko, in view of Wikipedia, Stack Exchange, and Foss, teaches the apparatus of claim 6.
Katsuhiko, in view of Wikipedia, Stack Exchange, and Foss, does not teach that the first memory is a Flash memory and the second memory is an SRAM.
Toshiba teaches a Flash ROM, which is a type of Flash memory (see sections “Flash ROM” and “Advantage of Flash ROM”).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Katsuhiko, in view of Wikipedia, Stack Exchange, and Foss, with the teachings of Toshiba to have made the ROM flash memory. Flash ROM provides many uses such as the flexibility of changing/modifying a program within a ROM compared to a standard mask ROM (see section “Advantage of Flash ROM”, paragraph 2).
Katsuhiko, in view of Wikipedia Stack Exchange, Foss, and Toshiba, still does not teach that the second memory is an SRAM.
Note that Katsuhiko indicates that ROM 32 (the second memory) can instead be implemented as RAM instead.
Tremblay-Munger teaches a program memory can be stored in SRAM, which is a type of RAM (see [0104]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Katsuhiko, in view of Wikipedia, Stack Exchange, Foss, and Toshiba, with the teachings of Tremblay-Munger to have implemented the second memory as SRAM. One of ordinary skill would recognize that SRAM provides many benefits such as faster data access speed and low power consumption, compared to other types of memories such as DRAM.
Claims 11 is rejected under 35 U.S.C. 103 as being unpatentable over Katsuhiko et al. (JPH04145542A, see IDS filed 04/14/2025 (Note: Examiner uses EPO machine translation for mapping)) in view of Wikipedia (“Microcontroller”, see Non-Final Office Action mailed 08/01/2025), Stack Exchange (“p-channel MOSFET switch”), Foss (US 20200401407 A1), and WikiChip (“Read-Only (RO) Register”, see Final Office Action mailed 12/31/2025).
Regarding claim 11, Katsuhiko, in view of Wikipedia, Stack Exchange, and Foss, teaches the method of claim 10, comprising:
updating a program counter of the processor with an address of a starting instruction stored at the second memory (Page 7, lines 12-13: CPU 40 would need a register to hold the address of the debug program stored in ROM 32 in order to read the instructions stored in that memory. The register as the program counter), the address of the starting instruction stored at a ROM of the microcontroller (Page 7, lines 12-13: The ROM 34 stores the starting address of the debug program stored in ROM 32).
Katsuhiko, in view of Wikipedia, Stack Exchange, and Foss, does not teach to use a register to store an address of a starting instruction of the instructions from the second memory.
WikiChip teaches a read-only register, which is a type of ROM (Paragraph under “Read-Only (RO) Register).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have substituted the ROM of Katsuhiko, in view of Wikipedia, Stack Exchange, and Foss, with a Read-only register and achieve similar results. A read-only register have the same properties as a read-only memory. One of those properties being that data can’t be written into using common methods of modifying registers. Given that the purpose of the ROM in Katsuhiko is to send the starting address of the debug program to the processor, a read-only register would be just as capable to do its job given the low storage requirement (See KSR Int'l Co. V. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007)).
Claims 13 is rejected under 35 U.S.C. 103 as being unpatentable over Katsuhiko et al. (JPH04145542A, see IDS filed 04/14/2025 (Note: Examiner uses EPO machine translation for mapping)) in view of Wikipedia (“Microcontroller”, see Non-Final Office Action mailed 08/01/2025), Stack Exchange (“p-channel MOSFET switch”), Foss (US 20200401407 A1), and Tokeida et al. (EP 0634715 A1).
Regarding claim 13, Katsuhiko, in view of Wikipedia, Stack Exchange, and Foss, teaches the method of claim 10.
Katsuhiko, in view of Wikipedia, Stack Exchange, and Foss, does not teach that setting the internal signal of the microcontroller comprises: writing to a strobe bit at the peripheral.
Tokeida teaches to write to a strobe bit at a peripheral (Fig. 1 and Col. 1, lines 31-49: CPU 3 transmits a strobe signal 6 to be written to one or more peripheral circuits).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Katsuhiko, in view of Wikipedia, with the teachings of Tokeida to have written to a strobe bit at the peripheral circuit. The purpose of writing a strobe bit at a peripheral is because it allows a system to control the timing of reading/writing data and indicate when data is stable and ready to be read, which one of ordinary skill may appreciate.
Claims 15 is rejected under 35 U.S.C. 103 as being unpatentable over Katsuhiko et al. (JPH04145542A, see IDS filed 04/14/2025 (Note: Examiner uses EPO machine translation for mapping)) in view of Wikipedia (“Microcontroller”, see Non-Final Office Action mailed 08/01/2025), Stack Exchange (“p-channel MOSFET switch”), Foss (US 20200401407 A1), and Hsu et al. (US 20190179568 A1).
Regarding claim 15, Katsuhiko, in view of Wikipedia, Stack Exchange, and Foss, teaches the method of claim 9 wherein enabling fetching instructions from the second memory comprises:
setting a fetch control signal (Fig. 6 and Page 8, lines 1-8: The memory switching signal as the fetch control signal)
Katsuhiko, in view of Wikipedia, Stack Exchange, and Foss, does not teach that enabling fetching instructions from the second memory comprises:
setting a fetch control signal that is utilized as a selection signal by a multiplexer that receives an output of a program memory of the first memory at a first input and an output of a data memory of the second memory at a second input.
Note that Katsuhiko does not explicitly state how the memories are switched, only that the memory switching signal “switches” the memory to read instructions from (see Page 8, lines 5-7).
Hsu teaches a fetch control signal that is utilized as a selection signal by a multiplexer that receives an output of a program memory of the first memory at a first input and an output of a data memory of the second memory at a second input (Fig.13C: The SEL signal is used as a selection signal of MUX 1314. MUX 1314 receives instruction output from ROM 1304 and instruction output from RAM 1308. The instruction output of ROM as the output of a program memory and first input of the MUX. The instruction output of RAM as the output of the data memory and second input of the MUX).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Katsuhiko, in view of Wikipedia, Stack Exchange, and Foss, with the teachings of Hsu to have selected the memory output using a MUX, utilizing the memory switch signal as the selection signal. One of ordinary skill would recognize that MUXs are a popular logic circuit to use for the selection of data to pass through as it consolidates multiple data lines into a singular data line, reducing wiring and complexity of a system.
Response to Arguments
Applicant's arguments, see page 7, paragraph 4 to page 9, paragraph 3, filed June 1 2026, with respect to claims 1, 4-6, 8, 9, and 14 under 35 U.S.C. 103 have been fully considered and are mostly persuasive.
Regarding argument on page 8, paragraph 2, Applicant argues that there is no reason to combine Katsuhiko and Wikipedia as there is no motivation to combine Katsuhiko onto a microcontroller and that the combination is reconstructible only with the present application as a road map, which is impermissible.
Examiner respectfully disagrees with this argument. In response to Applicant’s argument that there is no teaching, suggestion, or motivation to combine the references, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). As stated before, Examiner found the motivation to combine within “Microcontroller” as they state the benefits of implementing a processing system (such as the one in Katsuhiko) on a microcontroller over further modifying a processing system with multiple components to be used in applications such as using them in embedded systems. Applicant’s motivation of the invention may differ from Examiner’s motivation for the combination of the prior art, but both motivations may produce the same invention and/or end product. Furthermore, in response to Applicant's argument that the Examiner's conclusion of obviousness is based upon improper hindsight reasoning, it must be recognized that any judgment on obviousness is in a sense necessarily a reconstruction based upon hindsight reasoning. But so long as it takes into account only knowledge which was within the level of ordinary skill at the time the claimed invention was made, and does not include knowledge gleaned only from the applicant's disclosure, such a reconstruction is proper. See In re McLaughlin, 443 F.2d 1392, 170 USPQ 209 (CCPA 1971). Therefore, the remarks regarding lack of motivation to combine is considered not persuasive.
Regarding argument on page 8, paragraph 2, Applicant argues that the combination between Katsuhiko and Wikipedia does not show that the switching signal becomes responsive to a write by the processor.
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., the switching signal becomes responsive to a write by the processor) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Therefore, the remarks regarding that the combination does not show the exact feature is considered not persuasive.
Although some of Applicant’s arguments are not persuasive, the rejection of claims 1, 4-6, 8, 9, and 14 under 35 U.S.C. 103 are withdrawn due to amendments to the claims and arguments following these amendments (page 8, paragraph 3 to page 9, paragraph 3). However, upon further consideration, a new ground(s) of rejection is made in view newly found prior art reference(s). See 103 rejections above.
Applicant's arguments, see page 9, paragraph 4 to Page 10, paragraph 2, filed June 1 2026, with respect to claims 2-3 under 35 U.S.C. 103 have been fully considered and are mostly persuasive.
Regarding argument on page 9, paragraph 5 to page 10, paragraph 1, Applicant argues that the combination between Katsuhiko and Wikipedia does not show that the register mapped in the claims cannot be written into as per the recited register of the disclosure.
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., the register can be written into by the processor) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Therefore, the remarks regarding that the combination does not show the exact feature is considered not persuasive.
Although some of Applicant’s arguments are not persuasive, the rejection of claims 2-3 under 35 U.S.C. 103 are withdrawn due to amendments to the claims and arguments following these amendments (page 10, paragraph 2). However, upon further consideration, a new ground(s) of rejection is made in view newly found prior art reference(s). See 103 rejections above.
Applicant's arguments, see page 10, paragraphs 1-2, filed June 1 2026, with respect to claim 10 under 35 U.S.C. 103 have been fully considered and are mostly persuasive.
Regarding argument on page 10, paragraph 2, Applicant argues that the combination between Katsuhiko, in view of Wikipedia, and Foss does not “describe a peripheral whose output gates instruction fetch between two distinct instruction-memory sources during execution”.
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., “a peripheral whose output gates instruction fetch between two distinct instruction-memory sources during execution”) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Therefore, the remarks regarding that the combination does not show the exact feature is considered not persuasive.
Although some of Applicant’s arguments are not persuasive, the rejection of claims 10 under 35 U.S.C. 103 are withdrawn due to amendments to the claims and arguments following these amendments (page 11, paragraph 2). However, upon further consideration, a new ground(s) of rejection is made in view newly found prior art reference(s). See 103 rejections above.
Applicant's arguments, see page 11, paragraphs 1-2, filed June 1 2026, with respect to claim 10 rejected under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of newly found prior art reference(s). See new 103 rejections above.
Applicant's arguments, see page 9, paragraph 4 to Page 10, paragraph 2, filed June 1 2026, with respect to claim 11 under 35 U.S.C. 103 have been fully considered and are mostly persuasive.
Regarding argument on page 9, paragraph 5 to page 10, paragraph 1, Applicant argues that the reasons given to claim 2 that claim 11 is allowable.
Examiner respectfully disagrees with this argument. Applicant did not amend the claim similar to that of claim 2. Hence, the arguments made for claim 2 cannot be applied to claim 11. Therefore, the remarks regarding the reasons that claim 11 is allowable for the same reasons as claim 2 is considered not persuasive.
Although some of Applicant’s arguments are not persuasive, the rejection of claims 11 under 35 U.S.C. 103 are withdrawn due to amendments to the claim it depends on and their arguments following these amendments (see above). However, upon further consideration, a new ground(s) of rejection is made in view newly found prior art reference(s). See 103 rejections above.
Applicant's arguments, see page 11, paragraphs 5-6, filed June 1 2026, with respect to claim 13 rejected under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of newly found prior art reference(s). See new 103 rejections above.
Applicant's arguments, see page 12, paragraphs 1-2, filed June 1 2026, with respect to claim 15 rejected under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of newly found prior art reference(s). See new 103 rejections above.
Conclusion
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/E.A./Examiner, Art Unit 2183
/David J. Huisman/Primary Examiner, Art Unit 2183
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