DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1, 4-6, 8-9, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Katsuhiko et al. (JPH04145542A, see IDS filed 04/14/2025 (Note: Examiner uses EPO machine translation for mapping)) in view of Wikipedia (“Microcontroller”, see Non-Final Office Action mailed 08/01/2025).
“Spinning Numbers” is used as extrinsic evidence to explain how signals are asserted.
Regarding claim 1, Katsuhiko teaches an apparatus, comprising:
a first memory associated with a first address space (Fig. 6 and Page 7, line 10:“The first ROM 31 stores a regular program (first program) including an initialization program”. ROM 31 is a read-only memory with its own address space);
a second memory associated with a second address space (Fig. 6 and Page 7, line 11: “the second ROM 32 stores a debug program (second program)”. ROM 32 is a read-only memory with its own address space, separate from ROM 31), wherein the first address space and the second address space include like addresses (Page 7, lines 10-11: ROM 31 and ROM 32 contain addresses for a first program and a second program. Since memories are separated, they will have similar addresses (i.e., like addresses), which is why ROM 31 and ROM 32 have ROM 33 and ROM 34, respectively, to indicate the starting address of each program);
a processor including circuitry to disable execution of instructions from first memory and enable execution of instructions from second memory at least partially responsive to an internal signal (Fig. 6, Claims 2-4, Page 7, last line and Page 8, lines 1-10 : The memory switching signal is put into a negated state to indicated a reset vector fetch from a first memory (i.e., fetch the starting address for ROM 31 when the AUTO reset signal is low). The memory switching signal is put into an asserted state to indicated a reset vector fetch from a second memory (i.e., fetch the starting address for ROM 32 when the AUTO reset signal is high). The “access change” signal set by the AUTO signal as the internal signal); and
a peripheral (Figs. 6 and 7, Page 8, lines 1-13: The AUTO signal is set by an external switch. The AUTO signal input go through the control unit 40a (which can be implemented as a peripheral circuit of the CPU 40) and outputs an “access change” therefore the memories are switched from the first memory to the second memory and vice-versa. The control unit as the peripheral).
Katsuhiko does not teach that the internal signal is part of a microcontroller, that the peripheral is a peripheral of the microcontroller, or that the processor and memories are part of a microcontroller.
However, Wikipedia teaches a microcontroller, consisting of a CPU and memory (“A microcontroller contains one or more CPUs (processor cores) along with memory and programmable input/output peripherals.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Katsuhiko with the teachings of Wikipedia to implement a processor and processor storage onto a microcontroller. Implementing the processor and its memory onto a microcontroller allows one of ordinary skill to use the microcontroller as part of an embedded system, which would be cost-effective and a reduction in size compared to a microprocessor with various components (3rd paragraph).
Regarding claim 4, Katsuhiko, in view of Wikipedia, teaches the apparatus of claim 1, wherein the peripheral includes a logic circuit to set the internal signal (Page 8, lines 3-5: The control unit asserts the “access change” signal. For a signal to be asserted, some type of logic, such as logic gates, would be needed to assert the signal. Therefore, the logic gate(s) to assert the “access change” signal as the logic circuit; see Spinning Numbers in pertinent art section)).
Regarding claim 5, Katsuhiko, in view of Wikipedia, teaches the apparatus of claim 4, wherein the logic circuit includes a control bit (Fig. 6, Page 7, last line and Page 8, lines 1-5: The AUTO reset signal as the control bit, which is set by the AUTO switch 39), and a value of the internal signal is responsive to a write operation to the control bit (Fig. 6, Page 7, last line and Page 8, lines 1-5: When the AUTO switch is set, the AUTO reset signal is asserted (i.e., written to HIGH or “1”). When the AUTO reset signal is set, the access change signal is asserted (i.e., the value of the signal changes)).
Regarding claim 6, Katsuhiko, in view of Wikipedia, teaches the apparatus of claim 1, wherein the first memory is a program memory and the second memory is a data memory (Fig. 6 and Page 7, lines 10-11: ROM 31 stores a first program. Therefore, ROM 31 is a program memory. The debug program is considered to be data stored in ROM 32. Therefore, ROM 32 is a data memory).
Regarding claim 8, Katsuhiko, in view of Wikipedia, teaches the apparatus of claim 6, wherein the program memory and the data memory are in physically separate memories (Fig. 6: ROM 31 and ROM 32 are physically separated, as seen in the figure).
Regarding claim 9, the claim recites a method similar to the apparatus of claim 1, therefore the claim is rejected on the same premises.
Regarding claim 14, Katsuhiko, in view of Wikipedia, teaches the method of claim 9, comprising:
setting the processor of the microcontroller to execute instructions from the first memory of the microcontroller at least partially responsive to the state of the internal signal of the microcontroller or completing execution of code stored at the second memory (Katsuhiko, Fig. 6, Page 12 (Claims Page 3), lines 4-7, Page 7, last line, and Page 8, lines 1-5: When AUTO is not asserted, instructions are to be fetched from the program memory); and
executing, by the processor of the microcontroller, instructions fetched from the first memory of the microcontroller (Katsuhiko, Fig. 6 and Page 7, lines 10-13: Instructions fetched from the program memory (ROM 31) into CPU core 40b would be processed and executed).
Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Katsuhiko et al. (JPH04145542A, see IDS filed 04/14/2025 (Note: Examiner uses EPO machine translation for mapping)) in view of Wikipedia (“Microcontroller”, see Non-Final Office Action mailed 08/01/2025) and WikiChip (“Read-Only (RO) Register”).
Regarding claim 2, Katsuhiko teaches the apparatus of claim 1, comprising:
a ROM to store an address of a starting instruction of the instructions at from the second memory (Page 7, lines 12-13: The ROM 34 stores the starting address of the debug program stored in ROM 32),
wherein the processor is to update a program counter of the processor with the address when it enables execution of instructions from the second memory (Page 7, lines 12-13: CPU 40 would need a register to hold the address of the debug program stored in ROM 32 in order to read the instructions stored in that memory. The register as the program counter).
Katsuhiko, in view of Wikipedia, does not teach to use a register to store an address of a starting instruction of the instructions from the second memory.
WikiChip teaches the use of a read-only register, which is a type of ROM (Paragraph under “Read-Only (RO) Register).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have substituted the ROM of Katsuhiko, in view of Wikipedia, with the Read-only register and achieve similar results. A read-only register have the same properties as a read-only memory. One of those properties being that data can’t be written into using common methods of modifying registers. Given that the purpose of the ROM in Katsuhiko is to send the starting address of the debug program to the processor, a read-only register would be just as capable to do its job given the low storage requirement (See KSR Int'l Co. V. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007)).
Regarding claim 3, Katsuhiko, in view of Wikipedia and WikiChip, teaches the apparatus of claim 2, wherein the register is a memory-mapped register accessible to the processor (Fig. 6 and Page 7, lines 12-13: The read-only register (currently substituting ROM 34) holds a memory address mapped to the debug memory, hence a memory-mapped register. The read-only register connects to CPU 40 directly. Therefore, the register is accessible to the processor).
Claims 7 is rejected under 35 U.S.C. 103 as being unpatentable over Katsuhiko et al. (JPH04145542A, see IDS filed 04/14/2025 (Note: Examiner uses EPO machine translation for mapping)) in view of Wikipedia (“Microcontroller”, see Non-Final Office Action mailed 08/01/2025), Toshiba (“Flash ROM”), and Tremblay-Munger et al. (US 20150057111 A1)
Regarding claim 7, Katsuhiko, in view of Wikipedia, teaches the apparatus of claim 6.
Katsuhiko, in view of Wikipedia, does not teach that the first memory is a Flash memory and the second memory is an SRAM.
Toshiba teaches a Flash ROM, which is a type of Flash memory (see sections “Flash ROM” and “Advantage of Flash ROM”).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Katsuhiko, in view of Wikipedia, with the teachings of Toshiba to have made the ROM flash memory. Flash ROM provides many uses
Katsuhiko, in view of Wikipedia and Toshiba, still does not teach that the second memory is an SRAM.
Note that Katsuhiko indicates that ROM 32 (the second memory) can instead be implemented as RAM instead.
Tremblay-Munger teaches a program memory can be stored in SRAM, which is a type of RAM (see [0104]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Katsuhiko, in view of Wikipedia and Toshiba, with the teachings of Tremblay-Munger to have implemented the second memory as SRAM. One of ordinary skill would recognize that SRAM provides many benefits such as faster data access speed and low power consumption, compared to other types of memories such as DRAM.
Claims 10 is rejected under 35 U.S.C. 103 as being unpatentable over Katsuhiko et al. (JPH04145542A, see IDS filed 04/14/2025 (Note: Examiner uses EPO machine translation for mapping)) in view of Wikipedia (“Microcontroller”, see Non-Final Office Action mailed 08/01/2025) and Foss (US 20200401407 A1).
Brown (“Microcontrollers: Memory-mapped peripherals”) is used as extrinsic evidence to explain the details of how memory-mapped peripherals are modified.
Regarding claim 10, Katsuhiko, in view of Wikipedia, teaches the method of claim 9.
Katsuhiko, in view of Wikipedia, does not teach setting the processor of the microcontroller to execute instructions from the second memory of the microcontroller comprises: executing a specific instruction fetched from the first memory, the specific instruction designed to trigger memory source change; setting the internal signal of the microcontroller in response to execution of a specific instruction designed to trigger memory source change; and enabling fetching instructions from the second memory at least partially responsive to the set internal signal.
Note that the peripheral circuit in Katsuhiko initializes the process of fetching instructions from the second memory (see claim 1 mapping). However, they do not explicitly teach that the peripheral can be set by a specific instruction.
Foss teaches a microcontroller with memory-mapped peripherals, which can be triggered/set by an instruction (Fig. 1 and [0020]: Function registers of the peripherals may be memory mapped to the data memory. Memory-mapped peripherals can be modified by using a programming language (such as C) to set a value at a specified address. When translating to machine code, this could be interpreted as a store instruction (such as a MOV instruction in x86), to store data in memory. The store instruction as the specific instruction; see Brown in pertinent art section).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Katsuhiko, in view of Wikipedia, with the teachings of Foss to have made the peripheral circuit be memory-mapped. Having peripherals be memory mapped allows a processor to directly control the peripherals instead of using external devices/circuits to activate these peripherals, providing one of ordinary skill the flexibility to decide when/how to trigger the peripherals.
Claims 11 is rejected under 35 U.S.C. 103 as being unpatentable over Katsuhiko et al. (JPH04145542A, see IDS filed 04/14/2025 (Note: Examiner uses EPO machine translation for mapping)) in view of Wikipedia (“Microcontroller”, see Non-Final Office Action mailed 08/01/2025), Foss (US 20200401407 A1), and WikiChip (“Read-Only (RO) Register”).
Regarding claim 11, Katsuhiko, in view of Wikipedia and Foss, teaches the method of claim 10, comprising:
updating a program counter of the processor with an address of a starting instruction stored at the second memory (Page 7, lines 12-13: CPU 40 would need a register to hold the address of the debug program stored in ROM 32 in order to read the instructions stored in that memory. The register as the program counter), the address of the starting instruction stored at a ROM of the microcontroller (Page 7, lines 12-13: The ROM 34 stores the starting address of the debug program stored in ROM 32).
Katsuhiko, in view of Wikipedia and Foss, does not teach to use a register to store an address of a starting instruction of the instructions from the second memory.
WikiChip teaches a read-only register, which is a type of ROM (Paragraph under “Read-Only (RO) Register).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have substituted the ROM of Katsuhiko, in view of Wikipedia and Foss, with a Read-only register and achieve similar results. A read-only register have the same properties as a read-only memory. One of those properties being that data can’t be written into using common methods of modifying registers. Given that the purpose of the ROM in Katsuhiko is to send the starting address of the debug program to the processor, a read-only register would be just as capable to do its job given the low storage requirement (See KSR Int'l Co. V. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007)).
Claims 13 is rejected under 35 U.S.C. 103 as being unpatentable over Katsuhiko et al. (JPH04145542A, see IDS filed 04/14/2025 (Note: Examiner uses EPO machine translation for mapping)) in view of Wikipedia (“Microcontroller”, see Non-Final Office Action mailed 08/01/2025), Foss (US 20200401407 A1), and Tokeida et al. (EP 0634715 A1).
Regarding claim 13, Katsuhiko, in view of Wikipedia and Foss, teaches the method of claim 10.
Katsuhiko, in view of Wikipedia and Foss, does not teach that setting the internal signal of the microcontroller comprises: writing to a strobe bit at the peripheral.
Tokeida teaches to write to a strobe bit at a peripheral (Fig. 1 and Col. 1, lines 31-49: CPU 3 transmits a strobe signal 6 to be written to one or more peripheral circuits).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Katsuhiko, in view of Wikipedia, with the teachings of Tokeida to have written to a strobe bit at a peripheral. The purpose of writing a strobe bit at a peripheral is because it would allow a system to control the timing of reading/writing data and indicate when data is stable and ready to be read, which one of ordinary skill may appreciate.
Claims 15 is rejected under 35 U.S.C. 103 as being unpatentable over Katsuhiko et al. (JPH04145542A, see IDS filed 04/14/2025 (Note: Examiner uses EPO machine translation for mapping)) in view of Wikipedia (“Microcontroller”, see Non-Final Office Action mailed 08/01/2025), Foss (US 20200401407 A1), and Hsu et al. (US 20190179568 A1, see Non-Final Office Action mailed 08/01/2025).
Regarding claim 15, Katsuhiko, in view of Wikipedia, teaches the method of claim 9 wherein enabling fetching instructions from the second memory comprises:
setting a fetch control signal (Fig. 6 and Page 8, lines 1-8: The memory switching signal as the fetch control signal)
Katsuhiko, in view of Wikipedia, does not teach that enabling fetching instructions from the second memory comprises:
setting a fetch control signal that is utilized as a selection signal by a multiplexer that receives an output of a program memory of the first memory at a first input and an output of a data memory of the second memory at a second input.
Note that Katsuhiko does not explicitly state how the memories are switched, only that the memory switching signal “switches” the memory to read instructions from (see Page 8, lines 5-7).
Hsu teaches a fetch control signal that is utilized as a selection signal by a multiplexer that receives an output of a program memory of the first memory at a first input and an output of a data memory of the second memory at a second input (Fig.13C: The SEL signal is used as a selection signal of MUX 1314. MUX 1314 receives instruction output from ROM 1304 and instruction output from RAM 1308. The instruction output of ROM as the output of a program memory and first input of the MUX. The instruction output of RAM as the output of the data memory and second input of the MUX).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Katsuhiko, in view of Wikipedia, with the teachings of Hsu to have selected the memory output using a MUX, utilizing the memory switch signal as the selection signal. One of ordinary skill would recognize that MUXs are a popular logic circuit to use for the selection of data to pass through as it consolidates multiple data lines into a singular data line, reducing wiring and complexity of a system.
Response to Arguments
Applicant’s amendments, filed November 3 2025, with respect to the specification objections raised by the Examiner have been addressed. Therefore, the objections of the drawings has been withdrawn.
Applicant’s amendments, filed November 3 2025, with respect to the abstract objections raised by the Examiner have been addressed. Therefore, the objections of the abstract has been withdrawn.
Applicant’s amendments, filed November 3 2025, with respect to the drawing objections raised by the Examiner have been addressed. Therefore, the objections of the drawings has been withdrawn.
Applicant’s amendments, filed November 3 2025, with respect to the 35 U.S.C. 112(a)/(b) rejections raised by the Examiner addresses the rejections. Therefore, the 112(a)/(b) rejections of claims 1-15 has been withdrawn.
Applicant’s arguments, see Page 12, second-to-last line to Page 13, last line, filed November 3 2025, with respect to claims 1-2, 4-6, 8-10, and 12-15 rejected under 35 U.S.C. 102(a)(1)/(a)(2) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of a different interpretation of a previously applied reference and/or newly found prior art reference(s) for claims 2, 4-6, 8, 10, and 13-15. See 103 rejections above.
Applicant’s arguments, see Page 14, first line to Page 13, line 9, filed November 3 2025, with respect to claims 3 and 11 rejected under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of a different interpretation of a previously applied reference and/or newly found prior art reference(s) for claims 3 and 11. See new 103 rejections above.
Applicant’s arguments, see Page 14, line 11 to Page 13, line 23, filed November 3 2025, with respect to claims 7 rejected under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of a different interpretation of a previously applied reference and/or newly found prior art reference(s) for claim 7. See new 103 rejections above.
Applicant's arguments, see Page 14, fourth-to-last line to Page 15, last line, filed November 3 2025, with respect to claims 1 and 9 under 35 U.S.C. 103 have been fully considered but they are not persuasive.
Regarding argument on Page 15, line 8 to line 15, Applicant argues that there is no reason to combine Katsuhiko and “Microcontroller” as there is no motivation to “adapt reset loading to runtime peripheral signal, lacking reasonable success without hindsight”.
Examiner respectfully disagrees with this argument. In response to Applicant’s argument that there is no teaching, suggestion, or motivation to combine the references, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). In this case, Examiner found the motivation to combine within “Microcontroller” as they state the benefits of implementing the processor (such as the one in Katsuhiko) on a microcontroller over further modifying a processor with multiple components to be used in applications such as using them in embedded systems. Applicant’s motivation of the invention may differ from Examiner’s motivation for the combination of the prior art, but both motivations may produce the same invention and/or end product. Therefore, the remarks regarding lack of motivation to combine is considered not persuasive.
Although Applicant’s arguments are not persuasive, the rejection of claims 1 and 9 under 35 U.S.C. 103 are withdrawn due to amendments to the claims. However, upon further consideration, a new ground(s) of rejection is made in view of a different interpretation of the previously applied reference(s). See 103 rejection above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
“Assertion”: This website teaches how signals are to be asserted using logic.
“Microcontrollers: Memory-mapped peripherals”: Brown teaches the basics of triggering memory-mapped peripherals.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/E.A./Examiner, Art Unit 2183
/JYOTI MEHTA/ Supervisory Patent Examiner, Art Unit 2183