DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 21-40 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12034440. Although the claims at issue are not identical, they are not patentably distinct from each other because the patent claims and application claims recite similar limitations, i.e., claims 1 and 4 of the patent claims recite a first interface, a circuit comprises resistor-capacitor parallel arrangement, one or more current source, an operational amplifier; and a second interface connected as recited in claim 21 of the application claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 21-40 is/are rejected under 35 U.S.C. 103 as being unpatentable over Aga et al. (US 7589649) in view of Hedberg (US 6654462).
As to claim 21, Aga et al.’s figure 6 shows an apparatus comprising: a first interface (531 or output of 531) comprising circuitry configured to receive an input signal; a circuit (530) coupled to the first interface and configured to generate an output signal as a baseline wander corrected version of the input signal. The figure fails to show that the circuit comprises a resistor-capacitor parallel arrangement. However, Hedberg’s figures 1-3 show a similar circuit that comprises capacitor Ca coupled in parallel with resistor Ra in order to compensate the influence of parasitic capacitance (col. 2, lines 59-62). Therefore, it would have been obvious to one having ordinary skill in the art to add capacitor couped in parallel with Aga et al.’s resistor 532 for the purpose of compensating parasitic capacitance. The modified Aga et al.’s figure further shows one or more current sources (534a and 535a) connected to a first end of the resistor-capacitor parallel arrangement; and an operational amplifier (in 580. Operational amplifier used as a comparator is well known in the art. It would have been obvious to one having ordinary skill in the art to use operational amplifier for Aga et al.’s comparator in comparing circuit 580, (see figures 4A-4D) for the purpose of providing more precise compared signal) configured to drive the one or more current sources; and a second interface (at the input of 580) configured to receive the output signal from the circuit.
As to claim 22, the modified Aga et al.’s figure 6 fails to show a second similar circuit. However, Hedberg’s figures show differential signal paths each comprising a resistor and first and second current sources, and first and second current sinks. Furthermore, it has been held that “mere duplication of parts has no patentable significance unless a new and unexpected result is produced”, MPEP 2144.04, VI, B. Therefore, it would have been obvious to one having ordinary skill in the art to duplicating the modified Aga et al.’s figure 6 for the purpose of providing differential signals. Thus, the modified circuit figure 6 shows a first feed-forward resistor (532) configured to receive, on the first end, the input signal from a first transmission line; and a second feed-forward resistor (the duplicated 532) configured to receive, on a second end, another input signal from a second transmission line, the resistor-capacitor parallel arrangement comprises the first feed-forward resistor.
As to claim 23, since voltages at the ends of the resistor are dependent of the selected current values generated by the shown current sources, selecting a first common mode voltage at the first end of the first feed-forward resistor and the second end of the second feed- forward resistor to be less than a second common mode voltage at a third end of the first feed-forward resistor and a fourth end of the second feed-forward resistor is seen as an obvious design preference to ensure optimum performance.
As to claim 24, the modified Aga et al.’s figure shows a given current source (534b) connected to the third end of the first feed-forward resistor; and a current sink (535a) connected to the first end of the first feed-forward resistor, wherein each of the given current source and the current sink is configured to shift a direct current level of the input signal from the first transmission line.
As to claim 25, since voltages at the ends of the resistor are dependent of the selected current values generated by the shown current sources, selecting a first common mode voltage at the first end of the first feed-forward resistor and the second end of the second feed- forward resistor to be greater than a second common mode voltage at a third end of the first feed-forward resistor and a fourth end of the second feed-forward resistor is seen as an obvious design preference to ensure optimum performance.
As to claim 26, the modified Aga et al.’s figure shows a given current source (534a) of the one or more current sources connected to the first end of the first feed-forward resistor; and a current sink (535b) connected to the third end of the first feed-forward resistor, wherein each of the given current source and the current sink is configured to shift a direct current level of the input signal from the first transmission line.
As to claim 27, the modified Aga et al.’s figure shows that each of the given current source and the current sink is configured to be driven by a control signal generated by the operational amplifier configured to receive a desired common mode reference voltage and a sensed common mode voltage at the third end of the first feed-forward resistor and the fourth end of the second feed-forward resistor (see Hadberg’s figure 3).
Claims 28-34 recite similar limitations in claims above. Therefore, they are rejected for the same reasons.
As to claims 35-40, the modified Aga et al.’s figure shows a receiver comprising elements connected as claimed.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANH-QUAN TRA whose telephone number is (571)272-1755. The examiner can normally be reached Mon-Fri from 8:00 A.M.-5:00 P.M.
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/QUAN TRA/
Primary Examiner
Art Unit 2842