Prosecution Insights
Last updated: May 29, 2026
Application No. 18/763,572

COMBINATION SCHEME FOR BASELINE WANDER, DIRECT CURRENT LEVEL SHIFTING, AND RECEIVER LINEAR EQUALIZATION FOR HIGH SPEED LINKS

Non-Final OA §103
Filed
Jul 03, 2024
Priority
Nov 04, 2021 — provisional 63/275,852 +1 more
Examiner
TRA, ANH QUAN
Art Unit
2843
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Advanced Micro Devices, Inc.
OA Round
2 (Non-Final)
73%
Grant Probability
Favorable
2-3
OA Rounds
6m
Est. Remaining
78%
With Interview

Examiner Intelligence

Grants 73% — above average
73%
Career Allowance Rate
811 granted / 1115 resolved
+4.7% vs TC avg
Moderate +6% lift
Without
With
+5.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
28 currently pending
Career history
1150
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
87.1%
+47.1% vs TC avg
§102
7.3%
-32.7% vs TC avg
§112
2.0%
-38.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1115 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claims 21-40 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12034440. Although the claims at issue are not identical, they are not patentably distinct from each other because the patent claims and application claims recite similar limitations, i.e., claims 1 and 4 of the patent claims recite a first interface, a circuit comprises resistor-capacitor parallel arrangement, one or more current source, an operational amplifier; and a second interface connected as recited in claim 21 of the application claims. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 21-26 and 28-40 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hedberg (US 6654462). As to claim 21, Hedberg’s figure 3 shows an apparatus comprising: a first interface (amplifier D or outputs of amplifier D) comprising circuitry configured to receive an input signal; a circuit (Ra and Rb) coupled to the first interface and configured to generate an output signal as a baseline wander corrected version of the input signal, wherein the circuit comprises a resistor-capacitor parallel arrangement (figures 1-2 show that capacitor Ca/Cb is coupled in parallel with resistor Ra/Ra in order to compensate the influence of parasitic capacitance (col. 2, lines 59-62). Therefore, it would have been obvious to one having ordinary skill in the art to add capacitor couped in parallel with resistors Ra and Rb in figure 3 for the purpose of compensating parasitic capacitance); one or more current sources (T1t-T4t) connected to a first end of the resistor-capacitor parallel arrangement; and an operational amplifier (At1 and/or At2, col. 6, lines 10-17) configured to generate a control signal drive the one or more current sources based on a sensed common mode voltage (ND3t, col. 6, lines 39-42); and a second interface (at the inputs of amplifier A) configured to receive the output signal from the circuit. As to claim 22, Hedberg’s figures show a first feed-forward resistor (Ra) configured to receive, on the first end, the input signal from a first transmission line; and a second feed-forward resistor (Rb) configured to receive, on a second end, another input signal from a second transmission line, the resistor-capacitor parallel arrangement comprises the first feed-forward resistor. As to claim 23, since voltages at the ends of the resistor are dependent on the selected values of reference voltages Vreflt, Verfht, Vreflr and Vrefhr, selecting a first common mode voltage at the first end of the first feed-forward resistor and the second end of the second feed- forward resistor to be less than a second common mode voltage at a third end of the first feed-forward resistor and a fourth end of the second feed-forward resistor is seen as an obvious design preference to ensure optimum performance. As to claim 24, figure 3 shows a given current source (T1r) connected to the third end of the first feed-forward resistor; and a current sink (T3t) connected to the first end of the first feed-forward resistor, wherein each of the given current source and the current sink is configured to shift a direct current level of the input signal from the first transmission line. As to claim 25, since voltages at the ends of the resistor are dependent on the selected reference voltages Vreflt, Verfht, Vreflr and Vrefhr, selecting a first common mode voltage at the first end of the first feed-forward resistor and the second end of the second feed- forward resistor to be greater than a second common mode voltage at a third end of the first feed-forward resistor and a fourth end of the second feed-forward resistor is seen as an obvious design preference to ensure optimum performance. As to claim 26, figure 3 shows a given current source (T1t) of the one or more current sources connected to the first end of the first feed-forward resistor; and a current sink (T3r) connected to the third end of the first feed-forward resistor, wherein each of the given current source and the current sink is configured to shift a direct current level of the input signal from the first transmission line. Claims 28-34 recite similar limitations in claims above. Therefore, they are rejected for the same reasons. As to claims 35-40, the modified Hedberg’s figure 3 shows a receiver comprising elements connected as claimed. Claim(s) 27-40 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hedberg (US 6654462) in view of Aga et al. (US 7589649). As to claim 27, the modified Hedberg’s figure 3 shows a first feed-forward resistor (Ra) configured to receive, at a first end, the input signal from a first transmission line; and a second feed-forward resistor (Rb) configured to receive, at a second end, another input signal from a second transmission line; wherein the resistor-capacitor parallel arrangement comprises the first feed-forward resistor. The figure fails to show that the operational amplifier is configured to receive the sensed common mode voltage at a third end of the first feed-forward resistor and a fourth end of the second feed-forward resistor, and to receive the reference voltage as a desired common mode reference voltage. However, Aga et al.’s figure 6 shows a similar device that comprises a single comparing circuitry 580 and 570 coupled to the third end of resistor 532 to controls plurality of current sources coupled to the two ends of resistors 532. It would have been obvious to one having ordinary skill in the art to Hedberg’s receiver comparing circuit (A1r, A2r, R1r and R2r), instead of transmitter comparing circuit, to controls the transmitter current sources (T1t-T4t) for the purpose of saving cost and achieving optimum performance. Claims 28-34 recite similar limitations in claims above. Therefore, they are rejected for the same reasons. As to claims 35-40, the modified Hedberg’s figure 3 shows a receiver comprising elements connected as claimed. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANH-QUAN TRA whose telephone number is (571)272-1755. The examiner can normally be reached Mon-Fri from 8:00 A.M.-5:00 P.M. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Lindgren Baltzell can be reached at 571-272-5918. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /QUAN TRA/ Primary Examiner Art Unit 2843
Read full office action

Prosecution Timeline

Jul 03, 2024
Application Filed
Feb 06, 2026
Non-Final Rejection mailed — §103
Apr 27, 2026
Response Filed
May 07, 2026
Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

2-3
Expected OA Rounds
73%
Grant Probability
78%
With Interview (+5.5%)
2y 4m (~6m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 1115 resolved cases by this examiner. Grant probability derived from career allowance rate.

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