DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-8 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rodrigues et al. (USPAPN 2022/0178999) in view of Kazmirski et al. (USPN 11,307,239).
With respect to claim 1, Rodrigues et al. discloses, in Figs 1 and 2, a system for online detection of a semiconductor device (Fig. 1, method of operation disclosed in Fig. 2), comprising a controller (170), an online measurement circuit (110), and a detection module (103 with 150) configured to extract saturated drain current information (drain current saturation measurements, see paragraphs 0024 and 0031. The current detected by 103 is saturation drain current value when 101 is fully turned on/operated in saturation) of a device under test (101), wherein one end of the online measurement circuit (cathode of 111 at 112) is connected to a drain (112 to drain of 101 via 103) of the device under test (101), and the other end of the online measurement circuit (118) is connected to a source (at 119) of the device under test (101);
when the device under test (101) enters a saturation region to operate (when fully turned on), an energy storage element (115) in the online measurement circuit (101) spontaneously injects current (Itest) into the drain (at 112 into drain of 101) of the device under test (101), so that the drain current of the device under test (100) rises (drain current rises by the Itest value); the controller is connected to the detection module (170 receives the outputs of 103 and 150), and determines operational parameters of the device under test (the controller determines operations of 101 according to measurements of the drain current, i.e., via 103/Vsense/Vpeak and the gate voltage, e.g., via Vgate, etc. see 207-211 of Fig. 2) according to the saturated drain current information of the device under test extracted by the detection module (according to the injected Itest current, see 205 of Fig. 2).
Rodrigues et al. fails to explicitly disclose that one of the measured parameters of the device under test (101) is "a junction temperature" the semiconductor device under test (101). Thus, Rodrigues et al. fails to explicitly disclose that the controller "determines the junction temperature of the device under test" (101) "according to the saturated drain current information of the device under test (100) extracted by the detection module"
However, Kazmirski et al. discloses in Figs. 3, 5A, 5B, 6 and 8, a system for online detection of a semiconductor device junction temperature (circuit of Fig. 3 further details disclose in Fig. 8 and further operational details disclosed in Figs. 5A-6). The system includes a device under test (e.g., 310 of Fig. 3/transistor of Fig. 8)a measurement circuit (330/device measuring VFE of Fig. 8) and controller (340 with 350) for measuring/determining junction temperature (see 615 of Fig. 6) based on the saturation (i.e., drain current Id) and saturation voltage (Vds, i.e., VFE of Fig. 8, see Col. 3 lines 30-41, Col. 5 lines 45-49 and Col. 7 line 63 to Col. 8 line 16. Note, VFE of Fig. 8 is used to determine the drain to source voltage which is used to determine the on resistance and thus junction temperature, see Col. 7 lines 55-62 and Fig. 5A and Fig. 5B with Col. 6 lines 20-47). As can be seen the above junction temperature determination circuitry of Kazmirski allows for the optimization of the transistor capacity with respect to junction temperature (see Col. 6 lines 20-47 and Figs. 5A-6). It is further noted that VFE of Kazmirski (i.e., Vds plus the voltage drop of the diode of Fig. 8) is essentially the same terminal/voltage as the voltage at 117 (i.e., at the anode) of 111 of Fig. 1 of Rodrigues et al.
It would have been obvious to add the additional junction temperature monitoring circuit of Kazmirski et al. (i.e., circuitry 330-350 that measures VFE of Fig. 8) to measure the voltage on 117 (i.e., the anode voltage of 111) of Rodrigues et al. for the purpose of being able measure the junction temperature of 101 and optimize the current capacity of 101 according to the measured junction temperature of 101 of Rodrigues et al.
With respect to claim 2, the system for online detection of a junction temperature of a semiconductor device according to claim 1, further comprising a driving voltage control circuit (120 with 140), wherein one end of the driving voltage control circuit (output of 123/140) is connected to a gate (gate of 101) of the device under test (101), the other end of the driving voltage control circuit is connected to a Kelvin source (119/157) of the device under test (101), a control end of the driving voltage control circuit is connected to the controller (e.g. 130 connected to 137 of 170), and the controller controls the driving voltage control circuit to output a driving voltage signal to the device under test (via at least under the controls of c137 and c143), so that the device under test enters the saturation region to operate (according to the magnitude of the output of the gate driver to fully activate 101). Assuming, arguendo, that the source terminal 119 and ground terminal of 157 is not explicitly disclosed as a "Kelvin" source. It is old and well-known to connect a gate driver, such as 120 of Rodrigues et al., to the Kelvin source of the transistor being driven by the gate driver, such as 101 of Rodrigues et al., to the Kelvin source (i.e., a source that is isolated from the main current-carrying source path) having a low-inductance path directly from the transistors die for the purpose of minimizing stray inductance and thus reducing switching losses and increasing switching speeds. Examiner takes official notice of such well-known connections between a gate driver and a Kelvin source of a transistor for the purpose of reducing switching losses and increasing switching speeds. It would have been obvious to connect the gate driver to a Kelvin source of 101 of Rodrigues et al. for the purpose of reducing switching losses and increasing switching speeds of the circuit of Rodrigues et al.
With respect to claim 3, the system for online detection of a junction temperature of a semiconductor device according to claim 1, wherein the online measurement circuit (110) comprises an energy storage element (115), a direct current (DC) voltage source (voltage across 108 with 109, see paragraphs 0012-0015), a controllable switching device (116) and a device with a unidirectional blocking function (111), wherein one end of the device with a unidirectional blocking function (112) is connected to the drain (at 112 via 103) of the device under test (101), the other end of the device with a unidirectional blocking function (117) is connected to one end of the energy storage element (positive terminal of 115 via 113) and one end of the controllable switching device (drain of 116), the other end of the controllable switching device (source of 116) is connected to a positive pole of the DC voltage source (via the drain to source conduction path of 116, capacitor 115 and resistor 114), and a negative pole of the DC voltage source (109) and the other end of the energy storage element (negative terminal of 115 when 116 is active) are connected to the source (119 via 118) of the device under test (101).
With respect to claim 4, the system for online detection of a junction temperature of a semiconductor device according to claim 1, wherein the online measurement circuit (110) comprises an energy storage element (115), a pulsed DC source (108 and 109 with 116. The DC voltage/current across 116 is pulsed according to the activation/deactivation of 116) and a device with a unidirectional blocking function (111), wherein one end of the device with a unidirectional blocking function (112) is connected to the drain (via 112 and 103) of the device under test (101), the other end of the device with a unidirectional blocking function (117 via 113) is connected to one end of the energy storage element (positive terminal of 115) and a positive pole of the pulsed DC source (108), and a negative pole of the pulsed DC source (109 with switch 116) and the other end of the energy storage element (negative terminal of 115) are connected to the source (119 via 118) of the device under test (101).
With respect to claim 5, the system for online detection of a junction temperature of a semiconductor device according to claim 1, wherein the online measurement circuit (110) comprises an energy storage element (115) and a device with a unidirectional blocking function (111), wherein one end of the device with a unidirectional blocking function (112) is connected to the drain (via 112 and 103) of the device under test (101), the other end of the device with a unidirectional blocking function (117) is connected to one end of the energy storage element (via 113), and the other end of the energy storage element (via 116) is connected to the source (119 via 118) of the device under test (101).
With respect to claim 6, the system for online detection of a junction temperature of a semiconductor device according to claim 5, wherein the energy storage element (115) is a capacitor (115 is a capacitor).
With respect to claim 7, a method for online detection of a junction temperature of a semiconductor device, based on the system for online detection of a junction temperature of a semiconductor device according to claim 1, and comprising:
enabling the device under test (100) to enter the saturation region to operate (by applying the gate voltage and turning on 101 to be full active, see 203 of Fig. 2 of Rodrigues et al.), and injecting (injecting Itest, see 205 of Fig. 2), by the energy storage element (115) in the online measurement circuit (110, Itest is generated according to energy stored within 115), current into the drain (Itest into 112 and into the drain via 103) of the device under test (101) spontaneously after the device under test (101) enters the saturation region to operate (Itest is injected after turn on/saturation), so that the drain current of the device under test (101) rises (drain current rises by the Itest value); extracting the saturated drain current information of the device under test (101) by the detection module (103 extracts the drain current/saturation current); and determining the junction temperature of the device under test (101) according to the saturated drain current information of the device under test (Kazmirski et al. discloses that the junction temperature is determined, at least in part, on the saturation current, i.e., drain current, see Col. 3 lines 30-47).
Claim 8 is rejected for essentially the same reasons as claim 2.
Claim 10 is rejected for essentially the same reasons as claims 1 and/or 7.
Allowable Subject Matter
Claim 9 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thomas J. Hiltunen whose telephone number is (571)272-5525. The examiner can normally be reached 9:00AM-5:30PM EST M-F.
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/THOMAS J. HILTUNEN/Primary Examiner, Art Unit 2836
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