DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 18-37 are pending in the application. Claims 21-37 are new. Claims 18, 21 and 29 are independent claims.
Election/Restrictions
Applicant’s election without traverse of Group III: claims 18-20 and new claims 21-37 in the reply filed on 15 April 2026 is acknowledged.
Information Disclosure Statement
Acknowledgment is made of applicant’s Information Disclosure Statement(s) (IDS), Form PTO-1449, filed 11 September 2025. The information therein was considered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 18-27 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chiang et al. (US 2023/0240078) (hereinafter, “Chiang”).
Re: independent claim 18, Chiang discloses in figs. 2 and 4-7 a method, comprising: forming a first active region (164) and a second active region (162) over a semiconductor substrate (214, 238, 258), wherein a longitudinal direction of the first active region is substantially parallel with a longitudinal direction of the second active region (fig. 4), and the second active region (162) extends beyond a side of the first active region (164) in a top view; forming a storage gate structure (168) over the first active region (164) and the second active region (162), a write access gate structure (170) over the first active region (164), and a read access gate structure (166) over the second active region (162), wherein the storage gate structure (168) overlaps the side of the first active region (164); and forming an interconnect structure over the storage gate structure (168), the write access gate structure (170), and the read access gate structure (166), wherein the interconnect structure comprises a write word line (112) electrically coupled with the write access gate structure (170) and a read word line (114) electrically coupled with the read access gate structure (166).
Re: claim 19, Chiang discloses in figs. 2 and 4-7 the method of claim 18, further comprising: forming an isolation structure (216) over the semiconductor substrate (214) to surround the first active region (212, 164) and the second active region (212, 162), wherein the isolation structure (216) is in contact with the side of the first active region (212, 164).
Re: claim 20, Chiang discloses in figs. 2 and 4-7 the method of claim 18, wherein forming the storage gate structure (168), the write access gate structure (170), and the read access gate structure (166) comprises: forming a plurality of dummy gate structures (206, 230, 250) over the first active region (236) and the second active region (212, 256), wherein one of the dummy gate structures (230) overlaps the side of the first active region (236); and replacing the dummy gate structures with a gate dielectric layer and a gate metal layer [0060], [0065], [0070].
Re: independent claim 21, Chiang discloses in figs. 2 and 4-7 a method, comprising: forming first and second active regions (164, 162) over a semiconductor substrate (214, 238, 258), the first and second active regions extending longitudinally in parallel (fig. 4), the second active region (162) extending beyond a side of the first active region (164) in a top view; forming a storage gate structure (168) over the first and second active regions (164, 162), a write access gate structure (170) over the first active region (164), and a read access gate structure (166) over the second active region (162), the storage gate structure (168) overlapping the side of the first active region (164) in the top view; forming source/drain regions (220, 244, 264) in the first and second active regions adjacent the storage gate structure (168), the write access gate structure (170), and the read access gate structure (166); forming source/drain contacts (180, 182, 174) over the source/drain regions; forming a connection feature (180) over and electrically coupling one of the source/drain contacts to the storage gate structure (168); and forming an interconnect structure over the source/drain contacts (180, 182, 174), the storage gate structure (168), the write access gate structure (170), and the read access gate structure (166), the interconnect structure comprising a write word line (112) electrically coupled with the write access gate structure (170) and a read word line (114) electrically coupled with the read access gate structure (166).
Re: claim 22, Chiang discloses in figs. 2 and 4-7 the method of claim 21, wherein the connection feature (180) is in contact with the one of the source/drain contacts (180) and the storage gate structure (168) [0052].
Re: claim 23, Chiang discloses in figs. 2 and 4-7 the method of claim 21, further comprising: forming an isolation structure (216) over the semiconductor substrate (214) to surround the first and second active regions (212, 164, 162), wherein the isolation structure (216) is in contact with the side of the first active region (212, 164).
Re: claim 24, Chiang discloses in figs. 2 and 4-7 the method of claim 21, wherein forming the storage gate structure (168) comprises: forming the storage gate structure (168) such that the side of the first active region (164) is located directly below the storage gate structure (168), and the second active region (162) extends beyond a sidewall of the storage gate structure (168) in the top view.
Re: claim 25, Chiang discloses in figs. 2 and 4-7 the method of claim 21, wherein the side of the first active region (164) is a first side, and the first active region (164) further has a second side extending substantially along a longitudinal direction of the first active region (164) and adjoining the first side, and the storage gate structure (168) is in contact with the first side in the top view (fig. 4).
Re: claim 26, Chiang discloses in figs. 2, 4-7 and 11-13 the method of claim 23, wherein, after the storage gate structure (168, 324) is formed, a bottom surface of the storage gate structure has a first portion over the first active region (164, 312), a second portion in contact with the isolation structure (314), and a third portion connecting the first portion to the second portion and in contact with the side of the first active region (164, 312) when viewed along a gate direction crossing the longitudinal direction of the first active region (figs. 11-13).
Re: claim 27, Chiang discloses in figs. 2 and 4-5 the method of claim 21, wherein forming the interconnect structure comprises: forming a first metallization layer comprising a write bit line (108), a read bit line (110), and a reference voltage line (116) extending in a first direction; and forming a second metallization layer comprising the write word line (112) and the read word line (114) extending in a second direction crossing the first direction.
Allowable Subject Matter
Claims 29-37 are allowed.
Claim 28 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record fails to teach the claimed limitations in combination namely, as recited in independent claim 29, a method, comprising: forming first and second active regions over a semiconductor substrate, the first and second active regions extending longitudinally in parallel, the second active region extending beyond a side of the first active region in a top view; forming a storage gate structure over the first and second active regions; forming a continuous metal gate structure over the first and second active regions; etching an opening in the continuous metal gate structure; filling the opening with a dielectric material to divide the continuous metal gate structure into a write access gate structure over the first active region and a read access gate structure over the second active region; forming source/drain regions in the first and second active regions adjacent the storage gate structure, the write access gate structure, and the read access gate structure; forming source/drain contacts over the source/drain regions; and forming an interconnect structure over the source/drain contacts, the storage gate structure, the write access gate structure, and the read access gate structure, the interconnect structure comprising a write word line electrically coupled with the write access gate structure and a read word line electrically coupled with the read access gate structure; and as recited in claim 28, the method of claim 21, wherein the first active region is free of a source/drain region on a side of the storage gate structure facing away from the write access gate structure.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Teman et al. US 11,127,455 teach a FinFET gain cell including a write port, a read port and a storage node; wherein a gate of a write transistor and a gate of a read transistor are formed on a same fin, the fin having a cut electrically disconnecting the gate of the write transistor and the gate of the second read transistor along the fin.
The examiner has cited particular columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. When responding to this office action, applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALLISON BERNSTEIN whose telephone number is (571)272-9011. The examiner can normally be reached M-F 8AM-5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached on 571-272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ALLISON BERNSTEIN/Primary Examiner, Art Unit 2824 7/14/2026
Prosecution Insights