DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Inventorship
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/03/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 2, 8, 12, 15, 18 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kasai et al. (US 20060198170) in view of Imai et al. (US 20040189273).
Claims 1, 2, 18 and 20; Kasai et al. disclose an apparatus comprising: controller circuitry (e.g. R1/Rx, ERA, PWMD, PWMU) having: a second input terminal (FB); and an output terminal (DH1/DL1/DH2/DL2); the controller circuitry configured to: receive, at the second input terminal, an indication of an output voltage (VFB); and, adjusts an offset value (14) in response to a determination that the output voltage is outside the threshold voltage (para. [0078]) and provide, at the output terminal, an output signal based on the offset value.
However, Kasai et al. do not disclose whether the control circuitry has a first input terminal coupled to memory configured to store a value representative of a threshold voltage (e.g. a reference voltage).
Imai et al. teach a switching power supply having control circuitry (10, 11, 12, 13, 15, 16) with an input terminal (at 15) coupled to memory (14) configured to store a value representative of a threshold voltage (e.g. a reference voltages) in order to regulate the output of switching power supplies to cause the output to reach the target value rapidly with suppressed overshoots and undershoots.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify Kasai et al. to include control circuitry with a first input terminal coupled to memory configured to store a value representative of a threshold voltage as taught by Imai et al. in order to provide a switching regulator that regulates the output of switching power supplies to cause the output to reach the target value rapidly with suppressed overshoots and undershoots.
Claims 8 and 12; having: Kasai et al. disclose a system, comprising: power stage circuitry (FET1-FET4); multiphase manager circuitry controller circuitry (e.g. R1/Rx, ERA, PWMD, PWMU) having: a second input terminal coupled to a capacitor (C1 at FB); and an output terminal (DH1/DL1/DH2/DL2) coupled to the power stage circuitry (FET!-FET4); the controller circuitry configured to: receive, at the second input terminal, an indication of an output voltage (VFB); and, adjusts an offset value (14) in response to a determination that the output voltage is outside the threshold voltage (para. [0078]) and provide, at the output terminal, a pulse width modulation (PWM) signal to the power stage circuitry based on the offset value.
However, Kasai et al. do not disclose whether the control circuitry has a first input terminal coupled to memory configured to store a value representative of a threshold voltage (e.g. a reference voltage).
Imai et al. teach a switching power supply having control circuitry (10, 11, 12, 13, 15, 16) with an input terminal (at 15) coupled to memory (14) configured to store a value representative of a threshold voltage (e.g. a reference voltages) in order to regulate the output of switching power supplies to cause the output to reach the target value rapidly with suppressed overshoots and undershoots.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify Kasai et al. to include control circuitry with a first input terminal coupled to memory configured to store a value representative of a threshold voltage as taught by Imai et al. in order to provide a switching regulator that regulates the output of switching power supplies to cause the output to reach the target value rapidly with suppressed overshoots and undershoots.
Claim 15; the power stage circuitry is first power stage circuitry (FET1 & FET2); the output terminal is a first output terminal (DH1/DL1); the PWM signal is a first PWM signal (PWMD); the multiphase manager circuitry further includes a second output terminal coupled to second power stage circuitry (FET2 & FET3); and the multiphase manager circuitry is further configured to provide, at the second output terminal, a second PWM signal (DH2/DL2) to the second power stage circuitry based on the offset value.
Allowable Subject Matter
Claim 3-7, 9-11, 13, 14, 16, 17 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claims 3-5; prior art fails to disclose or fairly suggest, inter alia, the threshold voltage is a first threshold voltage; the memory is further configured to store a second threshold voltage; and the controller circuitry is further configured to increase, in response to a determination the output voltage is below the second threshold voltage, the offset value.
Claim 6; prior art fails to disclose or fairly suggest, inter alia, the controller circuitry is configured to: increment a counter value in response to the output voltage exceeding the threshold voltage; and modify the offset value in response to the counter value exceeding a threshold value.
Claim 7; prior art fails to disclose or fairly suggest, inter alia, the output voltage is responsive to the output signal; and the controller circuitry is configured to provide the output signal such that the offset value is proportional to a target average magnitude of the output voltage.
Claims 9-11; prior art fails to disclose or fairly suggest, inter alia, wherein the multiphase manager circuitry is configured to: determine an output current flowing to a load based on the output voltage; and perform Direct Current Load Line (DCLL) control operations to adjust a setpoint of the output voltage as a function of the output current, the DCLL control operations including providing the PWM signal to the power stage circuitry.
Claim 13; prior art fails to disclose or fairly suggest, inter alia, the threshold voltage is a first threshold voltage; the memory is further configured to store a second threshold voltage; and the multiphase manager circuitry is further configured to increase, in response to a determination the output voltage is below the second threshold voltage, the offset value.
Claim 14; prior art fails to disclose or fairly suggest, inter alia, the memory is further configured to store: a maximum voltage corresponding to a safety rating of the system, the first threshold voltage less than the maximum voltage; and a minimum voltage corresponding to the safety rating of the system, the second threshold voltage greater than the maximum voltage.
Claim 16; prior art fails to disclose or fairly suggest, inter alia, the multiphase manager circuitry is configured to: increment a counter value in response to the output voltage exceeding the threshold voltage; and modify the offset value in response to the counter value exceeding a threshold value.
Claim 17; prior art fails to disclose or fairly suggest, inter alia, the output voltage is responsive to the PWM signal; and the multiphase manager circuitry is configured to provide the PWM signal such that the offset value is proportional to a desired average magnitude of the output voltage.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 20140132232 MacLean et al. disclose a DC converter with OFFSET adjustment; US 10778101 Schmitz discloses a switching regulator with memory circuit; US 5297014 Saito et al. disclose a switching power supply with offset means for offsetting a threshold value.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GARY L LAXTON whose telephone number is (571)272-2079. The examiner can normally be reached Monday-Friday, 8 am-4 pm.
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/GARY L LAXTON/Primary Examiner, Art Unit 2838 4/21/2026
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