DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 02/13/2026 has been entered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 4, 15 and 17-19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park et al. (US 2024/0038148 A1).
As to claim 1, Park et al. teaches a pixel driving circuit (P in Fig. 2;[0072]: pixel circuit P), comprising:
a driving module (T1 in Fig. 2), wherein a control terminal of the driving module (T1 in Fig. 2) is directly electrically connected to a first node (N1 in Fig. 2), a first terminal of the driving module (T1 in Fig. 2) is directly electrically connected to a second node (N2 in Fig. 2), and a second terminal of the driving module (T1 in Fig. 2) is directly electrically connected to a third node (N3 in Fig. 2);
a voltage writing module (T2 in Fig. 2), wherein a first terminal of the voltage writing module (T2 in Fig. 2) is directly electrically connected to a preset potential signal line (VDATA/Vbias line in Fig. 2), a second terminal of the voltage writing module (T2 in Fig. 2) is directly electrically connected to the second node (N2 in Fig. 2), and a control terminal of the voltage writing module (T2 in Fig. 2) directly electrically connected to a first control signal line (GW line in Fig. 2) ; and
a potential coupling module including a coupling capacitor (Cbst in Fig. 2) , wherein a first terminal of the coupling capacitor (Cbst in Fig. 2) is directly electrically connected to the first control signal line (GW line in Fig. 2), and a second terminal of the coupling capacitor (Cbst in Fig. 2) is directly electrically connected to at least one of the second node and the third node (N3 in Fig. 2).
As to claim 4, Park et al. teaches a display panel ([0060]: display panel), comprising:
a light-emitting element (EE in Fig. 2;[0072]); and
a plurality of pixel driving circuits ([0062]: pixel circuits P) electrically connected to the light-
emitting element (EE in Fig. 2; [0072]),
wherein:
each of at least a partial number of the plurality of the pixel driving circuits ([0062]: pixel circuits
P) includes:
a driving module (T1 in Fig. 2), wherein a control terminal of the driving module (T1 in Fig. 2) is directly electrically connected to a first node (N1 in Fig. 2), a first terminal of the driving module (T1 in Fig. 2) is directly electrically connected to a second node (N2 in Fig. 2), and a second terminal of the driving module (T1 in Fig. 2) is directly electrically connected to a third node (N3 in Fig. 2);
a voltage writing module (T2 in Fig. 2), wherein a first terminal of the voltage writing module (T2 in Fig. 2) is directly electrically connected to a preset potential signal line (VDATA/Vbias line in Fig. 2), a second terminal of the voltage writing module (T2 in Fig. 2) is directly electrically connected to the second node (N2 in Fig. 2), and a control terminal of the voltage writing module (T2 in Fig. 2) directly electrically connected to a first control signal line (GW line in Fig. 2) ; and
a potential coupling module including a coupling capacitor (Cbst in Fig. 2) , wherein a first terminal of the coupling capacitor (Cbst in Fig. 2) is directly electrically connected to the first control signal line (GW line in Fig. 2), and a second terminal of the coupling capacitor (Cbst in Fig. 2) is directly electrically connected to at least one of the second node and the third node (N3 in Fig. 2).
As to claim 15, Park et al. teaches the display panel according to claim 4, further comprising:
a base substrate (Abstract: substrate),
wherein: the pixel driving circuit further includes a first conductive layer ([0076]; [0121]: first gate line GT1a includes a first boost electrode BST1) and a second conductive layer located on one side of the base substrate (substrate SUB in Fig. 11; [0127]: second active pattern ACT2; [0130] second active pattern ACT2 (e.g., the compensation transistor T3 and the first initialization transistor T4), and the second conductive layer ([0127]: second active pattern ACT2; [0130] second active pattern ACT2 (e.g., the compensation transistor T3 and the first initialization transistor T4) is located on a side of the first conductive layer ([0076]; [0121]: first gate line GT1a includes a first boost electrode BST1) facing away from the base substrate (Abstract; [0127]; second active pattern ACT2, substrate SUB in Fig. 11);
transistors in the pixel driving circuit include a first type of transistors and a second type of
transistors ([0076-0077]: PMOS, NMOS transistors), and a material of an active layer of the first type of
transistors ([0113-0114]: first active pattern ACT1 includes a silicon semiconductor. First active
pattern ACT1 (e.g., the driving transistor T1, the write transistor T2, the first emission transistor
T5, the second emission transistor T6, and the second initialization transistor T7) are the PMOS
transistor) is different from a material of an active layer of the second type of transistors ([0077]:
compensation transistor T3 and the first initialization transistor T4 are oxide thin film
transistors; [0127]: second active pattern ACT2 include oxide semiconductor; [0130] second active pattern ACT2 (e.g., the compensation transistor T3 and the first initialization transistor T4) is NMOS transistor);
the first conductive layer includes one terminal of the coupling capacitor and a gate of the first type of transistors ([0076]; [0121]: first gate line GT1a includes a first boost electrode BST1 integrally formed with each of the gate electrode of the write transistor T2 and the second initialization transistor T7); and
the second conductive layer includes another terminal of the coupling capacitor, one terminal of the potential holding module in the pixel driving circuit, a gate of the second type of transistors, the active layer of the second type of transistors, or a source/drain of the first type of transistors and the second type of transistors ([0127]: second active pattern ACT2; [0130] second active pattern ACT2 (e.g., the compensation transistor T3 and the first initialization transistor T4).
As to claim 17, Park et al. teaches the display panel according to claim 4, wherein the voltage
writing module at least comprises:
a data writing module (T2 in Fig. 2),
wherein the pixel driving circuit also includes:
a threshold compensation module (T3 in Fig. 2) electrically connected between the first node
(N1 in Fig. 2) and the third node (N3 in Fig. 2);
a first light-emitting control module (T5 in Fig. 2) and a potential holding module (Cst in Fig.
2), wherein a first terminal of the first light-emitting control module (T5 in Fig. 2) and a first terminal of
the potential holding module (Cst in Fig. 2) are both connected to a first power signal line (ELVDD in
Fig. 2), a second terminal of the first light- emitting control module (T5 in Fig. 2) electrically connected to
the second node (N2 in Fig. 2), a control terminal of the first light-emitting control module (T5 in Fig. 2)
is electrically connected to a light-emitting control signal line (EM in Fig. 2), and a second terminal of the
potential holding module (Cst in Fig. 2) is electrically connected to the first node (N1 in Fig. 2);
a first reset module (T4 in Fig. 2), wherein a first terminal of the first reset module (T4 in Fig. 2)
is electrically connected to a first reset signal line (VINT line in Fig. 2), a second terminal of the first reset
module (T4 in Fig. 2) is electrically connected to the first node (N1 in Fig. 2), and a control terminal of
the first reset module (T4 in Fig. 2) is electrically connected to a second control signal line (GI line in Fig.
2); and
a second light-emitting control module (T6 in Fig. 2) and a second reset module (T7 in Fig. 2),
wherein a first terminal of the second light-emitting control module (T6 in Fig. 2) is electrically
connected to the second node (N2 in Fig. 2), a first terminal of the second reset module (T7 in Fig. 2) is
electrically connected to a second reset signal line (VAINT line in Fig. 2), a
second terminal of the second light-emitting control module (T6 in Fig. 2) and a second terminal of the
second reset module (T7 in Fig. 2) are both connected to the light-emitting element (EE in Fig. 2), a
control terminal of the second light-emitting control module (T6 in Fig. 2) is electrically connected to the
light-emitting control signal line (EM line in Fig. 2), and a control terminal of the second reset module
(T7 in Fig. 2) is electrically connected to the first control signal line (GW line in Fig. 2).
As to claim 18, Park et al. teaches the display panel according to claim 17, wherein the voltage
writing module further comprises: a bias module ([0025]: bias voltage applied to data line; [0100]: bias
voltage Vbias, Fig. 2).
As to claim 19, Park et al. teaches a display device ([0060]: display devuce), comprising:
a display panel ([0060]: display panel) including a light-emitting element (EE in Fig. 2; [0072]);
and
a plurality of pixel driving circuits ([0062]: pixel circuits P) electrically connected to the light-
emitting element (EE in Fig. 2; [0072]),
wherein each of at least a partial number of the plurality of the pixel driving circuits ([0062]:
pixel circuits P) includes:
a driving module (T1 in Fig. 2), wherein a control terminal of the driving module (T1 in Fig. 2) is directly electrically connected to a first node (N1 in Fig. 2), a first terminal of the driving module (T1 in Fig. 2) is directly electrically connected to a second node (N2 in Fig. 2), and a second terminal of the driving module (T1 in Fig. 2) is directly electrically connected to a third node (N3 in Fig. 2);
a voltage writing module (T2 in Fig. 2), wherein a first terminal of the voltage writing module (T2 in Fig. 2) is directly electrically connected to a preset potential signal line (VDATA/Vbias line in Fig. 2), a second terminal of the voltage writing module (T2 in Fig. 2) is directly electrically connected to the second node (N2 in Fig. 2), and a control terminal of the voltage writing module (T2 in Fig. 2) directly electrically connected to a first control signal line (GW line in Fig. 2) ; and
a potential coupling module including a coupling capacitor (Cbst in Fig. 2) , wherein a first terminal of the coupling capacitor (Cbst in Fig. 2) is directly electrically connected to the first control signal line (GW line in Fig. 2), and a second terminal of the coupling capacitor (Cbst in Fig. 2) is directly electrically connected to at least one of the second node and the third node (N3 in Fig. 2).
Claim(s) 5-6 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 2024/0038148 A1) in view of Zhang (US 2024/0371321 A1).
As to claim 5, Park et al. teaches the display panel according to claim 4, wherein the light-emitting element comprises: the pixel driving circuit includes a first pixel driving circuit and a second pixel driving circuit ([0062]: pixel circuits P) and the at least partial number of the pixel driving circuits include at least the first pixel driving circuit ([0062]: pixel circuits P), but does not explicitly disclose
a light-emitting element of a first color; and a light-emitting element of a second color, wherein:
the first color is different from the second color; the first pixel driving circuit is directly electrically connected to the light-emitting element of the first color; the second pixel driving circuit is directly electrically connected to the light-emitting element of the second color.
However, Zhang teaches a light-emitting element of a first color ([0040]: red; [0048]; claims 1 and 15: red); and
a light-emitting element of a second color ([0062]: blue; claims 1 and 15: blue),
wherein:
the first color ([0040]: red) is different from the second color ([0062]: blue);
the first pixel driving circuit is directly electrically connected to the light-emitting element of the first color ([0048]; claims 1 and 15: red)
the second pixel driving circuit is directly electrically connected to the light-emitting element of the second color ([0048];[0062]: blue; claims 3 and 15: blue).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Park et al. such that the first color is different from the second color, the first pixel driving circuit is directly electrically connected to the light-emitting element of the first color, and the second pixel driving circuit is directly electrically connected to the light-emitting element of the second color as taught by Zhang in order to display a color image.
As to claim 6, Park et al. teaches the display panel as discussed above, wherein the light-emitting element further comprises: the pixel driving circuit further includes a third pixel driving circuit ([0062]: plurality of pixel circuits P) the at least the partial number of the pixel driving circuits further include the third pixel driving circuit ([0062]: plurality of pixel circuits P); the potential coupling module (Cst in Fig. 2) in the first pixel driving circuit (P in Fig. 2;[0062];[0072]); the potential coupling module (Cst in Fig. 2) in the third pixel driving circuit ([0062]: plurality of pixel circuits P;[0072]), but does not explicitly disclose a light-emitting element of a third color, wherein: the third color is different from the first color and the second color; the third pixel driving circuit is electrically connected to the light-emitting element of the third color; the potential coupling module in the first pixel driving circuit has a first coupling value; the potential coupling module in the third pixel driving circuit has a second coupling value; and the second coupling value is different from the first coupling value.
However, Zhang teaches a light-emitting element of a third color ([0040];[0048]; claims 1 and 15: green),
wherein:
the third color ([0040]; [0048]; claims 1 and 15: green) is different from the first color ([0040]: red) and the second color ([0062]: blue);
the third pixel driving circuit is electrically connected to the light-emitting element of the third color ([0040]; [0048]; claims 1 and 15: green);
the potential coupling module in the first pixel driving circuit has a first coupling value (claim 1: the first pixel driving circuit has a first coupling capacitor, first coupling capacitance of the first coupling capacitor);
the potential coupling module in the third pixel driving circuit has a second coupling value ([0063]: third pixel driving circuit has third coupling capacitor, third coupling capacitance of the third coupling capacitor); and
the second coupling value is different from the first coupling value ([0063]; claims 1 and 3: first coupling capacitance of the first coupling capacitor is greater than a second coupling capacitance of the second coupling capacitor. The second coupling capacitance of the second coupling capacitor is greater than a third coupling capacitance of the third coupling capacitor).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Park et al. with a light-emitting element of a third color, wherein the third color is different from the first color and the second color, the third pixel driving circuit is electrically connected to the light-emitting element of the third color, the potential coupling module in the first pixel driving circuit has a first coupling value, the potential coupling module in the third pixel driving circuit has a second coupling value, and the second coupling value is different from the first coupling value as taught by Zhang in order to improve the issue of the abnormal color mixing introduced by the different degrees of change in luminance of light emitting devices of different colors.
As to claim 13, Park et al. teaches the display panel as discussed above, but does not explicitly disclose wherein: the first color is red; the second color is blue; and the third color is green.
However, Zhang teaches wherein: the first color is red ([0040]: red; [0048]; claims 1 and 15: red); the second color is blue ([0062]: blue; claims 1 and 15: blue); and the third color is green ([0040]; [0048]; claims 1 and 15: green).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Park et al. such that the first color is red, the second color is blue, and the third color is green as taught by Zhang in order to display a color image.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 2024/0038148 A1) in view of Zhang (US 2024/0371321 A1) and further in view of Li (US 2021/0158755 A).
As to claim 7, Park et al. teaches the display panel as discussed above, wherein the preset potential signal line comprises: a first potential signal line (VDATA/Vbias line in Fig. 2); wherein: the first potential signal line (VDATA/Vbias line in Fig. 2) is connected to the first pixel driving circuit (P in Fig. 2;[0072]: pixel circuit P); a second potential signal line ([0062]: plurality of data lines); and a third potential signal line ([0062]: plurality of data lines), the second potential signal line is connected to the second pixel driving circuit ([0062];[0111]: data line connected to each of the pixels); the third potential signal line is connected to the third pixel driving circuit([0062];[0111]: data line connected to each of the pixels); but does not explicitly disclose a driving sequence of the pixel driving circuit includes a refresh frame, and in the refresh frame, the first potential signal line transmits a first potential signal, the second potential signal line transmits a second potential signal, and the third potential signal line transmits a third potential signal.
However, Zhang teaches a driving sequence of the pixel driving circuit includes a refresh frame ([0037]: pixel driving circuit;[0043]: display panel adopts adaptive refresh rate technology to display images), and in the refresh frame ([0043]: display panel adopts adaptive refresh rate technology to display images. When the display panel displays images at a low refresh rate, the display period includes the write-in frame), the first potential signal line transmits a first potential signal ([0047]: data signal transmitted by the data line DL), the second potential signal line transmits a second potential signal ([0037]: pixel driving circuits, a plurality of data lines DL; [0047]: data signal transmitted by the data line DL), and the third potential signal line transmits a third potential signal ([0037]: pixel driving circuits, a plurality of data lines DL; [0047]: data signal transmitted by the data line DL).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Park et al. such that driving sequence of the pixel driving circuit includes a refresh frame, and in the refresh frame, the first potential signal line transmits a first potential signal, the second potential signal line transmits a second potential signal, and the third potential signal line transmits a third potential signal as taught by Zhang in order to display images.
Park et al. in view of Zhang teaches the device as discussed above, but does not explicitly disclose the second potential signal is lower than the first potential signal and the third potential signal.
However, Li et al. teaches the second potential signal is lower than the first potential signal and the third potential signal ([0040]; [0109]: pixel units of different colors have different data voltages; [0113]: blue pixel unit, red pixel unit, green pixel unit. Blue pixel unit should be provided with a smaller initial compensation data voltage).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Park et al. in view of Zhang such that the second potential signal is lower than the first potential signal and the third potential signal as taught by Li et al. in order to improve the display effect and avoid screen flicker.
Allowable Subject Matter
Claims 2-3, 8-12, and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 4-7, 13, 15 and 17-19 have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STACY KHOO whose telephone number is (571)270-3698. The examiner can normally be reached Mon-Fri 8:00 am-5:00 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Eason can be reached at 571-270-7230. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/STACY KHOO/Primary Examiner, Art Unit 2624