DETAILED ACTION
The following claims are pending in this office action: 1-30
Claims 1, 14, 20, 25 and 30 are independent claims
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings filed on 07/03/2024 are accepted.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/12/2024 has been considered. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, an initialed and dated copy of Applicant’s IDS form 1449 filed 11/12/2024 is attached to the instant Office action.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 6-7 are rejected under 35 U.S.C. 112(b), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 6-7 recites the limitation “the one or more threshold values” (claim 6, ln. 2-3; and claim 7, ln. 2-3). There is insufficient antecedent basis for this limitation in the claim. Examiner suggests replacing “the one or more threshold values” with “one or more threshold values.” See, for example, the same limitation recited in claim 2.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7, 9, 11, 13-17, 20-23, 25-28 and 30 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US Pub. 2025/0013746) (hereinafter “Kim”) as applied to claims 1, 5, 14, 20 and 25 above and in view Cho et al. (US Pub. 2023/0178140) (hereinafter “Cho”)
As per claim 1, Kim teaches a system, comprising: ([Kim, para. 0045] “a memory system 20 ... include a memory controller 30 [first semiconductor die] and a semiconductor memory device 200 [second semiconductor die]”)
a first semiconductor comprising: ([Kim, para. 0289] “The memory controller ...implemented using ... a system-on-a-chip”; the memory controller/first semiconductor as a first semiconductor die connected with the semiconductor memory device/second semiconductor as a second semiconductor die is more clearly taught by Cho below)
a first interface, ([Kim, para. 0062] “the memory controller 30 ... include a memory interface”) the first interface comprising first circuitry operable to transmit one or more access signals; and ([para. 0048] “The memory controller ... transmit a command”; [para. 0054] “In response to a ... command ... the row hammer management circuit 500 ... perform an internal read-update-write operation”; [para. 0065] “The memory interface 60 ... performing interfacing with the semiconductor memory device 200”)
a second semiconductor coupled with the first semiconductor, the second semiconductor comprising: ([Kim, para. 0291] “Each of the semiconductor devices ... employ the semiconductor memory device 200”; [Fig. 32] the semiconductor memory device is connected to the memory controller; the memory controller/first semiconductor as a first semiconductor die connected with the semiconductor memory device/second semiconductor as a second semiconductor die is more clearly taught by Cho below)
one or more memory arrays; and ([Kim, para. 0069] “the semiconductor memory device ... include ... the memory cell array”)
a second interface coupled with the first interface and the one or more memory arrays, ([Kim, para. 0290] “The memory module [second semiconductor device] ... coupled to the memory controller ... through the bus 1040”; [Fig. 1] The figure shows the memory cell array coupled to the memory controller) the second interface comprising second circuitry ([para. 0051] “The control logic circuit 210 ... control operations of the semiconductor memory device”) operable to access the one or more memory arrays based on receiving the one or more access signals, ([para. 0072-0073] “receive the BANK_ADDR [one or more access signals] ... from the memory controller ... The bank control logic 230 [an operation of the semiconductor memory device – see Fig. 3] may generate bank control signals in response to the bank address BANK_ADDR ... bank address BANK_ADDR is activated [access the one or more memory arrays] in response to the bank control signals [in response to the one or more access signals]”)
wherein the system is operable to: transmit, from the second interface to the first interface, one or more first signals ([Kim, para. 0141] “the monitor logic ... may notify the memory controller 30 [transmit to the first interface] ... transiting a logic level of the alert signal ALRT from a second logic level to a first logic level”) based on a value of a counter associated with a quantity of access operations on the one or more memory arrays; ([para. 0091] “The row hammer management circuit 500 may count the number of times of access associated with each of the plurality of memory cell rows based on an access address ADDR including the row address ROW_ADDR and the bank address BANK_ADDR accompanied by an active command from the memory controller 30 to store the counted values in the count cells of each of the plurality of memory cell rows as the count data CNTD”; [para. 0197] “row hammer management circuit 500 may read ... the count data CNTD ... number of times access is greater than ... reference number of times ... notify the memory controller 30 ... by transiting a logic level of the alert signal ALRT from the second logic level to the first logic level”)
transmit, from the first interface to the second interface based on the first interface receiving the one or more first signals, one or more second signals indicating a refresh operation associated with one or more addresses of the one or more memory arrays; and ([Kim, para. 0142] “In response to a transition of the alert signal ALRT [one or more first signals], the memory controller ... applies a refresh management command [one or more second signals] to the semiconductor memory device 200 ... the hammer refresh operation based on the hammer address HADDR [associated with one or more addresses of the one or more memory arrays]”)
perform, by the second interface, the refresh operation based on the second interface receiving the one or more second signals. ([Kim, para. 0142] “through the memory interface 60 in response to a transition of the alert signal ALRT from the semiconductor memory device 200 ... corresponding to the hammer address [associated with one or more addresses of the one or more memory arrays]”)
Kim does not clearly teach a first semiconductor die, a second semiconductor die, and a second semiconductor die coupled with the first semiconductor die.
However, Cho teaches a first semiconductor die, a second semiconductor die, and a second semiconductor die coupled with the first semiconductor die. ([Cho, Fig. 9] the memory controller [first semiconductor] included in the logic buffer die is coupled with the memory device including the RHC [second semiconductor] included in core dies 1-4; the row hammer control circuit corresponds to the semiconductor memory device 200)
It would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to have modified the elements disclosed by Kim with the teachings of Cho to include a first semiconductor die, a second semiconductor die, and a second semiconductor die coupled with the first semiconductor die. One of ordinary skill in the art would have been motivated to make this modification because such a modification allows for a high-performance interface for three-dimensional stacked memories allowing a wider bandwidth while consuming less power in a substantially smaller form factor. (Cho, para. 0090)
As per claim 2, Kim in view of Cho teaches claim 1.
Kim also teaches wherein the second circuitry of the second interface is further operable to: compare the value of the counter to one or more threshold values; and ([Kim, para. 0129] “provide the comparator 520 with the first reference number of times NTH1 as the selected reference number of times SNTH ... provide the comparator 520 with the second reference number of times NTH2 as the selected reference number of times SNTH”; [para. 0130] “The comparator 520 may compare the read count data CNTD [value of the counter] ... with the selected reference number of times SNTH [to one or more threshold values] to output a comparison signal CS2 indicating a result of the comparison”)
transmit the one or more first signals to the first interface based on the comparing. ([Kim, para. 0197] “row hammer management circuit 500 may perform the internal read-update-write operation to read the count data CNTD ... in response to the active count update command ... number of times of access is equal to or greater than the first reference number of times NTH1 and the second reference number of times NTH2 [based on the comparing] ... notify the memory controller 30 [transmit to the first interface] ... by transiting a logic level of the alert signal ALRT from the second logic level to the first logic level [transmit the one or more first signals]”)
As per claim 3, Kim in view of Cho teaches claim 2.
Kim also teaches wherein the second circuitry of the second interface is further operable to: read the value of the counter based on receiving the one or more access signals from the first interface; ([Kim, para. 0091] “The row hammer management circuit 500 [second circuitry of the second interface] may count [read] the number of times of access associated with each of the plurality of memory cell rows [the value of the counter] based on ... an active command from the memory controller 30 [receiving the one or more access signals from the first interface]”)
increment the value of the counter based on accessing the one or more memory arrays, ([Kim, para. 0125] “the adder 510 may update the count data CNTD read from the count cells of the target memory cell row to provide an updated count data UCNTD by increasing the count data CNTD by one, which is read from the count cells of the target memory cell row”) wherein the value of the counter is compared to the one or more threshold values after the incrementing; and ([para. 0130] “The comparator 520 may compare ... the updated count data UCNTD [value of the counter after the incrementing] with the selected reference number of times SNTH [the one or more threshold values”)
write the incremented value to the counter. ([Kim, para. 0206] “receive the ... updated count data UCNTD ... to be stored”)
As per claim 4, Kim in view of Cho teaches claim 1.
Kim also teaches wherein the second circuitry of the second interface is further operable to: perform one or more access operations on an address of the one or more memory arrays; and ([Kim, para. 0072-0073] “receive the address ... from the memory controller ... in response .... the bank address [address of the one or more memory arrays] ... activate [perform one or more access operations]”)
perform, concurrently with performing the one or more access operations, one or more operations to track, using the counter, a quantity of access operations on the address. ([Kim, para. 0091] “receive the address ... from the memory controller ... in response .... the bank address [address of the one or more memory arrays] ... activate [perform one or more access operations]”)
As per claim 5, Kim in view of Cho teaches claim 1.
Kim also teaches wherein the one or more first signals are transmitted based on the value of the counter indicating that a quantity of access operations on an address of the one or more memory arrays satisfies one or more threshold values. ([Kim, para. 0092] “The row hammer management circuit 500 may provide an address of a memory cell row which is intensively accessed as the hammer address HADDR to the... based on the result of the comparison”; [para. 0197] “row hammer management circuit 500 may perform the internal read-update-write operation to read the count data CNTD ... in response to ... number of times of access is equal to or greater than the ... reference number of times ... notify the memory controller 30 ... transiting a logic level of the alert signal ALRT from the second logic level to the first logic level”)
As per claim 6, Kim in view of Cho teaches claim 5.
Kim also teaches wherein the one or more first signals indicate that the value of the counter satisfies a first threshold value of the one or more threshold values, the system further operable to: generate, by the first interface, the one or more second signals indicating the refresh operation, wherein the refresh operation is for a second address different from the address and a third address different from the address based on the one or more first signals indicating that the value of the counter satisfies the first threshold value. ([Kim, para. 0067] “a refresh management command [one or more second signals indicating the refresh operation] to the semiconductor memory device 200 through the memory interface 60 [generate by the first interface] in response to [based on] a transition of the alert signal ALRT from the semiconductor memory device 200 [one or more first signals indicating that the value of the counter satisfies the first threshold value] such that the semiconductor memory device 200 performs a hammer refresh operation on one or more victim memory cell rows which are physically adjacent to a memory cell row [second address and third address different from the address] corresponding to the hammer address [the address]”; [para. 0152] “when a number of access times on a memory cell row ... becomes equal to or greater than the ... reference number of time NTH2 and an address of the word-lines WLd is determined as a hammer address HADDRa, the address of the word-lines WLd is provided to the refresh control circuit 400 as the hammer address HADDRa [first address] and the refresh control circuit 400 outputs addresses of the word-lines WLc and WLe, which are physically adjacent to the word-line WLd as hammer refresh addresses HREF_ADDRa_1 [second address] and HREF_ADDRa_2 [third address]”)
Kim does not clearly teach reset, by the second interface, a first portion of the counter based on the value of the counter satisfying the first threshold value; and increment, by the second interface, a second portion of the counter based on the value of the counter satisfying the first threshold value.
However, Cho teaches reset, by the second interface, a first portion of the counter based on the value of the counter satisfying the first threshold value; and ([Cho, para. 0053] “The comparator 530 [by the second interface] may output an output signal of a logic high level [reset] when the incremented access count value CNT+1 that is output from the counter 510 [value of the counter] and transmitted through the logic circuit 520 is greater than or equal to the threshold value THRESHOLD [satisfying the first threshold value] ... As an output CO signal of a logic high level of the comparator 530 is provided as a reset RST signal of the counter 510 ... the counter 510 may be reset to a zero value”)
increment, by the second interface, a second portion of the counter based on the value of the counter satisfying the first threshold value. ([Cho, para. 0049] “The control logic circuit 220 [second interface] may control the refresh control circuit 240 to perform a normal refresh operation by incrementing a refresh counter value by +1 [increment a second portion of the counter] in response to a refresh command [counter satisfying the first counter value as per above]”)
It would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to have modified the elements disclosed by Kim with the teachings of Cho to include reset, by the second interface, a first portion of the counter based on the value of the counter satisfying the first threshold value; and increment, by the second interface, a second portion of the counter based on the value of the counter satisfying the first threshold value. One of ordinary skill in the art would have been motivated to make this modification because accordingly, by keeping track of the refresh operations, row hammer address stored in the address storage may be prevented from being evicted or deleted until being target-refreshed by the counter, which in turn allows a row hammer attack from being easily performed. (Cho, para. 0031)
As per claim 7, Kim in view of Cho teaches claim 5.
Kim also teaches wherein the one or more first signals indicate that the value of the counter satisfies a second threshold value of the one or more threshold values greater than a first threshold value of the one or more threshold values, the system further operable to: ([Kim, para. 0128] “The register 530 may store a first reference number of times NTH1 and a second reference number of times NTH2 smaller than the first reference number of times NTH1”; [para. 0129] “provide the comparator 520 with the first reference number of times NTH1 as the selected reference number of times SNTH”; [para. 0130] “The comparator 520 may compare the read count data CNTD [value of the counter] ... with the selected reference number of times SNTH [to one or more threshold values] to output a comparison signal CS2 indicating a result of the comparison”)
generate, by the first interface, the one or more second signals indicating the refresh operation for ([Kim, para. 0067] “The RFM control logic 100 ... applies a refresh management command [generate the one or more second signals indicating the refresh operation] to the semiconductor memory device 200 through the memory interface 60 [by the first interface] in response to a transition of the alert signal ALRT from the semiconductor memory device 200 such that the semiconductor memory device 200 performs a hammer refresh operation on one or more victim memory cell rows which are physically adjacent to a memory cell row corresponding to the hammer address [for a first set of addresses]”; [para. 0197] “the row hammer management circuit 500, in response to ... number of times of access is equal to or greater than the first reference number of times NTH1 ... notify the memory controller 30 ... by transiting a logic level of the alert signal ALRT from the second logic level to the first logic level”) a first set of addresses that are different from the address and a second set of addresses that different from the address based on the one or more first signals indicating that the value of the counter satisfies the second threshold value. ([Para. 0251] “applies a refresh command RFM ... a hammer refresh operation two victim memory cell rows [a first set of addresses and a second set of addresses that are different from the address] physically adjacent to a memory cell row corresponding to the hammer address, in response to the refresh management command RFM [based on the one or more first signals as described above]”)
Kim does not clearly teach reset, by the second interface, the counter based on the value of the counter satisfying the threshold value.
However, Cho teaches reset, by the second interface, the counter based on the value of the counter satisfying the threshold value. ([Cho, para. 0053] “The comparator 530 [by the second interface] may output an output signal of a logic high level [reset] when the incremented access count value CNT+1 that is output from the counter 510 [value of the counter] and transmitted through the logic circuit 520 is greater than or equal to the threshold value THRESHOLD [satisfying the second threshold value as the threshold value is settable/changeable – see para. 0075] ... As an output CO signal of a logic high level of the comparator 530 is provided as a reset RST signal of the counter 510 ... the counter 510 may be reset to a zero value”; in view of Kim above, this is the counter satisfying the second threshold value as the first signal indicates the counter satisfying the second threshold value)
It would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Kim and Cho for the same reasons as disclosed above.
As per claim 9, Kim in view of Cho teaches claim 1.
Kim also teaches wherein the first circuitry of the first interface is further operable to determine an address of the one or more memory arrays associated with the one or more first signals. ([Kim, para. 0156] “an active command ... denotes ... a memory cell”; [para. 0158] “The memory controller 30 [first circuitry of the first interface], in response to transition of the alert signal ALRT [the one or more first signals], may withhold application of [determine] the active command [the one or more memory arrays associated with the one or more first signals]”)
Kim does not clearly teach determine an address based on a duration between transmitting the one or more access signals from the first interface and receiving the one or more first signals from the second interface.
However, Cho teaches determine an address based on a duration ([Cho, para. 0078] “When the row hammer monitoring time frame tREFi has not elapsed [based on a duration] ... control logic circuit 220 may perform a counter-based latch hold operation for the row hammer address RH_ADDR [determine an address]”) between transmitting the one or more access signals from the first interface and receiving the one or more first signals from the second interface. ([Para. 0096] “The row hammer control circuit RHC may monitor a row address that accesses a word line during a row hammer monitoring time frame [a duration], and when the number of times the word line is accessed [between transmitting the one or more access signals from the first interface] is greater than or equal to a threshold value, the row hammer control circuit (RHC) [the second interface] may determine the row address to be a row hammer address and store the row address [receiving the one or more first signals from the second interface]”)
It would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to have modified the elements disclosed by Kim with the teachings of Cho to include determine an address based on a duration between transmitting the one or more access signals from the first interface and receiving the one or more first signals from the second interface. One of ordinary skill in the art would have been motivated to make this modification because accordingly, by setting a time frame for the monitoring, row hammer attacks may be prevented by preventing the row hammer address from being deleted until normally refreshed, by the predetermined time frame. (Cho, para. 0031)
As per claim 11, Kim in view of Cho teaches claim 1.
Kim also teaches wherein the system is further operable to: transmit, from the first interface to the second interface, ([Kim, para. 0106] “in response to a refresh management signal RFMS ... provide ... a hammer refresh signal HREF [refresh operation]”; [para. 0107] “The control logic circuit [transmit to the second interface] ... refresh management signal RFMS based on a refresh management command from the memory controller 30 [from the first interface]”) one or more third signals indicating a second refresh operation associated with a set of addresses of the one or more memory arrays. ([Para. 0268; Fig. 29] “the hammer refresh address generator 440 may generate the hammer refresh address HREF_ADDR representing the address Ha1, Ha2, Ha3 and Ha4 [associated with a set of addresses of the one or more memory arrays] of the rows that are physically adjacent to the row of the hammer address in synchronization with the activation time points t5 [first refresh operation], t6, t7 and t8 [one or more third signals indicating a second refresh operation] of the hammer refresh signal HREF”)
Kim does not clearly teach reset, by the second interface, respective counters associated with each address of the set of addresses based on the one or more third signals.
However, Cho teaches reset, by the second interface, respective counters associated with each address of the set of addresses ([Cho, para. 0043] “the m-th counter memory cells [respective counters] C3m may store the number of access times for activating a memory cell row of the m-th word line WLm [associated with each address of the set of addresses]”; [para. 0052] “an access count value CNT stored in the counter memory cells ... may be read into the counter 510”; [para. 0053] “reset ... the counter 510 to zero”) based on the one or more third signals. ([Para. 0053] “As ... a reset RST signal [one or more third signals as the refresh operations are reset signals] ... the counter 510 may be reset to a zero signal”)
It would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Kim and Cho for the same reasons as disclosed above.
As per claim 13, Kim in view of Cho teaches claim 1.
Kim also teaches wherein the second semiconductor comprises: the counter; and ([Kim, para. 0050] “The semiconductor memory device 200 [second semiconductor] ... include a memory cell array 310 [the counter]”; [para. 0053] “store count data in the count cells of each of the plurality of memory cell rows”)
one or more dedicated access lines coupled with the second interface for accessing the counter. ([Kim, para. 0056] “The control logic circuit 210 [second interface] ... control access [coupled with] on the memory cell array 310”; [Fig. 4] dedicated lines are used for accessing the memory cells)
Kim does not clearly teach the second semiconductor as the second semiconductor die.
However, Cho teaches the second semiconductor as the second semiconductor die. ([Cho, Fig. 9] the memory device including the RHC [second semiconductor] is included in core dies 1-4)
It would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Kim and Cho for the same reasons as disclosed above.
As per claim 14, Kim teaches an apparatus comprising: ([Kim, para. 0045] “a memory system 20 [apparatus – see para. 0294 where the system is describes to be a number of different apparatuses] ... include a memory controller 30 [first semiconductor die] and a semiconductor memory device 200 [second semiconductor die]”)
a first semiconductor comprising ([Kim, para. 0289] “The memory controller ...implemented using ... a system-on-a-chip”; the memory controller/first semiconductor as a first semiconductor die connected with the semiconductor memory device/second semiconductor as a second semiconductor die is more clearly taught by Cho below) a first interface, the first interface comprising circuitry operable to: ([para. 0062] “the memory controller 30 ... include a memory interface”)
transmit, to a second interface of a second semiconductor coupled with the first semiconductor, ([Kim, para. 0290] “The memory module [second semiconductor device] ... coupled to the memory controller ... through the bus 1040”; [Fig. 1] The figure shows the memory cell array coupled to the memory controller; [para. 0051] “The control logic circuit 210 ... control operations of the semiconductor memory device”) one or more first signals comprising a first command to activate a row of a memory array of the second semiconductor die; ([para. 0072-0073] “receive the BANK_ADDR [one or more first signals] ... from the memory controller [transmit from the first interface] ... The bank control logic 230 may generate bank control signals in response to the bank address BANK_ADDR ... bank address BANK_ADDR is activated [activate a row of a memory array] in response to the bank control signals”)
receive, from the second interface based on transmitting the one or more first signals, one or more second signals comprising an alert message ([Kim, para. 0141] “the monitor logic [the second interface as it is an operation of the semiconductor memory device – see para. 0139 and para. 0122] ... may notify the memory controller 30 [receiving by the first interface] ... transiting a logic level of the alert signal ALRT [one or more second signals comprising an alert message]”) associated with a row hammer mitigation operation associated with the row of the memory array; and ([para. 0142] “In response to a transition of the alert signal ALRT, the memory controller 30 of FIG. 2 applies a refresh management command [associated with a row hammer mitigation operation] to the semiconductor memory device 200, and the monitor logic 650 may transit the alert signal ALRT to the second logic level in response to the hammer refresh operation based on the hammer address HADDR [associated with the row of the memory array]”)
transmit, to the second interface based on the alert message, ([Kim, para. 0106] “in response to a refresh management signal RFMS ... provide ... a hammer refresh signal HREF [refresh operation]”; [para. 0107] “The control logic circuit [transmit to the second interface] ... refresh management signal RFMS based on a refresh management command from the memory controller 30”; [para. 0142] “In response to a transition of the alert signal ALRT [based on the alert message], the memory controller 30 of FIG. 2 applies a refresh management command to the semiconductor memory device 200”) one or more third signals comprising a second command to refresh one or more rows of the memory array adjacent to the row of the memory array. ([Para. 0268; Fig. 29] “the hammer refresh address generator 440 may generate the hammer refresh address HREF_ADDR representing the address Ha1, Ha2, Ha3 and Ha4 of the rows that are physically adjacent to the row of the hammer address [to refresh one or more rows of the memory array adjacent to the row of the memory array] in synchronization with the activation time points t5 [first refresh operation], t6, t7 and t8 [one or more third signals indicating a second command to refresh] of the hammer refresh signal HREF”)
Kim does not clearly teach a first semiconductor die, a second semiconductor die, and a second semiconductor die coupled with the first semiconductor die.
However, Cho teaches a first semiconductor die, a second semiconductor die, and a second semiconductor die coupled with the first semiconductor die. ([Cho, Fig. 9] the memory controller [first semiconductor] included in the logic buffer die is coupled with the memory device including the RHC [second semiconductor] included in core dies 1-4; the row hammer control circuit corresponds to the semiconductor memory device 200)
It would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to have modified the elements disclosed by Kim with the teachings of Cho to include a first semiconductor die, a second semiconductor die, and a second semiconductor die coupled with the first semiconductor die. One of ordinary skill in the art would have been motivated to make this modification because such a modification allows for a high-performance interface for three-dimensional stacked memories allowing a wider bandwidth while consuming less power in a substantially smaller form factor. (Cho, para. 0090)
As per claim 15, Kim teaches claim 14.
Kim also teaches wherein the circuitry of the first interface is operable to: generate the one or more third signals ([Kim, para. 0106] “in response to a refresh management signal RFMS ... provide ... a hammer refresh signal HREF [generate the one or more third signals]”; [para. 0107] “The control logic circuit... refresh management signal RFMS based on a refresh management command from the memory controller 30 [the circuitry of the first interface operates to]”) comprising the second command, the second command indicating to refresh a first row of the memory array and a second row of the memory array that are different from the row ([para. 0268; Fig. 29] “the hammer refresh address generator 440 may generate the hammer refresh address HREF_ADDR representing the address Ha1, Ha2, Ha3 and Ha4 of the rows that are physically adjacent to the row of the hammer address [a first row of the memory array and a second row of the memory array that are different from the row] in synchronization with the activation time points t5 [first refresh operation], t6, t7 and t8 [second command indicating to refresh] of the hammer refresh signal HREF”) based on the alert message ([para. 0142] “In response to a transition of the alert signal ALRT [based on the alert message], the memory controller 30 of FIG. 2 applies a refresh management command to the semiconductor memory device 200”) indicating that a quantity of activations of the row satisfies a first threshold. ([Para. 0197] “row hammer management circuit 500 may perform the internal read-update-write operation to read the count data CNTD ... in response to the active count update command ... number of times of access is equal to or greater than the first reference number of times NTH1 and the second reference number of times NTH2 [a quantity of activations of the row satisfies a first threshold] ... notify the memory controller 30 [transmit to the first interface] ... by transiting a logic level of the alert signal ALRT from the second logic level to the first logic level”)
As per claim 16, Kim in view of Cho teaches claim 14.
Kim also teaches wherein circuitry of the first interface is operable to: generate the one or more third signals ([Kim, para. 0106] “in response to a refresh management signal RFMS ... provide ... a hammer refresh signal HREF [generate the one or more third signals]”; [para. 0107] “The control logic circuit... refresh management signal RFMS based on a refresh management command from the memory controller 30 [the circuitry of the first interface operates to]”) comprising the second command, the second command indicating to refresh a first set of rows of the memory array and a second set of rows that are different from the row ([para. 0268; Fig. 29] “the hammer refresh address generator 440 may generate the hammer refresh address HREF_ADDR representing the address Ha1, Ha2, Ha3 and Ha4 of the rows that are physically adjacent to the row of the hammer address [a first row of the memory array and a second row of the memory array that are different from the row] in synchronization with the activation time points t5 [first refresh operation], t6, t7 and t8 [second command indicating to refresh] of the hammer refresh signal HREF”) based on the alert message ([para. 0142] “In response to a transition of the alert signal ALRT [based on the alert message], the memory controller 30 of FIG. 2 applies a refresh management command to the semiconductor memory device 200”) indicating that a quantity of activations of the row satisfies a second threshold greater than a first threshold or indicating an error associated with a counter for counting activations of the row. ([Para. 0137] “the error flag EF associated with ... the count data CNTD [a counter for counting activations] of a corresponding memory cell row”; [para. 0197] “based on the error flag EF [an error associated with a counter for counting activations of the row] ... transiting a logic level of the alert signal ALRT from the second logic level to the first logic level”)
As per claim 17, Kim in view of Cho teaches claim 14.
Kim also teaches wherein the circuitry of the first interface is operable to: determine that the one or more second signals are associated with the row. ([Kim, para. 0156] “an active command ... denotes ... a memory cell”; [para. 0158] “The memory controller 30 [first circuitry of the first interface], in response to transition of the alert signal ALRT [the one or more first signals], may withhold application of [determine] the active command [the one or more memory arrays associated with the one or more first signals]”)
Kim does not clearly teach: determine that the one or more second signals are associated with the row based on a duration between transmitting the one or more first signals and receiving the one or more second signals.
However, Cho teaches determine that the one or more second signals are associated with the row based on a duration ([Cho, para. 0078] “When the row hammer monitoring time frame tREFi has not elapsed [based on a duration] ... control logic circuit 220 may perform a counter-based latch hold operation for the row hammer address RH_ADDR”; [para. 0079] “In operation S750, the control logic circuit 220 may perform a normal refresh and/or a target row refresh operation for the row hammer address RH_ADDR obtained [determine that the one or more second signals are associated with the row based on a duration]”) between transmitting the one or more first signals and receiving the one or more second signals. ([Para. 0096] “The row hammer control circuit RHC may monitor a row address that accesses a word line during a row hammer monitoring time frame [a duration], and when the number of times the word line is accessed [between transmitting the one or more first signals from the first interface] is greater than or equal to a threshold value, the row hammer control circuit (RHC) [the second interface] may determine the row address to be a row hammer address and store the row address [receiving the one or more second signals from the second interface]”)
It would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Kim and Cho for the same reasons as disclosed above.
As per claim 20, Kim teaches a method comprising: transmitting, from a first interface of a first semiconductor to ([Kim, para. 0289] “The memory controller ...implemented using ... a system-on-a-chip”; [para. 0062] “the memory controller 30 ... include a memory interface”; the memory controller/first semiconductor as a first semiconductor die connected with the semiconductor memory device/second semiconductor as a second semiconductor die is more clearly taught by Cho below) a second interface of a second semiconductor coupled with the first semiconductor, ([para. 0290] “The memory module [second semiconductor device] ... coupled to the memory controller ... through the bus 1040”; [Fig. 1] The figure shows the memory cell array coupled to the memory controller; [para. 0051] “The control logic circuit 210 ... control operations of the semiconductor memory device”) one or more first signals comprising a first command to activate a row of a memory array of the second semiconductor die; ([para. 0072-0073] “receive the BANK_ADDR [one or more first signals] ... from the memory controller [transmit from the first interface] ... The bank control logic 230 may generate bank control signals in response to the bank address BANK_ADDR ... bank address BANK_ADDR is activated [activate a row of a memory array] in response to the bank control signals”)
receiving, at the first interface from the second interface based on transmitting the one or more first signals, one or more second signals comprising an alert message ([Kim, para. 0141] “the monitor logic [the second interface as it is an operation of the semiconductor memory device – see para. 0139 and para. 0122] ... may notify the memory controller 30 [receiving by the first interface] ... transiting a logic level of the alert signal ALRT [one or more second signals comprising an alert message]”) associated a row hammer mitigation operation associated with the row of the memory array; and ([para. 0142] “In response to a transition of the alert signal ALRT, the memory controller 30 of FIG. 2 applies a refresh management command [associated with a row hammer mitigation operation] to the semiconductor memory device 200, and the monitor logic 650 may transit the alert signal ALRT to the second logic level in response to the hammer refresh operation based on the hammer address HADDR [associated with the row of the memory array]”)
transmitting, from the first interface to the second interface based on the alert message, ([Kim, para. 0106] “in response to a refresh management signal RFMS ... provide ... a hammer refresh signal HREF [refresh operation]”; [para. 0107] “The control logic circuit [transmit to the second interface] ... refresh management signal RFMS based on a refresh management command from the memory controller 30 [from the first interface]”; [para. 0142] “In response to a transition of the alert signal ALRT [based on the alert message], the memory controller 30 of FIG. 2 applies a refresh management command to the semiconductor memory device 200”) one or more third signals comprising a second command to refresh one or more rows of the memory array adjacent to the row of the memory array. ([Para. 0268; Fig. 29] “the hammer refresh address generator 440 may generate the hammer refresh address HREF_ADDR representing the address Ha1, Ha2, Ha3 and Ha4 of the rows that are physically adjacent to the row of the hammer address [to refresh one or more rows of the memory array adjacent to the row of the memory array] in synchronization with the activation time points t5 [first refresh operation], t6, t7 and t8 [one or more third signals indicating a second command to refresh] of the hammer refresh signal HREF”)
Kim does not clearly teach a first semiconductor die, a second semiconductor die, and a second semiconductor die coupled with the first semiconductor die.
However, Cho teaches a first semiconductor die, a second semiconductor die, and a second semiconductor die coupled with the first semiconductor die. ([Cho, Fig. 9] the memory controller [first semiconductor] included in the logic buffer die is coupled with the memory device including the RHC [second semiconductor] included in core dies 1-4; the row hammer control circuit corresponds to the semiconductor memory device 200)
It would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to have modified the elements disclosed by Kim with the teachings of Cho to include a first semiconductor die, a second semiconductor die, and a second semiconductor die coupled with the first semiconductor die. One of ordinary skill in the art would have been motivated to make this modification because such a modification allows for a high-performance interface for three-dimensional stacked memories allowing a wider bandwidth while consuming less power in a substantially smaller form factor. (Cho, para. 0090)
As per claim 21, Kim in view of Cho teaches claim 20.
Kim also teaches generating, by the first interface, the one or more third signals ([Kim, para. 0106] “in response to a refresh management signal RFMS ... provide ... a hammer refresh signal HREF [generate the one or more third signals]”; [para. 0107] “The control logic circuit... refresh management signal RFMS based on a refresh management command from the memory controller 30 [the circuitry of the first interface operates to]”) comprising the second command, the second command indicating to refresh a first row of the memory array and a second row of the memory array that are adjacent to the row ([para. 0268; Fig. 29] “the hammer refresh address generator 440 may generate the hammer refresh address HREF_ADDR representing the address Ha1, Ha2, Ha3 and Ha4 of the rows that are physically adjacent to the row of the hammer address [to refresh one or more rows of the memory array adjacent to the row of the memory array] in synchronization with the activation time points t5 [first refresh operation], t6, t7 and t8 [one or more third signals indicating a second command to refresh] of the hammer refresh signal HREF”) based on the alert message ([para. 0142] “In response to a transition of the alert signal ALRT [based on the alert message], the memory controller 30 of FIG. 2 applies a refresh management command to the semiconductor memory device 200”) indicating that a quantity of activations of the row satisfies a first threshold. ([Para. 0197] “row hammer management circuit 500 may perform the internal read-update-write operation to read the count data CNTD ... in response to the active count update command ... number of times of access is equal to or greater than the first reference number of times NTH1 and the second reference number of times NTH2 [a quantity of activations of the row satisfies a first threshold] ... notify the memory controller 30 [transmit to the first interface] ... by transiting a logic level of the alert signal ALRT from the second logic level to the first logic level”)
As per claim 22, Kim in view of Cho teaches claim 20.
Kim also teaches generating, by the first interface, the one or more third signals ([Kim, para. 0106] “in response to a refresh management signal RFMS ... provide ... a hammer refresh signal HREF [generate the one or more third signals]”; [para. 0107] “The control logic circuit... refresh management signal RFMS based on a refresh management command from the memory controller 30 [the circuitry of the first interface operates to]”) comprising the second command, the second command indicating to refresh a first set of rows of the memory array and a second set of rows that are adjacent to the row ([para. 0268; Fig. 29] “the hammer refresh address generator 440 may generate the hammer refresh address HREF_ADDR representing the address Ha1, Ha2, Ha3 and Ha4 of the rows that are physically adjacent to the row of the hammer address [to refresh one or more rows of the memory array adjacent to the row of the memory array] in synchronization with the activation time points t5 [first refresh operation], t6, t7 and t8 [one or more third signals indicating a second command to refresh] of the hammer refresh signal HREF”) based on the alert message ([para. 0142] “In response to a transition of the alert signal ALRT [based on the alert message], the memory controller 30 of FIG. 2 applies a refresh management command to the semiconductor memory device 200”) indicating that a quantity of activations of the row satisfies a second threshold greater than a first threshold or indicating an error associated with a counter for counting activations of the row. ([Para. 0137] “the error flag EF associated with ... the count data CNTD [a counter for counting activations] of a corresponding memory cell row”; [para. 0197] “based on the error flag EF [an error associated with a counter for counting activations of the row] ... transiting a logic level of the alert signal ALRT from the second logic level to the first logic level”)
As per claim 23, Kim in view of Cho teaches claim 20.
Kim also teaches determining, by the first interface, that the one or more second signals is associated with the row. ([Kim, para. 0156] “an active command ... denotes ... a memory cell”; [para. 0158] “The memory controller 30 [first circuitry of the first interface], in response to transition of the alert signal ALRT [the one or more second signals], may withhold application of [determine] the active command [the one or more memory arrays associated with the one or more second signals]”)
Kim does not clearly teach determining that the one or more second signals is associated with the row based on a duration between transmitting the one or more first signals and receiving the one or more second signals.
However, Cho teaches determining that the one or more second signals is associated with the row based on a duration between transmitting the one or more first signals and receiving the one or more second signals. ([Cho, para. 0078] “When the row hammer monitoring time frame tREFi has not elapsed [based on a duration] ... control logic circuit 220 may perform a counter-based latch hold operation for the row hammer address RH_ADDR”; [para. 0079] “In operation S750, the control logic circuit 220 may perform a normal refresh and/or a target row refresh operation for the row hammer address RH_ADDR obtained [determine that the one or more second signals are associated with the row based on a duration]”) between transmitting the one or more first signals and receiving the one or more second signals. ([Para. 0096] “The row hammer control circuit RHC may monitor a row address that accesses a word line during a row hammer monitoring time frame [a duration], and when the number of times the word line is accessed [between transmitting the one or more first signals] is greater than or equal to a threshold value, the row hammer control circuit (RHC) [the second interface] may determine the row address to be a row hammer address and store the row address [receiving the one or more second signals]”)
It would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Kim and Cho for the same reasons as disclosed above.
As per claim 25, Kim teaches an apparatus, comprising: ([Kim, para. 0045] “a memory system 20 [apparatus – see para. 0294 where the system is describes to be a number of different apparatuses] ... include a memory controller 30 [first semiconductor die] and a semiconductor memory device 200 [second semiconductor die]”)
a second semiconductor comprising a second interface, the second interface comprising circuitry operable to: ([Kim, para. 0290] “The memory module [second semiconductor/semiconductor memory device] ... coupled to the memory controller ... through the bus 1040 [second interface]”; [para. 0051] “The control logic circuit 210 ... control operations of the semiconductor memory device”)
receive, from a first interface of a first semiconductor, one or more first signals comprising a command to activate a row of a memory array of the second semiconductor; ([Kim, para. 0072-0073] “receive the BANK_ADDR [one or more first signals comprising a command to activate] ... from the memory controller 30 [from a first interface of a first semiconductor] ... The bank control logic 230 [an operation of the semiconductor memory device – see Fig. 3, and so receiving by the semiconductor memory device] may generate bank control signals in response to the bank address BANK_ADDR ... bank address BANK_ADDR is activated [activate a row of a memory array of the second semiconductor] in response to the bank control signals”)
increment a value of a counter associated with the row based on activating the row in accordance with the one or more first signals; ([Kim, para. 0091] “The row hammer management circuit 500 [second circuitry of the second interface] may count the number of times of access associated with each of the plurality of memory cell rows based on ... an active command from the memory controller 30 [activating the row in accordance with the one or more first signals]”; [para. 0125] “update the count data CNTD read from the count cells of the target memory cell row to provide an updated count data UCNTD by increasing the count data CNTD by one”)
read the value of the counter after incrementing the value of the counter; and ([Kim, para. 0125] “update the count data CNTD read from the count cells of the target memory cell row to provide an updated count data UCNTD by increasing the count data CNTD by one, which is read from the count cells of the target memory cell row”))
transmit, to the first interface based on reading the value of the counter, one or more second signals comprising an alert message associated a row hammer mitigation operation associated with the row. ([Kim, para. 0197] “row hammer management circuit 500 may perform the internal read-update-write operation to read the count data CNTD [based on reading the value of the counter counter] ... in response to the active count update command ... number of times of access is equal to or greater than the first reference number of times NTH1 and the second reference number of times NTH2... notify the memory controller 30 [transmit to the first interface] ... by transiting a logic level of the alert signal ALRT from the second logic level to the first logic level [one or more second signals comprising an alert message]”; [para. 0142] “In response to a transition of the alert signal ... applies a refresh management command [row hammer mitigation operation]”)
Kim does not clearly teach a second semiconductor die receiving signals from a first semiconductor die.
However, Cho teaches a second semiconductor die receiving signals from a first semiconductor die. ([Cho, Fig. 9] the memory controller [first semiconductor] is included in the logic buffer die and the memory device including the RHC [second semiconductor] are included in core dies 1-4; [para. 0093] “The host device 110 [memory controller/first semiconductor die – see Fig. 1 and para. 0025: “host device 110 ... include a memory controller 112 that controls data transmission and data reception”] may transmit the command/address and the data ... through to the first channel CH1 to the eighth channel”; [para. 0096] “CH1 to CH8 ... include a row hammer circuit RHC”)
It would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to have modified the elements disclosed by Kim with the teachings of Cho to include a first semiconductor die, a second semiconductor die, and a second semiconductor die coupled with the first semiconductor die. One of ordinary skill in the art would have been motivated to make this modification because such a modification allows for a high-performance interface for three-dimensional stacked memories allowing a wider bandwidth while consuming less power in a substantially smaller form factor. (Cho, para. 0090)
As per claim 26, Kim in view of Cho teaches claim 25.
Kim also teaches wherein the circuitry of the second interface further operable to: receive, from the first interface based on the alert message, ([Kim, para. 0106] “in response to a refresh management signal RFMS ... provide ... a hammer refresh signal HREF”; [para. 0107] “The control logic circuit [the circuitry of the second interface] ... refresh management signal RFMS based on a refresh management command from the memory controller 30 [receive from the first interface]”; [para. 0142] “In response to a transition of the alert signal ALRT [based on the alert message], the memory controller 30 of FIG. 2 applies a refresh management command to the semiconductor memory device 200”) one or more third signals comprising a second command to refresh one or more rows of the memory array adjacent to the row of the memory array; and ([Para. 0268; Fig. 29] “the hammer refresh address generator 440 may generate the hammer refresh address HREF_ADDR representing the address Ha1, Ha2, Ha3 and Ha4 of the rows that are physically adjacent to the row of the hammer address [to refresh one or more rows of the memory array adjacent to the row of the memory array] in synchronization with the activation time points t5 [first refresh operation], t6, t7 and t8 [one or more third signals indicating a second command to refresh] of the hammer refresh signal HREF”)
refresh the one or more rows based on the second command. ([Kim, para. 0251] "The semiconductor memory device 200 performs a hammer refresh operation two victim memory cell rows physically adjacent to a memory cell row corresponding to the hammer address, in response to the refresh management command”)
As per claim 27, Kim in view of Cho teaches claim 25.
Kim also teaches wherein the alert message indicates that the value of the counter satisfies a first threshold value. ([Kim, para. 0197] “row hammer management circuit 500 may perform the internal read-update-write operation to read the count data CNTD ... in response to the active count update command ... number of times of access is equal to or greater than the first reference number of times ... NTH2 [counter satisfies a first threshold value] ... by transiting a logic level of the alert signal ALRT from the second logic level to the first logic level”)
Kim does not clearly teach the circuitry of the second interface further operable to: reset a first portion of the counter based on the value of the counter satisfying the first threshold value; and increment a second portion of the counter based on resetting the first portion of the counter.
However, Cho teaches the circuitry of the second interface further operable to: reset a first portion of the counter based on the value of the counter satisfying the first threshold value; and ([Cho, para. 0053] “The comparator 530 [by the second interface] may output an output signal of a logic high level [reset] when the incremented access count value CNT+1 that is output from the counter 510 [value of the counter] and transmitted through the logic circuit 520 is greater than or equal to the threshold value THRESHOLD [satisfying the first threshold value] ... As an output CO signal of a logic high level of the comparator 530 is provided as a reset RST signal of the counter 510 ... the counter 510 may be reset to a zero value”)
increment a second portion of the counter based on resetting the first portion of the counter. ([Cho, para. 0049] “The control logic circuit 220 [second interface] may control the refresh control circuit 240 to perform a normal refresh operation by incrementing a refresh counter value by +1 [increment a second portion of the counter] in response to a refresh command [based on resetting]”)
It would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Kim and Cho for the same reasons as disclosed above.
As per claim 28, Kim in view of Cho teaches claim 25.
Kim also teaches wherein the alert message indicates that the value of the counter satisfies a second threshold value greater than a first threshold value. ([Kim, para. 0128] “The register 530 may store a first reference number of times NTH1 and a second reference number of times NTH2 smaller than the first reference number of times NTH1”; [para. 0197] “the row hammer management circuit 500, in response to ... number of times of access is equal to or greater than the first reference number of times NTH1 [satisfies a second threshold] ... notify the memory controller 30 ... by transiting a logic level of the alert signal ALRT from the second logic level to the first logic level”)
Kim does not clearly teach the circuitry of the second interface further operable to: reset the counter based on the value of the counter satisfying the second threshold value.
However, Cho teaches the circuitry of the second interface further operable to: reset the counter based on the value of the counter satisfying the second threshold value. ([Cho, para. 0053] “The comparator 530 [by the second interface] may output an output signal of a logic high level [reset] when the incremented access count value CNT+1 that is output from the counter 510 [value of the counter] and transmitted through the logic circuit 520 is greater than or equal to the threshold value THRESHOLD [satisfying the second threshold value as the threshold value is settable/changeable – see para. 0075] ... As an output CO signal of a logic high level of the comparator 530 is provided as a reset RST signal of the counter 510 ... the counter 510 may be reset to a zero value”; in view of Kim above, this is the counter satisfying the second threshold value as the alert signal indicates the counter satisfying the second threshold value)
It would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Kim and Cho for the same reasons as disclosed above.
As per claim 30, Kim teaches a method comprising: receiving, at a second interface of a second semiconductor from a first interface of a first semiconductor operable to couple with the second semiconductor, one or more first signals comprising a first command to activate a row of a memory array of the second semiconductor; ([Kim, para. 0072-0073] “receive [a method comprising receiving] the BANK_ADDR [one or more first signals comprising a command to activate] ... from the memory controller 30 [from a first interface of a first semiconductor] ... The bank control logic 230 [an operation of the semiconductor memory device – see Fig. 3, and so receiving by the second semiconductor memory device – see para. 0051: “The control logic circuit 210 ... control operations of the semiconductor memory device”] may generate bank control signals in response to the bank address BANK_ADDR ... bank address BANK_ADDR is activated [activate a row of a memory array of the second semiconductor] in response to the bank control signals”; [para. 0290] “The memory module [second semiconductor/semiconductor memory device] ... coupled to the memory controller [first semiconductor] ... through the bus 1040 [second interface]”)
incrementing, by the second interface, a value of a counter associated with the row based on activating the row in accordance with the one or more first signals; ([Kim, para. 0091] “The row hammer management circuit 500 [second circuitry of the second interface] may count the number of times of access associated with each of the plurality of memory cell rows based on ... an active command from the memory controller 30 [activating the row in accordance with the one or more first signals]”; [para. 0125] “update the count data CNTD read from the count cells of the target memory cell row to provide an updated count data UCNTD by increasing the count data CNTD by one”)
reading, by the second interface, the value of the counter after incrementing the value of the counter; and ([Kim, para. 0125] “update the count data CNTD read from the count cells of the target memory cell row to provide an updated count data UCNTD by increasing the count data CNTD by one, which is read from the count cells of the target memory cell row”))
transmitting, from the second interface to the first interface based on reading the value of the counter, one or more second signals comprising an alert message associated a row hammer mitigation operation associated with the row. ([Kim, para. 0197] “row hammer management circuit 500 may perform the internal read-update-write operation to read the count data CNTD [based on reading the value of the counter counter] ... in response to the active count update command ... number of times of access is equal to or greater than the first reference number of times NTH1 and the second reference number of times NTH2... notify the memory controller 30 [transmit to the first interface] ... by transiting a logic level of the alert signal ALRT from the second logic level to the first logic level [one or more second signals comprising an alert message]”; [para. 0142] “In response to a transition of the alert signal ... applies a refresh management command [row hammer mitigation operation]”)
Kim does not clearly teach a first semiconductor die, a second semiconductor die, and a second semiconductor die coupled with the first semiconductor die.
However, Cho teaches a first semiconductor die, a second semiconductor die, and a second semiconductor die coupled with the first semiconductor die. ([Cho, Fig. 9] the memory controller [first semiconductor] included in the logic buffer die is coupled with the memory device including the RHC [second semiconductor] included in core dies 1-4; the row hammer control circuit corresponds to the semiconductor memory device 200)
It would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to have modified the elements disclosed by Kim with the teachings of Cho to include a first semiconductor die, a second semiconductor die, and a second semiconductor die coupled with the first semiconductor die. One of ordinary skill in the art would have been motivated to make this modification because such a modification allows for a high-performance interface for three-dimensional stacked memories allowing a wider bandwidth while consuming less power in a substantially smaller form factor. (Cho, para. 0090)
Claims 8 and 29 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Cho as applied to claims 5 and 25 above and in view of Muchheria et al. (US Pub. 2021/0035649) (hereinafter “Muchheria”)
As per claim 8, Kim in view of Cho teaches claim 5.
Kim also teaches wherein the one or more first signals indicate an error associated with the counter, ([Kim, para. 0137] “the error flag EF associated with ... the count data CNTD [a counter for counting activations] of a corresponding memory cell row”; [para. 0197] “based on the error flag EF [an error associated with a counter for counting activations of the row] ... transiting [indicate the error] a logic level of the alert signal ALRT [one or more first signals] from the second logic level to the first logic level”) the system further operable to: generate, by the first interface, the one or more second signals indicating the refresh operation for ([para. 0067] “The RFM control logic 100 ... applies a refresh management command [generate the one or more second signals indicating the refresh operation] to the semiconductor memory device 200 through the memory interface 60 [by the first interface] in response to a transition of the alert signal ALRT from the semiconductor memory device 200 such that the semiconductor memory device 200 performs a hammer refresh operation on one or more victim memory cell rows which are physically adjacent to a memory cell row corresponding to the hammer address [for a first set of addresses]”; [para. 0197] “the row hammer management circuit 500, in response to ... number of times of access is equal to or greater than the first reference number of times NTH1 ... notify the memory controller 30 ... by transiting a logic level of the alert signal ALRT from the second logic level to the first logic level”) a first set of addresses that are different from the address and a second set of addresses that are different from the address based on the one or more first signals indicating the error. ([Para. 0251] “applies a refresh command RFM ... a hammer refresh operation two victim memory cell rows [a first set of addresses and a second set of addresses that are different from the address] physically adjacent to a memory cell row corresponding to the hammer address, in response to the refresh management command RFM [based on the one or more first signals as described above]”)
Kim in view of Cho does not clearly teach reset, by the second interface, the counter based on the error.
However, Muchheria teaches reset, by the second interface, the counter based on the error. ([Muchheria, para. 0040] “If the error threshold criterion is satisfied [based on the error] ... the processing device [second interface in view of Kim above] relocates the data from the block to another block and resets the read count value of read counter”)
It would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to have modified the elements disclosed by Kim in view of Cho with the teachings of Muchheria to include reset, by the second interface, the counter based on the error. One of ordinary skill in the art would have been motivated to make this modification because error rate is correlated to a read disturb which causes the threshold of read operations to be met significantly faster, resulting in the performance of excessive memory management operations, and this modification reduces the memory space overhead thereby increasing performance, decreasing power consumption and freeing system resources for other functionality. (Muchheria, para. 0017-0020)
As per claim 29, Kim in view of Cho teaches claim 25.
Kim also teaches wherein the alert message indicates an error associated with the counter. ([Kim, para. 0137] “the error flag EF associated with ... the count data CNTD [a counter for counting activations] of a corresponding memory cell row”; [para. 0197] “based on the error flag EF [an error associated with a counter for counting activations of the row] ... transiting [indicate the error] a logic level of the alert signal ALRT [one or more first signals] from the second logic level to the first logic level”)
Kim in view of Cho does not clearly teach the circuitry of the second interface further operable to: reset the counter based on identifying the error.
However, Muchheria teaches the circuitry of the second interface further operable to: reset the counter based on identifying the error. ([Muchheria, para. 0040] “If the error threshold criterion is satisfied [based on the error] ... the processing device [circuitry of the second interface in view of Kim above] relocates the data from the block to another block and resets the read count value of read counter”)
It would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Kim, Cho and Muchheria for the same reasons as disclosed above.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Cho as applied to claim 1 above and in view of Bang (US Pub. 2018/0158507) (hereinafter “Bang”)
As per claim 10, Kim in view of Cho teaches claim 1.
Kim also teaches wherein the one or more first signals are associated with a first address of the one or more memory arrays ([Kim, para. 0142] “In response to a transition of the alert signal ALRT [one or more first signals], the memory controller ... applies a refresh management command to the semiconductor memory device 200 ... the hammer refresh operation based on the hammer address HADDR [associated with one or more addresses of the one or more memory arrays]”) and a second address of the one or more memory arrays adjacent to the first address. ([Para. 0152] “the address of the word-lines WLd is provided to the refresh control circuit 400 as the hammer address HADDRa [first signals are associated with one or more first signals] and the refresh control circuit 400 outputs addresses of the word-lines WLc and WLe, which are physically adjacent to the word-line WLd as hammer refresh addresses HREF_ADDRa_1 [a second address of the one or more memory arrays adjacent to the first address]”)
Kim in view of Cho does not clearly teach and wherein the first circuitry of the first interface is operable to: determine the one or more addresses for the refresh operation to be adjacent to the first address or the second address and to exclude the first address and the second address based on the first address and the second address being adjacent.
However, Bang teaches wherein the first circuitry of the first interface is operable to: determine the one or more addresses for the refresh operation to be adjacent to the first address or the second address and to exclude the first address and the second address based on the first address and the second address being adjacent. ([Bang, para. 0140] “the semiconductor memory device 800 [first circuitry of the first interface] may map a normal wordline ... corresponding to the hammer address HADD the one or more addresses to a first redundancy wordline [determine the one more addresses for the refresh operation – see para. 0132: “perform the hammer refresh operation based on the hammer address HADD”] and disable second redundancy wordlines RW1 and RW3 adjacent to the first redundancy wordline RW2 such that the second redundancy wordlines RW1 and RW3 are not mapped to an access address [exclude the first address and the second address based on the first address and the second address being adjacent] ... In this case, the normal wordline NW3 corresponding to the hammer address HADD is not actually accessed, and thus, the adjacent normal wordlines NW2 and NW4 do not require the hammer refresh operation”)
It would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to have modified the elements disclosed by Kim in view of Cho with the teachings of Bang to include wherein the first circuitry of the first interface is operable to: determine the one or more addresses for the refresh operation to be adjacent to the first address or the second address and to exclude the first address and the second address based on the first address and the second address being adjacent. One of ordinary skill in the art would have been motivated to make this modification because this method distributes the burden of the hammer refresh operation, thus reducing a size of the memory device and enhancing overall performance of the memory system. (Bang, para. 0147)
Claims 12 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Cho as applied to claims 1 and 14 above and in view of Jones et al. (US Pub. 2019/0103147) (hereinafter “Jones”)
As per claim 12, Kim in view of Cho teaches claim 1.
Kim in view of Cho does not clearly teach wherein the one or more second signals indicating the refresh operation is based on the one or more addresses being associated with a spare row of the one or more memory arrays.
However, Jones teaches wherein the one or more second signals indicating the refresh operation is based on the one or more addresses being associated with a spare row of the one or more memory arrays. ([Jones para. 0061] “determine whether the target row of memory [based on the one more addresses] has been repaired [associated with a spare row of the one or more memory addresses as a spare row is a repaired row – see para. 0091 of the instant application] and if so, provide a MATCH control signal [the one or more second signals] indicating ... target row of memory to be refreshed ... and further cause any unrepaired rows of memory physically adjacent the interior primary row of memory that is the target row of memory to be refreshed [one or more second signals indication the refresh operation]”)
It would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to have modified the elements disclosed by Kim in view of Cho with the teachings of Jones to include wherein the one or more second signals indicating the refresh operation is based on the one or more addresses being associated with a spare row of the one or more memory arrays. One of ordinary skill in the art would have been motivated to make this modification because in this manner, accesses of malfunctioning and/or damaged rows may be avoided and refreshed. (Jones, para. 0047)
As per claim 19, Kim in view of Cho teaches claim 14.
Kim in view of Cho does not clearly teach wherein the second command to refresh the one or more rows is based on whether the row is a spare row of the memory array.
However, Jones teaches wherein the one or more second signals indicating the refresh operation is based on the one or more addresses being associated with a spare row of the one or more memory arrays. ([Jones para. 0061] “determine whether the target row of memory [based on the one more addresses] has been repaired [associated with a spare row of the one or more memory addresses as a spare row is a repaired row – see para. 0091 of the instant application] and if so, provide a MATCH control signal [the one or more second signals] indicating ... target row of memory to be refreshed ... and further cause any unrepaired rows of memory physically adjacent the interior primary row of memory that is the target row of memory to be refreshed [one or more second signals indication the refresh operation]”)
It would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Kim, Cho and Jones for the same reasons as disclosed above.
Claims 18 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Cho as applied to claims 14 and 20 above and in view of Lee et al. (US 10,236,035) (hereinafter “Lee”)
As per claim 18, Kim in view of Cho teaches claim 14.
Kim also teaches wherein the circuitry operable to transmit the one or more third signals is further operable to: transmit the one or more third signals based on receiving the alert message. ([Kim, para. 0142] “In response to a transition of the alert signal ALRT [based on receiving the alert message], the memory controller 30 of FIG. 2 applies a refresh management command to the semiconductor memory device 200”; [para. 0268; Fig. 29] “the hammer refresh address generator 440 may generate the hammer refresh address HREF_ADDR representing the address Ha1, Ha2, Ha3 and Ha4 of the rows that are physically adjacent to the row of the hammer address [to refresh one or more rows of the memory array adjacent to the row of the memory array] in synchronization with the activation time points t5 [first refresh operation], t6, t7 and t8 [one or more third signals indicating a second command to refresh] of the hammer refresh signal HREF”)
Kim in view of Cho does not clearly teach receiving a second alert message associated with a second row hammer mitigation operation associated with a second row adjacent to the row.
However, Lee teaches receiving a second alert message ([Lee, col. 7, ln. 23-25] “The refresh device 14 refreshes the refresh unit 32 according to a first refresh rate REF0 except for the neighbor memory rows 33 and 35 in response to a first event [a second alert message – col. 7, ln. 60-61 where an event indicates function abnormally and lack reliability]”; the event is a “second alert message” as the refresh of the memory row 34 is done in accordance to a control device that determines a quantity of access memory rows is greater than a threshold [see col. 7, ln. 7-12] which is the “first alert message” as explained by Kim above) associated with a second row hammer mitigation operation associated with a second row adjacent to the row. ([Col. 7, ln. 23-32] “The refresh device 14 refreshes the refresh unit 32 according to a first refresh rate REF0 except for the neighbor memory rows 33 and 35 in response to a first event, in which ... the refresh device 14 refreshes the neighbor memory rows 33 and 35 according to a second refresh rate REF0′ greater than the first refresh rate REF0 in response to the first event [a second row hammer mitigation operation associated with a second row adjacent to the row])
It would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to have modified the elements disclosed by Kim in view of Cho with the teachings of Lee to include receiving a second alert message associated with a second row hammer mitigation operation associated with a second row adjacent to the row. One of ordinary skill in the art would have been motivated to make this modification because in this way only the neighbor rows are signaled and refreshed so that adverse effects on the rows are alleviated/eliminated and not all the non-accessed memory rows are refreshed and as a result, the memory is relatively power efficient. (Lee, col. 7, ln. 40-46)
As per claim 24, Kim in view of Cho teaches claim 20.
Kim also teaches receiving, at the first interface from the second interface, an alert message wherein the one or more third signals is transmitted based on receiving the alert message. ([Kim, para. 0142] “In response to a transition of the alert signal ALRT [based on receiving the alert message], the memory controller 30 of FIG. 2 [receiving the ALRT at the first interface from the second interface] applies a refresh management command to the semiconductor memory device 200”; [para. 0268; Fig. 29] “the hammer refresh address generator 440 may generate the hammer refresh address HREF_ADDR representing the address Ha1, Ha2, Ha3 and Ha4 of the rows that are physically adjacent to the row of the hammer address [to refresh one or more rows of the memory array adjacent to the row of the memory array] in synchronization with the activation time points t5 [first refresh operation], t6, t7 and t8 [one or more third signals indicating a second command to refresh] of the hammer refresh signal HREF”)
Kim in view of Cho does not clearly teach receiving a second alert message associated with a second row hammer mitigation operation associated with a second row adjacent to the row; and wherein the one or more third signals is transmitted based on the second alert message.
However, Lee teaches receiving a second alert message ([Lee, col. 7, ln. 23-25] “The refresh device 14 refreshes the refresh unit 32 according to a first refresh rate REF0 except for the neighbor memory rows 33 and 35 in response to a first event [a second alert message – col. 7, ln. 60-61 where an event indicates function abnormally and lack reliability]”; the event is a “second alert message” as the refresh of the memory row 34 is done in accordance to a control device that determines a quantity of access memory rows is greater than a threshold [see col. 7, ln. 7-12] which is the “first alert message” as explained by Kim above) associated with a second row hammer mitigation operation associated with a second row adjacent to the row; and ([Col. 7, ln. 23-32] “The refresh device 14 refreshes the refresh unit 32 according to a first refresh rate REF0 except for the neighbor memory rows 33 and 35 in response to a first event, in which ... the refresh device 14 refreshes the neighbor memory rows 33 and 35 according to a second refresh rate REF0′ greater than the first refresh rate REF0 in response to the first event [a second row hammer mitigation operation associated with a second row adjacent to the row])
wherein the one or more third signals is transmitted based on the second alert message. ([Col. 7, ln. 29-31] “the refresh device 14 refreshes the neighbor memory rows 33 and 35 according to a second refresh rate REF0′ [one or more third signals] greater than the first refresh rate REF0 in response to the first event [based on the second alert message])
It would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Kim and Lee for the same reasons as disclosed above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Lim (US Pub. 2025/0239290) discloses preventing row-hammer attacks where an occurrence of a row-hammer attack is checked where if a counter is greater than or equal to a threshold, a refresh operation is activated, and the memory device and the controller for the memory device are on separate dies.
Shin et al. (US Pub. 2019/0333573) discloses where a refresh controller controls memory cell array blocks and executes two adjacent memory cell array blocks.
Bains et al. (US Pub. 2014/0095780) discloses distributed row hammer tracking where detection logic in the memory device alerts the memory controller when a row hammer event is detected, and where multiple alerts may be generated on the same pin in order to trigger a refresh operation where the memory controller obtains the address from the memory device.
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/ZHE LIU/Examiner, Art Unit 2493