DETAILED ACTION
The following claims are pending in this office action: 1-31
Claims 1, 15, 22, 27 and 31 are independent claims
The following claims are amended: 5, 8, 17, 22 and 30
The following claims are new: -
The following claims are cancelled: -
Claims 1-31 are rejected. This rejection is FINAL.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
RESPONSE TO ARGUMENTS
Applicant’s arguments in the amendment filed 05/28/2026 have been fully considered but are not persuasive. The reasons are set forth below.
Applicant’s position is that the memory module of Kim does not teach the claimed “second semiconductor die.” Applicant explains:
… The Office Action alleges that the memory modules of Kim are relevant to the claimed "second semiconductor die." However, a memory module that has multiple discrete semiconductor chips, as described in Kim, does not teach or suggest a single "second semiconductor die" that includes each of "one or more memory arrays," "a second counter," and "a second interface coupled with the first interface, the one or more memory arrays, and the second counter," as recited in independent claim 1. (Arguments, pg. 12)
For example, Kim describes that each of the chips 110 to 117 and 131 is configured with respective sets of pins. See, e.g., id. [0023]. That is, Kim's memory module chips are not integrated together as part of the same semiconductor die, but instead are described as separate chips. But because the memory modules of Kim include a combination of multiple distinct chips, the memory modules of Kim do not teach or suggest "a second semiconductor die" that itself includes both "one or more memory arrays" and "a second counter," as claimed. (Arguments, pg. 12)
For example, the RCD chip 180, which the Office Action alleges to be relevant to a "second interface," is yet another physically separate chip of a memory module of Kim, distinct from both the data chips and the counter chip. See, e.g., id. [0074]. (Argument, pg. 13)
If an Applicant disagrees with any factual findings by the Office, an effective traverse of a rejection based wholly or partially on such findings must include a reasoned statement explaining why the Applicant believes the Office has erred substantively as to the factual findings. A mere statement or argument that the Office has not established a prima facie case of obviousness will not be considered substantively adequate to rebut the rejection or an effective traverse of the rejection under 37 CFR 1.111(b). See MPEP §2141. During patent prosecution, “claims must be given their broadest reasonable interpretation in light of the specification… Though understanding the claim language may be aided by explanations contained in the written description, it is important not to import into a claim limitations that are not part of the claim.” See MPEP § 2111. "A person of ordinary skill in the art is also a person of ordinary creativity, not an automaton." KSR Int'l Co. sv. Teleflex Inc., 550 U.S. 398, 421, 82 USPQ2d 1385, 1397 (2007). "[I]n many cases a person of ordinary skill will be able to fit the teachings of multiple patents together like pieces of a puzzle." Id. at 420, 82 USPQ2d 1397. Office personnel may also take into account "the inferences and creative steps that a person of ordinary skill in the art would employ." Id. at 418, 82 USPQ2d at 1396. Also see MPEP 2141.03. One cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Kim discloses a memory module, a semiconductor device, that includes memory cell arrays 110-117 and 120-127 (see para. 0033 and Fig. 2), a row hammer counter chip 131 (see para. 0061) and an RCD chip 180 that receives signals from a memory controller (see para. 0077). Below is the memory module represented in Fig. 5 of Kim which explicitly discloses these elements on one memory module.
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Additionally, Hanham discloses “SRAM 220 is a memory device coupled to the controller” and “SRAM 220 can be an on-chip memory.” In combination, Kim and Hanham discloses that the memory module/device is an on-chip device, or a semiconductor die in accordance with Applicant’s specification. See para. 0022 of the instant application where “memory dies” and “memory chips” are used interchangeably.
Here, Applicant argues that the memory of Kim is not a “second semiconductor die” as it does not comprise “one or more memory arrays”, “a second counter” and a “second interface.” However, as the memory module of Kim, or memory chip/die in view of Hanham shows, it clearly includes multiple memory arrays 110-117, counter 131 and interface 180. Applicant also argues that the memory module cannot be considered a semiconductor die as it itself contains separate semiconductor dies/chips distinct from one another. However, this is contrary to Applicant’s own specification. Para. 0033 of the instant specification notes: “The system 200 illustrates an example of a die.” Fig. 2 of the instant application shows that the dies include sensors, non-volatile storage, memory arrays, interface blocks, controllers, logic blocks, and a host processor. Para. 0175 of the instant application notes “the various illustrative blocks and modules described in connection with the disclosure herein may be implemented ... with a processor... A processor may be an example of a microprocessor.” The BRI of the claim includes that the semiconductor die includes microprocessors which are other dies. Applicant cannot reasonably argue that the claimed dies do not include other dies when this is explicitly disclosed in the instant application. Thus, Applicant’s arguments that a second semiconductor die is not disclosed, is not persuasive.
Applicant also argues Kim does not teach “second signaling indicating an error associated with a first counter ... for counting activations of the row of the memory array.”
… For example, Kim's ECC-based error detection is not the same as "an error associated with a first counter" at least because Kim's ECC does not detect an error of any counter. Rather, Kim's ECC is limited to detecting errors in user data stored in the data chips 110 to 117. See, e.g., id. [0071]. Kim does not teach or suggest any "signaling indicating an error associated with" the row hammer counter chip 131 or any other counter. Because an error detected by reading ECC bits of user data is unrelated to any counter for counting activations, Kim does not teach or suggest "second signaling indicating an error associated with a first counter . .. for counting activations of the row," as claimed. Because Kim fails to teach or suggest "second signaling indicating an error," Kim also fails to teach or suggest "activat[ing] a second counter of the first semiconductor die for counting activations of the row of the memory array based on receiving the second signaling indicating the error," as recited in independent claim 15. (Arguments, pg. 15)
Kim discloses that DRAM-based systems experience “intermittent failure due to heavy work load” that are “traced to repetitive access to a row of single memory cells, also known as row hammers” Para. 0004. “The counter memory cells C110 to C117 connected to the first word line WL1 may store the number of times of access for activating the memory cell row of the first word line WL1 of each of the data chips 110 to 117” where the memory cells are “in the row hammer chip 131.” Para. 0049. Furthermore, when the memory controller 20 detects an error in the data of the data chips 110 to 117, the memory controller 20 may correct a 1-bit error in the 512-bit data of the first memory channel 310 by using the 64-bit ECC bit. Para. 0071. Thus, Kim teaches an EEC bit that indicates an error (a signaling error) in the data of the data chips, where the error results from repetitive access (associated with a count) to a row of single memory cells, where a counter stores the number of times of access (thus making the error associated with the counter) for activating the data of the data chips (for counting activations of the row of the memory array).
Here, Applicant believes a data error detected in user data is not the same and does not teach or suggest “an error associated with a first counter ... for counting activation. However, Kim clearly teaches that errors in the data are cause by repetitive access to memory cells or “row hammers.” Applicant ignores that the counters are explicitly in a “row hammer chip” which are clearly at least used to detect these errors in the user data. As counters in a “row hammer chip” are clearly linked/associated with the row hammer failures in the data chips due to repeated access, it is unreasonable to argue that the error is entirely unassociated with the counter without further limiting the scope of the association. Thus, Applicant’s argument that a second signaling indicating an error associated with a first counter for counting activations of the row of the memory array is not disclosed is not persuasive.
In conclusion, as Applicant’s arguments do not reasonably explain the supposed errors in the rejection, they are not persuasive and are not substantively adequate to rebut the rejection or an effective traverse of the rejection.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US Pub. 2023/0205428) (hereinafter “Kim”) in view Hanham et al. (US Pub. 2023/0047029) (hereinafter “Hanham”).
As per claim 1, Kim teaches a system, comprising: ([Kim, para. 0058; Fig. 5] “Fig. 5 is a diagram illustrating a memory system”)
A first semiconductor, comprising: ([Kim, para. 0059; Fig. 5] “a memory system 4 ... include ... a memory controller 20”)
a first interface, ([Kim, para. 0028] “The memory controller 20 ... communicatively coupled through a ... interface used to perform memory access operations”) the first interface comprising first circuitry operable to transmit access signaling; and ([para. 0027] “The memory controller 20 may control the memory module ... according to a memory request ... The memory controller 20 may control a write operation or a read operation performed on the memory chips 110 to 117 and 131 by providing a command and an address to the memory module ... data for a write operation and data read may be transmitted/received between the memory controller 20 and the memory module ... These memory access operations are performed through a memory bus 30 [circuitry operable to transmit access signaling] between the memory controller 20 and the memory module”)
a first counter; and ([Kim, para. 0029] “The memory controller 20 ... include a row hammer counter 21”)
a second semiconductor coupled with the first semiconductor, the second semiconductor comprising: ([Kim, para. 0028] “The memory controller 20 and the memory module [second semiconductor] ... communicatively coupled”; [para. 0059] “The memory module implemented as a double data rate synchronous dynamic random-access memory dual in-line memory module ... DDR DIMM”)
one or more memory arrays; ([Kim, Fig. 5] the memory module includes memory chips 110 to 117; [para. 0033] “Fig. 2 shows the memory chip 110 as a representative memory chip among the memory chips 110 to 117”; [Fig. 2] the memory chip includes memory cell arrays)
a second counter; and ([Kim, para. 0061] “The memory module ... include ... row hammer counter chip [second counter] ... 131”)
a second interface coupled with the first interface, the one or more memory arrays, and the second counter, ([Kim, para. 0074] “the memory module ... include ... RCD chip”; [para. 0077] “the RCD chip [second interface] ... receive a command, an address, a clock signal and a control signal from the memory controller 20 through the memory bus 30 [the first interface] ... distributing the received signals to ... The memory chips 110 to 117 [the one or more memory arrays] ... 131 [second counter]”) the second interface comprising second circuitry operable to access the one or more memory arrays based on receiving the access signaling, ([para. 0041] “The control logic circuit 220 [second interface comprising second circuitry] ... receive a clock signal CLK and the command CMD [based on receiving access signaling] ... generate control signals for controlling [accessing]... the memory cell array”)
wherein the first circuitry of the first interface is operable to transmit refresh signaling to the second interface indicating a refresh operation associated with one or more addresses of the one or more memory arrays ([Kim, para. 0044] “The memory controller 20 [first circuitry of the first interface] ... issue a normal refresh command [transmit refresh signaling indicating a refresh operation] based on row-hammer-risky row information ... The memory controller 20 may transmit an address signal of one or more memory cell rows [associated with one or more addresses of the one or more memory arrays] ... together with a refresh command”) based on a quantity of access operations on the one or more memory arrays indicated by the first counter or by the second counter. ([Para. 0042] “the control logic circuit 220 ... receive the number of times of access of each of the memory cell rows in the memory cell array 200 of the memory device 110 [a quantity of access operations on the one or more memory arrays] from the row hammer counter chip 131 [indicated by the first or second counter] ... determines whether the number of times of access of any of the memory cell rows is greater than or equal to a threshold, and identifies a memory cell row for which the number of times of access is equal to or greater than the threshold as a row-hammer-risky row [based on the counter, as row-hammer risky row information is used to issue the refresh command]”)
Kim does not clearly teach a first semiconductor die; and a second semiconductor die coupled with the first semiconductor die.
However, Hanham teaches a first semiconductor die; and ([Hanham, para. 0038] “SRAM ... includes a shared memory controller [first semiconductor]”; [para. 0038] “the SRAM ... an on-chip SRAM memory [a die]”)
a second semiconductor die coupled with the first semiconductor die. ([Hanham, para. 0029] “Each of the ... memory devices [second semiconductor] ... includes one or more individual ... dies”; [Fig. 1] the two dies are coupled)
It would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to have modified the elements disclosed by Kim with the teachings of Hanham to include a first semiconductor die; and a second semiconductor die coupled with the first semiconductor die. One of ordinary skill in the art would have been motivated to make this modification because such a configuration advantageously reduces the physical footprint of the memory controller and increases the speed of memory operations. (Hanham, para. 0048)
As per claim 13, Kim in view of Hanham teaches claim 1.
Kim also teaches wherein the first interface comprises the first counter of the first semiconductor. ([Kim, para. 0028] “The memory controller 20 ... communicatively coupled through a ... interface used to perform memory access operations”; [para. 0029] “The memory controller 20 may include a row hammer counter 21 [first counter of the first semiconductor] for monitoring a row hammer for all memory cell rows of each of the data chips 110 to 117 [memory access operations, and thus, the first interface])
Kim does not clearly teach the first semiconductor as a semiconductor die.
However, Hanham teaches the first semiconductor as a semiconductor die. ([Hanham, para. 0038] “SRAM ... includes a shared memory controller [first semiconductor]”; [para. 0038] “the SRAM ... an on-chip SRAM memory [a die]”)
It would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Kim and Hanham for the same reasons as disclosed above.
As per claim 14, Kim in view of Hanham teaches claim 1.
Kim also teaches wherein the refresh operation is for a set of one or more addresses different from an address of the one or more memory arrays that is associated with the first counter or the second counter. ([Kim, para. 0044] “The memory controller 20 ... issue a normal refresh command based on row-hammer-risky row information ... The memory controller 20 may transmit an address signal of one or more memory cell rows physically adjacent to [one or more addresses different from] a row-hammer-risky row [an address of the one or more memory arrays that is associated with the first counter or the second counter] to the memory device 110 together with a refresh command .... The memory device 110 may refresh the one or more memory cell rows physically adjacent to the row-hammer-risky row”; [para. 0042] “the number of times of access of each of the memory cell rows in the memory cell array 200 of the memory device 110 from the row hammer counter chip 131 ... determines ... a row-hammer-risky row [an address of the one or more memory arrays that is associated with the first counter or the second counter]”)
Claims 2-3 and 5-12, and 15-31 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Hanham and further in view of Agarwal et al. (US Pub. 2024/0112723) (hereinafter “Agarwal”)
As per claim 2, Kim in view of Hanham teaches claim 1.
Kim also teaches the second circuitry of the second interface is further operable to transmit first signaling to the first interface based on receiving the access signaling, the first signaling indicating an error ([Kim, para. 0071] “the memory controller 20 is to transmit a particular command to the memory module 100, [based on receiving the access signaling] and is to receive [transmit to the first interface] information in the ECC [error correction code] bits [first signaling as it indicates an error – see para. 0054: the occurrence of an error ... perform error correction”] stored in the first ECC chip 151 during memory processing with the first memory channel 310 [second circuitry of the second interface]”) associated with the second counter. ([Para. 0048] “the row hammer counter chip 131 [second counter] ... include ... the data chips 110 to 117”; [para. 0071] “the memory controller 20 detects an error in the [associated with] data of the data chips 110 to 117 [second counter]”)
Kim in view of Hanham does not teach the first circuitry of the first interface is further operable to activate the first counter based on receiving the first signaling.
However, Agarwal teaches the first circuitry of the first interface is further operable to activate ([Agarwal, para. 0072] “the row hammer detection system 110 ... activate the sampling mode [first counter] by setting an always sampling register (ASR) to an “on” value” [based on the first signaling]; [para. 0118] “errors [the first signaling] ... result in ... the row hammer detection system 110 ... engage the sampling mode”) the first counter based on receiving the first signaling. ([Para. 0085] “counting record 602 that the row hammer detection system 110 may maintain [activate the first counter] while engaged in the sampling mode [based on receiving the first signaling]”)
It would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to have modified the elements disclosed by Kim in view of Hanham with the teachings of Agarwal to include the first circuitry of the first interface is further operable to activate the first counter based on receiving the first signaling. One of ordinary skill in the art would have been motivated to make this modification because a traditional system utilizing one counter can easily become overwhelmed, where this approach enables the systems described to meet the performance needs of a memory controller which would be difficult or impossible with conventional approaches. (Agarwal, para. 0003; para. 0020)
As per claim 3, Kim in view of Hanham and Agarwal teaches claim 2.
Kim also teaches wherein, to activate the first counter, the first circuitry of the first interface is operable to: ([Kim, para. 0090] “the memory system 1 may perform initialization [activate] ... the memory controller 20 [first circuitry of the first interface] ... perform an initial setting operation [activate] according to a preset method ... initialization of the memory system [activation of the first counter, as the row hammer counter is within the memory system - see Fig. 1]”)
associate the first counter with an address of the one or more memory arrays that is associated with the second counter. ([Kim, para. 0031] “the row hammer counter 21 [first counter] and the row hammer chip 131 [second counter] ... provide a per-row hammer tracking [associated with] ... the data chips 110 to 117 [the one or more memory arrays] ... thereby preventing a missing hammer address [associated with an address of the one or more memory arrays]”; [para. 0048] “BANK ... include the data chips 110 to 117; [Fig. 2] the data banks are the one or more memory arrays)
Kim in view of Agarwal does not clearly teach allocate a portion of a memory array of the first semiconductor die for the first counter.
However, Hanham teaches allocate a portion of a memory array of the first semiconductor die for the first counter. ([Hanham, para. 0055] “the overflow counter ... associated respectively with a corresponding one of the buffer memory blocks [a portion of a memory array of the first semiconductor die -see para. 0041 and Fig. 3]”; [para. 0078] “At 752, the example system allocates an overflow counter [a portion of a memory array of the first semiconductor die] corresponding to a reference counter [for the first counter]”)
It would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to have modified the elements disclosed by Kim in view of Agarwal with the teachings of Hanham to include allocate a portion of a memory array of the first semiconductor die for the first counter. One of ordinary skill in the art would have been motivated to make this modification because by doing so, the speed of the operation of electronic memory device can be advantageously increased by assigning/allocating/deallocating counters to minimize or eliminate reference counter overflows and it is advantageous to control allocation and deallocation of the buffer array in order to reduce cost and complexity. (Hanham, para. 0022, para. 0025 and para. 0043)
As per claim 5, Kim in view of Hanham and Agarwal teaches claim 2.
Kim also teaches wherein the first circuitry of the first interface is further operable to: ([Kim, para. 0027] “The memory controller 20 may control the memory module”)
transmit, to the second interface, access signaling; ([Kim, para. 0027] “The memory controller 20 ... control a write operation or a read operation ... by providing a command and an address [transmit access signaling] to the memory module [second interface]”)
transmit the refresh signaling to the second interface based on the value of the first counter satisfying one or more thresholds; and ([Kim, para. 0093] “the memory controller 20 may count a number of times ... the data chips 110 to 117 are accessed ... by using the row hammer counter 21 [based on the value of the first counter]”; [para. 0095] “when the number of times of access ... is equal to or greater than the threshold, a memory cell row ... may be target-refreshed”)
reset one or more portions of the first counter ([Kim, para. 0068] “The row hammer counter 21 [first counter] may store the number of times of access of the word lines of each of the data chips 110 to 117”; [para. 0096] “in operation S1060 ... the memory controller 20 may reset the number of accesses to each word line ... the data chips 110 to 117 to ... 0”) based on transmitting the refresh signaling. ([Para. 0095] “In operation S1050 ... a memory cell row ... may be target-refreshed”; [Fig. 10] As the counter resets based on step 1050, the reset is “based on” transmitting the refresh signaling)
Kim in view of Hanham does not clearly teach transmit, after receiving the first signaling, second access signaling; and increment a value of the first counter based on transmitting the second access signaling.
However, Agarwal teaches transmit, after receiving the first signaling, second access signaling; and ([Agarwal, para. 0072] “the row hammer detection system 110 ... activate the sampling mode by setting an always sampling register (ASR) to an “on” value” [the first signaling]”; [para. 0075] “Upon activating the sampling mode ... row hammer detection system 110 may perform an act 520 of detecting an activation of a next address [second access signaling]”)
increment a value of the first counter based on transmitting the second access signaling. ([Agarwal, para. 0095] “the row hammer detection system 110 may continue tracking address and count values 612a-n [the first counter] for corresponding memory sub-banks ... a number of activation counts similar to the examples described above in connection with FIGS. 2-4”; [para. 0061] “Upon detecting activation of a next address, [based on transmitting the second access signaling] the row hammer detection system 110 may ... perform an act 410 of incrementing or otherwise iterating a count for the row entry [increment a value of the first counter]”)
It would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to have modified the elements disclosed by Kim in view of Hanham with the teachings of Agarwal to include transmit, after receiving the first signaling, second access signaling; and increment a value of the first counter based on transmitting the second access signaling. One of ordinary skill in the art would have been motivated to make this modification because this parallelism allows for fast access and update of the respective entries within the activation count record. (Agarwal, para. 0052)
As per claim 6, Kim in view of Hanham and Agarwal teaches claim 2.
Kim also teaches the second circuitry of the second interface is further operable to transmit, second signaling to the first interface indicating that a value of the second counter satisfies a threshold. ([Kim, para. 0042] “the number of times of access of each of the memory cell rows in the memory cell array 200 of the memory device 110 from the row hammer counter chip 131 [value of the second counter] ... The control logic circuit 220 may include a row hammer control circuit 210 that determines whether the number of times of access of any of the memory cell rows is greater than or equal to a threshold [satisfies a threshold], and identifies ... as a row-hammer-risky row [second signaling]”; [para 0044] “the row hammer control circuit 210 [second circuitry of the second interface] may transmit information on the detected row-hammer-risky row [second signaling] to the memory controller 20 [to the first interface]”)
Kim in view of Hanham does not clearly teach transmit, after transmitting the first signaling, second signaling to the first interface indicating that a value of the second counter satisfies a threshold; and the first circuitry of the first interface is further operable to deactivate the first counter based on receiving the second signaling.
However, Agarwal teaches transmit, after transmitting the first signaling, second signaling ([Agarwal, para. 0070] “the row hammer detection system ... perform an act 510 of activating ... a sampling mode [transmitting the first signaling]”; [para. 0084] “re-engage the counting mode [transmit second signaling – see para. 0072: “the ASR bit may act as a signal ... to implement ... counting mode”] after engaging the sampling mode [after transmitting the first signaling]”) to the first interface ([para. 0072] “the row hammer detection system [first interface] may be configured to check the ASR bit [transmit the bit to the first interface]”) indicating that a value of the second counter satisfies a threshold; and ([para. 0033] “the activation count table [second counter] ... additionally include a spillover count [a value of the second counter – see Fig. 3]”; [para. 0121-122] “engaging a counting mode [second signaling] ... by maintaining ... a spillover count determining exceeds a threshold count associated with a likelihood of an aggressor row [a threshold]”)
the first circuitry of the first interface is further operable to ([Agarwal, para. 0021] “a memory controller [first circuitry of the first interface] transitions between a counting mode and a sampling mode”)
deactivate the first counter based on receiving the second signaling. ([Agarwal, para. 0112] “re-engaging ... the counting mode [based on receiving the second signaling] ... transition from the sampling mode [deactivate the first counter]”; [para. 0125] “Engaging the sampling mode ... including maintaining a spill overflow count ... while the sampling mode is engaged”; as the spill overflow count/first counter [see Fig. 6] is maintained only while the sampling mode is engaged, it is necessarily deactivated once the sampling mode is transitioned to the counting mode)
It would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to have modified the elements disclosed by Kim in view of Hanham with the teachings of Agarwal to include transmit, after transmitting the first signaling, second signaling to the first interface indicating that a value of the second counter satisfies a threshold; and the first circuitry of the first interface is further operable to deactivate the first counter based on receiving the second signaling. One of ordinary skill in the art would have been motivated to make this modification because such a technique provides an effective approach in switching between operational modes as engaging the sampling mode/first counter indefinitely may be an undesirable approach when a row hammer attach is not currently ongoing. (Agarwal, para. 0024)
As per claim 7, Kim in view of Hanham and Agarwal teaches claim 2.
Kim in view of Hanham does not clearly teach wherein the first circuitry of the first interface is further operable to: deactivate the first counter based on a value of the first counter failing to satisfy a threshold within a duration.
However, Agarwal teaches wherein the first circuitry of the first interface is further operable to: ([Agarwal, para. 0021] “a memory controller [first circuitry of the first interface] transitions between a counting mode and a sampling mode”)
deactivate the first counter based on a value of the first counter failing to satisfy a threshold within a duration. ([Agarwal, para. 0105] “where the sampling mode countdown hits zero [within a duration] and where the spill overflow count is greater than zero [failing to satisfy a threshold within a duration] ... the row hammer detection system 110 may re-engage the counting mode [deactivate the first counter]”; [para. 0125] “Engaging the sampling mode ... including maintaining a spill overflow count ... while the sampling mode is engaged”; as the spill overflow count/first counter is maintained only while the sampling mode is engaged, it is necessarily deactivated once the sampling mode is transitioned to the counting mode)
It would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Kim, Hanham and Agarwal for the same reasons as disclosed above.
As per claim 8, Kim in view of Hanham and Agarwal teaches claim 7.
Kim does not clearly teach wherein, to deactivate the first counter, the first circuitry of the first interface is operable to: deallocate a portion of a memory array of the first semiconductor die for the first counter; and disassociate the first counter from an address of the one or more memory arrays.
However, Haham teaches deallocate a portion of a memory array of the first semiconductor die for the first counter. ([Hanham, para. 0055] “the overflow counter ... associated respectively with a corresponding one of the buffer memory blocks [a portion of a memory array of the first semiconductor die -see para. 0041 and Fig. 3]”; [para. 0078] “At 960, the example system deallocates an overflow counter [a portion of a memory array] corresponding to a reference counter [for the first counter]”)
It would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Kim and Hanham for the same reasons as disclosed above.
Kim in view of Hanham does not clearly teach wherein, to deactivate the first counter, the first circuitry of the first interface is operable to: disassociate the first counter from an address of the one or more memory arrays.
However, Agarwal teaches wherein, to deactivate the first counter, the first circuitry of the first interface is operable to: ([Agarwal, para. 0021] “a memory controller [first circuitry of the first interface] transitions between a counting mode and a sampling mode [deactivate the first counter]”)
disassociate the first counter ([Agarwal, para. 0125] “Engaging the sampling mode ... including maintaining a spill overflow count ... while the sampling mode is engaged”; as the spill overflow count/first counter [see Fig. 6] is maintained only while the sampling mode is engaged, it is necessarily deactivated/disassociated once the sampling mode is transitioned to the counting mode) from an address of the one or more memory arrays. ([Para. 0085] “the counting record 602 [first counter] ... include ... row address ... for one or more memory sub-banks”; as the first counter [see Fig. 6] is maintained only while the sampling mode is engaged, it and associated addresses are necessarily deactivated/disassociated once the sampling mode is transitioned to the counting mode)
It would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Kim, Hanham and Agarwal for the same reasons as disclosed above.
As per claim 9, Kim in view of Hanham and Agarwal teaches claim 2.
Kim in view of Hanham does not clearly teach wherein the first circuitry of the first interface is further operable to: transmit the refresh signaling based on the first signaling indicating the error associated with the second counter.
However, Agarwal teaches wherein the first circuitry of the first interface is further operable to: ([Agarwal, para. 0035] “the memory controller ... issuing a refresh command indicating the memory address as a predicted aggressor row of a row hammer attack”) transmit the refresh signaling ([para. 0079] “perform an act 550 of generating a refresh command”) based on the first signaling indicating the error associated with the second counter. ([Para. 0072] “the row hammer detection system 110 ... activate the sampling mode [first counter] by setting an always sampling register (ASR) to an “on” value” [based on the first signaling]; [para. 0118] “errors [the first signaling] ... result in ... the row hammer detection system 110 ... engage the sampling mode”)
It would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to have modified the elements disclosed by Kim in view of Hanham with the teachings of Agarwal to include wherein the first circuitry of the first interface is further operable to: transmit the refresh signaling based on the first signaling indicating the error associated with the second counter. One of ordinary skill in the art would have been motivated to make this modification because such a technique allows minimization of a total number of vulnerable refresh windows, decreasing transitions which reduces the probability that a row hammer attack will successfully corrupt data on the memory hardware. (Agarwal, para. 0025; and para. 0090)
As per claim 10, Kim in view of Hanham and Agarwal teaches claim 9.
Kim also teaches wherein the second circuitry of the second interface is further operable to: ([Kim, para. 0064] “The RH chips ... of the memory channels [second circuitry of the second interface] ... store the numbers of times accessing [portions of the second counter]”)
reset one or more portions of the second counter. ([Kim, para. 0091] “The memory controller 20 may store the number of times of access ... as “0” [reset] ... in the counter memory cells C110 to C117 of the row hammer counter chip 131 [one or more portions of the second counter”)
Kim in view of Hanham does not clearly teach reset one or more portions of the second counter based on the error associated with the second counter.
However, Agarwal teaches reset one or more portions of the second counter based on the error associated with the second counter. ([Agarwal, para. 0067] “after 32 milliseconds have passed without the spillover count [based on the error associated with the second counter] hitting or exceeding the threshold ... row hammer detection system 110 ... reset the counts [one or more portions of the second counter – see para. 0059 that describes the count is of a corresponding activation count table]”; [para. 0065] “the spillover count ... a metric for determining the counting method [second counter] is becoming overwhelmed [an error associated with the second counter]”)
It would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to have modified the elements disclosed by Kim in view of Hanham with the teachings of Agarwal to include reset one or more portions of the second counter based on the error associated with the second counter. One of ordinary skill in the art would have been motivated to make this modification because such a modification solve problems associated with detecting and mitigating row hammer attacks this enables the row hammer detection system to track activations. (Agarwal, para. 0018; and para. 0020)
As per claim 11, Kim in view of Hanham teaches claim 1.
Kim also teaches wherein the second circuitry of the second interface is further operable to: read a value of the second counter based on accessing the one or more memory arrays; and ([Kim, para. 0042] “The control logic circuit 220 [the second circuitry of the second interface] may receive [read] the number of times of access of each of the memory cell rows in the memory cell array 200 [based on accessing one or more memory arrays] of the memory device 110 from the row hammer counter chip 131 [a value of the second counter]”)
transmit first signaling to the first interface based on identifying the error, the first signaling indicating the error ([Kim, para. 0071] “the memory controller 20 ... is to receive [transmit to the first interface] information in the ECC [error correction code/based on identifying the error] bits [first signaling as it indicates an error – see para. 0054: the occurrence of an error ... perform error correction”] stored in the first ECC chip 151 during memory processing with the first memory channel 310 [transmitting by the second circuitry of the second interface]”) associated with the second counter. ([Para. 0048] “the row hammer counter chip 131 [second counter] ... include ... the data chips 110 to 117”; [para. 0071] “the memory controller 20 detects an error in the [associated with] data of the data chips 110 to 117 [second counter]”)
Kim in view of Hanham does not clearly teach identify an error associated with the second counter based on reading the value of the second counter.
However, Agarwal teaches identify an error associated with the second counter based on reading the value of the second counter. ([Agarwal, para. 0062-0064] “the row hammer detection system 110 may query [based on reading] the counts of the table [the value of the second counter] ... where the row hammer detection system 110 determines that there is not a table entry that is equal to the spillover count ... incrementing or otherwise iterating the spillover count ... where the spillover count is greater ... a threshold count, the row hammer detection system 110 ... activating a sampling mode [identify an error associated with the second counter]”; [para. 0065] “the spillover count may be considered as a metric for determining whether the counting method is becoming overwhelmed by a potential row hammer attack [an error associated with the second counter]”)
It would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Kim, Hanham and Agarwal for the same reasons as disclosed above.
As per claim 12, Kim in view of Hanham and Agarwal teaches claim 11.
Kim also teaches wherein the second circuitry of the second interface is operable to identify the error ([Kim, para. 0054] “the memory controller 20 recognizes the occurrence of an error in the memory module”) based on one or more parity bits of the second counter, one or more error detection bits of the second counter, a cyclic redundancy check operation based on an indication of the second counter, or any combination thereof. ([Para. 0061] “The error detection ... include a cyclic redundancy check”; [para. 0071] “memory controller 20 detects an error in the data of the data chips 110 to 117 [an indication of the second counter]”; [para. 0091] “The memory controller 20 may store the number of times of access of each word line WL1 to WLm of the data chips 110 to 117 [an indication] ... the counter memory cells C110 to C117 of the row hammer counter chip 131 [of the second counter]”)
As per claim 15, Kim teaches an apparatus, comprising: ([Kim, para. 0025] “the host may be ... a computer [apparatus]”)
a first semiconductor ([Kim, para. 0026] “the memory controller 20 [first semiconductor] corresponds to a component provided in the processing unit of the host”) comprising a first interface, ([Kim, para. 0028] “The memory controller 20 ... communicatively coupled through a ... interface used to perform memory access operations”) the first interface comprising circuitry operable to: ([para. 0027] “The memory controller 20 may control the memory module ... These memory access operations are performed through a memory bus 30 [circuitry operable to transmit access signaling] between the memory controller 20 and the memory module”)
transmit, to a second interface of a second semiconductor coupled with the first semiconductor, first signaling comprising a first command to activate a row of a memory array of the second semiconductor; ([Kim, para. 0027] “The memory controller 20 may control the memory module ... according to a memory request ... The memory controller 20 may control a write operation or a read operation performed on the memory chips 110 to 117 and 131 by providing a command and an address to the memory module [first signaling comprising a first command to activate a row of a memory array of the second semiconductor – see Fig. 2] ... data for a write operation and data read may be transmitted/received between the memory controller 20 and the memory module ... These memory access operations are performed through a memory bus 30; [para. 0028] “The memory controller 20 and the memory module [second semiconductor] ... communicatively coupled”; [para. 0059] “The memory module implemented as a double data rate synchronous dynamic random-access memory dual in-line memory module ... DDR DIMM”; [para. 0041] “The control logic circuit 220 [second interface comprising second circuitry] ... receive a clock signal CLK and the command CMD [based on receiving access signaling] ... generate control signals for controlling [activating]... the memory cell array [row of a memory array of the second semiconductor]”)
receive, from the second interface based on transmitting the first signaling, second signaling indicating an error ([Kim, para. 0071] “the memory controller 20 is to transmit a particular command to the memory module 100, [based on transmitting the first signaling] and is to receive [transmit to the first interface] information in the ECC [error correction code] bits [second signaling as it indicates an error – see para. 0054: “the occurrence of an error ... perform error correction”] stored in the first ECC chip 151 during memory processing with the first memory channel 310 [from the second interface]”) associated with a first counter ([para. 0048] “the row hammer counter chip 131 [first counter] ... include ... the data chips 110 to 117”; [para. 0071] “the memory controller 20 detects an error in the [associated with] data of the data chips 110 to 117 [first counter]”) of the second semiconductor for counting activations of the row of the memory array; and ([para. 0042] “the control logic circuit 220 ... receive the number of times of access [for counting activations] of each of the memory cell rows in the memory cell array 200 of the memory device 110 from the row hammer counter chip 131 [first counter]”)
transmit, to the second interface based on a value of the second counter or the second signaling indicating the error, third signaling comprising a second command to refresh one or more rows of the memory array different from the row. ([Kim, para. 0044] “The memory controller 20 ... issue [transmit] a normal refresh command [third signal comprising a second command to refresh] based on row-hammer-risky row information [based on a value of the second counter – see para 0022: “identify a memory cell row with more than a threshold number of times of access, among the number of times each of the memory cell rows are accessed ... as a row-hammer-risky row” and para. 0029: “row hammer counter 21 ... count a number of times each of the memory cell rows of the data chips 110 to 117 is accessed”] ... The memory controller 20 may transmit an address signal of one or more memory cell rows physically adjacent to [one or more addresses different from] a row-hammer-risky row to the memory device 110 [to the second interface] together with a refresh command .... The memory device 110 may refresh the one or more memory cell rows physically adjacent to the row-hammer-risky row”)
Kim does not clearly teach a first semiconductor die; a second semiconductor die coupled with the first semiconductor die; and activate a second counter of the first semiconductor die for counting activations of the row of the memory array based on receiving the second signaling indicating the error.
However, Hanham teaches a first semiconductor die; and ([Hanham, para. 0038] “SRAM ... includes a shared memory controller [first semiconductor]”; [para. 0038] “the SRAM ... an on-chip SRAM memory [a die]”)
a second semiconductor die coupled with the first semiconductor die. ([Hanham, para. 0029] “Each of the ... memory devices [second semiconductor] ... includes one or more individual ... dies”; [Fig. 1] the two dies are coupled)
It would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to have modified the elements disclosed by Kim with the teachings of Hanham to include a first semiconductor die; and a second semiconductor die coupled with the first semiconductor die. One of ordinary skill in the art would have been motivated to make this modification because such a configuration advantageously reduces the physical footprint of the memory controller and increases the speed of memory operations. (Hanham, para. 0048)
Kim in view of Hanham does not clearly teach activate a second counter of the first semiconductor die for counting activations of the row of the memory array based on receiving the second signaling indicating the error.
However, Agarwal teaches activate a second counter of the first semiconductor for counting activations of the row of the memory array based on receiving the second signaling indicating the error. ([Agarwal, para. 0072] “the row hammer detection system 110 [first semiconductor] ... activate the sampling mode [second counter] by setting an always sampling register (ASR) to an “on” value” [based on the second signaling]; [para. 0118] “errors [the second signaling indicating the error] ... result in ... the row hammer detection system 110 ... engage the sampling mode”; [para. 0085] “counting record 602 [second counter] that the row hammer detection system 110 may maintain while engaged in the sampling mode [based on receiving the second signaling]”; [para. 0095] “the row hammer detection system 110 may continue tracking ... count values 612a-n [second counter – see Fig. 6] for corresponding memory sub-banks ... a number of activation counts”)
It would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to have modified the elements disclosed by Kim in view of Hanham with the teachings of Agarwal to include activate a second counter of the first semiconductor die for counting activations of the row of the memory array based on receiving the second signaling indicating the error. One of ordinary skill in the art would have been motivated to make this modification because a traditional system utilizing one counter can easily become overwhelmed, where this approach enables the systems described to meet the performance needs of a memory controller which would be difficult or impossible with conventional approaches. (Agarwal, para. 0003; para. 0020)
As per claim 16, allocate Kim in view of Hanham and Agarwal teaches claim 15.
Kim also teaches wherein to activate the second counter, the circuitry is operable to: ([Kim, para. 0090] “the memory system 1 may perform initialization [activate] ... the memory controller 20 [the circuitry] ... perform an initial setting operation [activate] according to a preset method ... initialization of the memory system [activation of the second counter, as the row hammer counter is within the memory system– see Fig. 1]”)
associate the second counter with the row. ([Kim, para. 0031] “the row hammer counter 21 [second counter] ... provide a per-row hammer tracking [associated with] ... the data chips 110 to 117 [the row]”)
Kim in view of Agarwal does not clearly teach allocate a portion of a second memory array of the first semiconductor die for the second counter.
However, Hanham teaches allocate a portion of a second memory array of the first semiconductor die for the second counter. ([Hanham, para. 0055] “the overflow counter ... associated respectively with a corresponding one of the buffer memory blocks [a portion of a second memory array of the first semiconductor die - see para. 0041 and Fig. 3]”; [para. 0078] “At 752, the example system allocates an overflow counter [a portion of a second memory array of the first semiconductor die] corresponding to a reference counter [for the second counter]”)
It would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Kim, Hanham and Agarwal for the same reasons as disclosed above.
As per claim 17, Kim in view of Hanham and Agarwal teaches claim 15.
Kim also teaches wherein the circuitry is further operable to: ([Kim, para. 0027] “The memory controller 20 [circuitry] may control the memory module”)
transmit, to the second interface, a command to activate the row; ([Kim, para. 0027] “The memory controller 20 ... control a write operation or a read operation ... by providing a command and an address [transmit a command to activate the row] to the memory module [second interface]”)
transmit the third signaling to the second interface based on the value of the second counter satisfying one or more thresholds; and ([Kim, para. 0093] “the memory controller 20 may count a number of times ... the data chips 110 to 117 are accessed ... by using the row hammer counter 21 [based on the value of the second counter]”; [para. 0095] “when the number of times of access ... is equal to or greater than the threshold, a memory cell row ... may be target-refreshed”)
reset one or more portions of the second counter ([Kim, para. 0068] “The row hammer counter 21 [second counter] may store the number of times of access of the word lines of each of the data chips 110 to 117”; [para. 0096] “in operation S1060 ... the memory controller 20 may reset the number of accesses to each word line ... the data chips 110 to 117 to ... 0”) based on transmitting the third signaling. ([Para. 0095] “In operation S1050 ... a memory cell row ... may be target-refreshed”; [Fig. 10] As the counter resets based on step 1050, the reset is “based on” transmitting the refresh signaling)
Kim in view of Hanham does not clearly teach transmit, after activating the second counter, fourth signaling comprising a third command to activate the row; and increment the value of the second counter based on transmitting the fourth signaling to the second interface.
However, Agarwal teaches transmit, after activating the second counter, fourth signaling comprising a third command to activate the row; and ([Agarwal, para. 0072] “the row hammer detection system 110 ... activate the sampling mode [after activating the second counter] by setting an always sampling register (ASR) to an “on” value””; [para. 0075] “Upon activating the sampling mode ... row hammer detection system 110 may perform an act 520 of detecting an activation of a next address [fourth signaling comprising a third command to activate the row as the address is associated with a row hammer attack]”)
increment the value of the second counter based on transmitting the fourth signaling to the second interface. ([Agarwal, para. 0095] “the row hammer detection system 110 may continue tracking address and count values 612a-n [the second counter] for corresponding memory sub-banks ... a number of activation counts similar to the examples described above in connection with FIGS. 2-4”; [para. 0061] “Upon detecting activation of a next address, [based on transmitting the fourth signaling in view of Kim as per above] the row hammer detection system 110 may ... perform an act 410 of incrementing or otherwise iterating a count for the row entry [increment a value of the first counter]”)
It would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Kim, Hanham and Agarwal for the same reasons as disclosed above.
As per claim 18, Kim in view of Hanham and Agarwal teaches claim 15.
Kim also teaches receive, from the second interface, fourth signaling indicating that a value of the first counter satisfies a threshold. ([Kim, para. 0042] “the number of times of access of each of the memory cell rows in the memory cell array 200 of the memory device 110 from the row hammer counter chip 131 [value of the first counter] ... The control logic circuit 220 may include a row hammer control circuit 210 that determines whether the number of times of access of any of the memory cell rows is greater than or equal to a threshold [satisfies a threshold], and identifies ... as a row-hammer-risky row [fourth signaling]”; [para 0044] “the row hammer control circuit 210 [from second interface] may transmit information on the detected row-hammer-risky row [fourth signaling] to the memory controller 20 [receive by the circuitry]”)
Kim in view of Hanham does not clearly teach receive, after receiving the second signaling, fourth signaling indicating that a value of the first counter satisfies a threshold; and deactivate the second counter based on receiving the fourth signaling.
However, Agarwal teaches receive, after receiving the second signaling, fourth signaling ([Agarwal, para. 0070] “the row hammer detection system ... perform an act 510 of activating ... a sampling mode [receiving the second signaling - see para. 0072: “the ASR bit may act as a signal ... to implement ... sampling mode]”; [para. 0084] “re-engage the counting mode [receiving fourth signaling – see para. 0072: “the ASR bit may act as a signal ... to implement ... counting mode”] after engaging the sampling mode [after receiving the second signaling]”) indicating that a value of the first counter satisfies a threshold; and ([para. 0033] “the activation count table [first counter] ... additionally include a spillover count [a value of the first counter – see Fig. 3]”; [para. 0121-122] “engaging a counting mode [fourth signaling] ... by maintaining ... a spillover count determining exceeds a threshold count associated with a likelihood of an aggressor row [a threshold]”)
deactivate the second counter based on receiving the fourth signaling. ([Agarwal, para. 0112] “re-engaging ... the counting mode [based on receiving the fourth signaling] ... transition from the sampling mode [deactivate the second counter]”; [para. 0125] “Engaging the sampling mode ... including maintaining a spill overflow count ... while the sampling mode is engaged”; as the spill overflow count/second counter [see Fig. 6] is maintained only while the sampling mode is engaged, it is necessarily deactivated once the sampling mode is transitioned to the counting mode)
It would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Kim, Hanham and Agarwal for the same reasons as disclosed above.
As per claim 19, Kim in view of Hanham and Agarwal teaches claim 15.
Kim in view of Hanham does not clearly teach deactivate the second counter based on the value of the second counter failing to satisfy a threshold within a duration.
However, Agarwal teaches deactivate the second counter based on the value of the second counter failing to satisfy a threshold within a duration. ([Agarwal, para. 0105] “where the sampling mode countdown hits zero [within a duration] and where the spill overflow count is greater than zero [failing to satisfy a threshold within a duration] ... the row hammer detection system 110 may re-engage the counting mode [deactivate the first counter]”; [para. 0125] “Engaging the sampling mode ... including maintaining a spill overflow count ... while the sampling mode is engaged”; as the spill overflow count/second counter is maintained only while the sampling mode is engaged, it is necessarily deactivated once the sampling mode is transitioned to the counting mode)
It would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Kim, Hanham and Agarwal for the same reasons as disclosed above.
As per claim 20, Kim in view of Hanham and Agarwal teaches claim 15.
Kim also teaches wherein the first interface comprises the second counter. ([Kim, para. 0028] “The memory controller 20 ... communicatively coupled through a ... interface used to perform memory access operations”; [para. 0029] “The memory controller 20 may include a row hammer counter 21 [second counter of the first semiconductor] for monitoring a row hammer for all memory cell rows of each of the data chips 110 to 117 [memory access operations, and thus, the first interface])
As per claim 21, Kim in view of Hanham and Agarwal teaches claim 15.
Kim in view of Agarwal does not clearly teach wherein the circuitry is operable to transmit the third signaling in response to receiving the second signaling indicating the error, the one or more rows of the memory array different from the row comprising a first set of rows and a second set of rows different from the first set of rows based on the second signaling indicating the error.
However, Agarwal teaches wherein the circuitry is operable to ([Agarwal, para. 0035] “the memory controller ... issuing a refresh command indicating the memory address as a predicted aggressor row of a row hammer attack”) transmit the third signaling in response to receiving the second signaling ([para. 0079] “perform an act 550 of generating a refresh command [third signaling]”; this occurs after transitioning to sampling mode/second signaling – see Fig. 5) indicating the error, ([para. 0072] “the row hammer detection system 110 ... activate the sampling mode by setting an always sampling register (ASR) to an “on” value” [in response to the second signaling]; [para. 0118] “errors ... result in [indicate] ... the row hammer detection system 110 ... engage the sampling mode [indicating the error]”) the one or more rows of the memory array different from the row comprising a first set of rows and a second set of rows different from the first set of rows based on the second signaling indicating the error. ([Para. 0081] “the refresh command includes an indication of a blast radius ... For example, the row hammer detection system 110 may generate and issue a refresh command indicating a row that is suspected as an aggressor row in combination with a blast radius of a predetermined number of rows ... two rows ... indicate both the aggressor row [the one or more rows of the memory array] and row(s) on either side of the aggressor row [different from the row comprising a first set of rows and a second set of rows]... should be refreshed in response to the refresh command [based on the second signaling indicating the error as the signaling indicating the error triggers the refresh command]”)
It would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Kim, Hanham and Agarwal for the same reasons as disclosed above.
As per claim 22, Kim teaches a method, comprising: ([Kim, para. 0006] “a method of operating the memory system; [para. 0058; Fig. 5] “Fig. 5 is a diagram illustrating a memory system”)
transmitting, from a first interface of a first semiconductor to a second interface of a second semiconductor coupled with the first semiconductor, first signaling comprising a first command to activate a row of a memory array of the second semiconductor; ([Kim, para. 0027] “The memory controller 20 [first semiconductor including a first interface – see Fig. 5] may control the memory module ... according to a memory request ... The memory controller 20 may control a write operation or a read operation performed on the memory chips 110 to 117 and 131 by providing a command and an address to the memory module [first signaling comprising a first command to activate a row of a memory array of the second semiconductor – see Fig. 2] ... data for a write operation and data read may be transmitted/received between the memory controller 20 and the memory module ... These memory access operations are performed through a memory bus 30; [para. 0028] “The memory controller 20 and the memory module [second semiconductor] ... communicatively coupled”; [para. 0059] “The memory module implemented as a double data rate synchronous dynamic random-access memory dual in-line memory module ... DDR DIMM”; [para. 0041] “The control logic circuit 220 [second interface comprising second circuitry] ... receive a clock signal CLK and the command CMD [based on receiving access signaling] ... generate control signals for controlling [activating]... the memory cell array [row of a memory array of the second semiconductor]”)
receiving, at the first interface from the second interface based on transmitting the first signaling, second signaling indicating an error ([Kim, para. 0071] “the memory controller 20 is to transmit a particular command to the memory module 100, [based on transmitting the first signaling] and is to receive [transmit to the first interface] information in the ECC [error correction code] bits [second signaling as it indicates an error – see para. 0054: “the occurrence of an error ... perform error correction”] stored in the first ECC chip 151 during memory processing with the first memory channel 310 [from the second interface]”) associated with a first counter ([para. 0048] “the row hammer counter chip 131 [first counter] ... include ... the data chips 110 to 117”; [para. 0071] “the memory controller 20 detects an error in the [associated with] data of the data chips 110 to 117 [first counter]”) of the second semiconductor for counting activations of the row of the memory array; and ([para. 0042] “the control logic circuit 220 ... receive the number of times of access [for counting activations] of each of the memory cell rows in the memory cell array 200 of the memory device 110 from the row hammer counter chip 131 [first counter]”)
transmitting, from the first interface to the second interface based a value of the second counter or the second signaling indicating the error, third signaling comprising a second command to refresh one or more rows of the memory array different from the row. ([Kim, para. 0044] “The memory controller 20 ... issue [transmit] a normal refresh command [third signal comprising a second command to refresh] based on row-hammer-risky row information [based on a value of the second counter – see para 0022: “identify a memory cell row with more than a threshold number of times of access, among the number of times each of the memory cell rows are accessed ... as a row-hammer-risky row” and para. 0029: “row hammer counter 21 ... count a number of times each of the memory cell rows of the data chips 110 to 117 is accessed”] ... The memory controller 20 may transmit an address signal of one or more memory cell rows physically adjacent to [one or more addresses different from] a row-hammer-risky row to the memory device 110 [to the second interface] together with a refresh command .... The memory device 110 may refresh the one or more memory cell rows physically adjacent to the row-hammer-risky row”)
Kim does not clearly teach a first semiconductor die; a second semiconductor die coupled with the first semiconductor die; and activating, at the first interface, a second counter of the first semiconductor for counting activations of the row of the memory array based on receiving the second signaling indicating the error.
However, Hanham teaches a first semiconductor die; and ([Hanham, para. 0038] “SRAM ... includes a shared memory controller [first semiconductor]”; [para. 0038] “the SRAM ... an on-chip SRAM memory [a die]”)
a second semiconductor die coupled with the first semiconductor die. ([Hanham, para. 0029] “Each of the ... memory devices [second semiconductor] ... includes one or more individual ... dies”; [Fig. 1] the two dies are coupled)
It would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to have modified the elements disclosed by Kim with the teachings of Hanham to include a first semiconductor die; and a second semiconductor die coupled with the first semiconductor die. One of ordinary skill in the art would have been motivated to make this modification because such a configuration advantageously reduces the physical footprint of the memory controller and increases the speed of memory operations. (Hanham, para. 0048)
Kim in view of Hanham does not clearly teach activating, at the first interface, a second counter of the first semiconductor for counting activations of the row of the memory array based on receiving the second signaling indicating the error.
However, Agarwal teaches activating, at the first interface, a second counter of the first semiconductor for counting activations of the row of the memory array based on receiving the second signaling indicating the error. ([Agarwal, para. 0072] “the row hammer detection system 110 [first semiconductor] ... activate the sampling mode [second counter] by setting an always sampling register (ASR) to an “on” value” [based on the second signaling]; [para. 0118] “errors [the second signaling indicating the error] ... result in ... the row hammer detection system 110 ... engage the sampling mode”; [para. 0085] “counting record 602 [second counter] that the row hammer detection system 110 may maintain while engaged in the sampling mode [based on receiving the second signaling]”; [para. 0095] “the row hammer detection system 110 may continue tracking ... count values 612a-n [second counter – see Fig. 6] for corresponding memory sub-banks ... a number of activation counts”)
It would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to have modified the elements disclosed by Kim in view of Hanham with the teachings of Agarwal to include activating, at the first interface, a second counter of the first semiconductor for counting activations of the row of the memory array based on receiving the second signaling indicating the error. One of ordinary skill in the art would have been motivated to make this modification because a traditional system utilizing one counter can easily become overwhelmed, where this approach enables the systems described to meet the performance needs of a memory controller which would be difficult or impossible with conventional approaches. (Agarwal, para. 0003; para. 0020)
As per claim 23 Kim in view of Hanham and Agarwal teaches claim 22.
Kim also teaches wherein activating the second counter comprises: ([Kim, para. 0090] “the memory system 1 may perform initialization [activate] ... the memory controller 20 ... perform an initial setting operation [activate] according to a preset method ... initialization of the memory system [activation of the second counter, as the row hammer counter is within the memory system– see Fig. 1]”)
associating the second counter with the row. ([Kim, para. 0031] “the row hammer counter 21 [second counter] ... provide a per-row hammer tracking [associated with] ... the data chips 110 to 117 [the row]”)
Kim in view of Agarwal does not clearly teach wherein allocating a portion of a second memory array of the first semiconductor die for the second counter.
However, Hanham teaches wherein allocating a portion of a second memory array of the first semiconductor die for the second counter. ([Hanham, para. 0055] “the overflow counter ... associated respectively with a corresponding one of the buffer memory blocks [a portion of a second memory array of the first semiconductor die - see para. 0041 and Fig. 3]”; [para. 0078] “At 752, the example system allocates an overflow counter [a portion of a second memory array of the first semiconductor die] corresponding to a reference counter [for the second counter]”)
It would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Kim, Hanham and Agarwal for the same reasons as disclosed above.
As per claim 24, Kim in view of Hanham and Agarwal teaches claim 22.
Kim also teaches transmitting, from the first interface to the second interface, a command to activate the row; ([Kim, para. 0027] “The memory controller 20 [from the first interface] ... control a write operation or a read operation ... by providing a command and an address [transmit a command to activate the row] to the memory module [to the second interface]”)
transmitting the third signaling from the first interface to the second interface based on the value of the second counter satisfying one or more thresholds; and ([Kim, para. 0093] “the memory controller 20 [from the first interface] may count a number of times ... the data chips 110 to 117 are accessed ... by using the row hammer counter 21 [based on the value of the second counter]”; [para. 0095] “when the number of times of access ... is equal to or greater than the threshold, a memory cell row [to the second interface] ... may be target-refreshed”)
resetting, at the first interface, one or more portions of the second counter ([Kim, para. 0068] “The row hammer counter 21 [second counter] may store the number of times of access of the word lines of each of the data chips 110 to 117”; [para. 0096] “in operation S1060 ... the memory controller 20 may reset the number of accesses to each word line ... the data chips 110 to 117 to ... 0”) based on transmitting the third signaling. ([Para. 0095] “In operation S1050 ... a memory cell row ... may be target-refreshed”; [Fig. 10] As the counter resets based on step 1050, the reset is “based on” transmitting the refresh signaling)
Kim in view of Hanham does not clearly teach transmitting, after activating the second counter, fourth signaling comprising a third command to activate the row; and incrementing, at the first interface, the value of the second counter based on transmitting the fourth signaling.
However, Agarwal teaches transmitting, after activating the second counter, fourth signaling comprising a third command to activate the row; and ([Agarwal, para. 0072] “the row hammer detection system 110 ... activate the sampling mode [after activating the second counter] by setting an always sampling register (ASR) to an “on” value””; [para. 0075] “Upon activating the sampling mode ... row hammer detection system 110 may perform an act 520 of detecting an activation of a next address [fourth signaling comprising a third command to activate the row as the address is associated with a row hammer attack]”)
incrementing, at the first interface, the value of the second counter based on transmitting the fourth signaling. ([Agarwal, para. 0095] “the row hammer detection system 110 [first interface] may continue tracking address and count values 612a-n [the second counter] for corresponding memory sub-banks ... a number of activation counts similar to the examples described above in connection with FIGS. 2-4”; [para. 0061] “Upon detecting activation of a next address, [based on transmitting the fourth signaling in view of Kim as per above] the row hammer detection system 110 may ... perform an act 410 of incrementing or otherwise iterating a count for the row entry [increment a value of the first counter]”)
It would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Kim, Hanham and Agarwal for the same reasons as disclosed above.
As per claim 25, Kim in view of Hanham and Agarwal teaches claim 22.
Kim also teaches receiving, at the first interface from the second interface after receiving the second signaling, fourth signaling indicating that a value of the first counter satisfies a threshold. ([Kim, para. 0042] “the number of times of access of each of the memory cell rows in the memory cell array 200 of the memory device 110 from the row hammer counter chip 131 [value of the first counter] ... The control logic circuit 220 may include a row hammer control circuit 210 that determines whether the number of times of access of any of the memory cell rows is greater than or equal to a threshold [satisfies a threshold], and identifies ... as a row-hammer-risky row [fourth signaling]”; [para 0044] “the row hammer control circuit 210 [from second interface] may transmit information on the detected row-hammer-risky row [fourth signaling] to the memory controller 20 [receive at the first interface]”)
Kim in view of Hanham does not clearly teach Kim also teaches receiving, after receiving the second signaling, fourth signaling indicating that a value of the first counter satisfies a threshold; and deactivating, at the first interface, the second counter based on receiving the fourth signaling.
However, Agarwal teaches receiving, after receiving the second signaling, fourth signaling ([Agarwal, para. 0070] “the row hammer detection system ... perform an act 510 of activating ... a sampling mode [receiving the second signaling - see para. 0072: “the ASR bit may act as a signal ... to implement ... sampling mode]”; [para. 0084] “re-engage the counting mode [receiving fourth signaling – see para. 0072: “the ASR bit may act as a signal ... to implement ... counting mode”] after engaging the sampling mode [after receiving the second signaling]”) indicating that a value of the first counter satisfies a threshold; and ([para. 0033] “the activation count table [first counter] ... additionally include a spillover count [a value of the first counter – see Fig. 3]”; [para. 0121-122] “engaging a counting mode [fourth signaling] ... by maintaining ... a spillover count determining exceeds a threshold count associated with a likelihood of an aggressor row [a threshold]”)
deactivating, at the first interface, the second counter based on receiving the fourth signaling. ([Agarwal, para. 0112] “the row hammer detection system 110 [at the first interface] may perform an act ... of re-engaging ... the counting mode [based on receiving the fourth signaling] ... transition from the sampling mode [deactivate the second counter]”; [para. 0125] “Engaging the sampling mode ... including maintaining a spill overflow count ... while the sampling mode is engaged”; as the spill overflow count/second counter [see Fig. 6] is maintained only while the sampling mode is engaged, it is necessarily deactivated once the sampling mode is transitioned to the counting mode)
It would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Kim, Hanham and Agarwal for the same reasons as disclosed above.
As per claim 26, Kim in view of Hanham and Agarwal teaches claim 22.
Kim in view of Hanham does not clearly teach deactivating, at the first interface, the second counter based on the value of the second counter failing to satisfy a threshold within a duration.
However, Agarwal teaches deactivating, at the first interface, the second counter based on the value of the second counter failing to satisfy a threshold within a duration. [Agarwal, para. 0105] “where the sampling mode countdown hits zero [within a duration] and where the spill overflow count is greater than zero [failing to satisfy a threshold within a duration] ... the row hammer detection system 110 [at the first interface] may re-engage the counting mode [deactivate the first counter]”; [para. 0125] “Engaging the sampling mode ... including maintaining a spill overflow count ... while the sampling mode is engaged”; as the spill overflow count/second counter is maintained only while the sampling mode is engaged, it is necessarily deactivated once the sampling mode is transitioned to the counting mode)
It would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Kim, Hanham and Agarwal for the same reasons as disclosed above.
As per claim 27, Kim teaches an apparatus ([Kim, para. 0025] “the host may be ... a computer [apparatus]”) comprising a second semiconductor ([para. 0026] “the memory controller 20 [first semiconductor] corresponds to a component provided in the processing unit of the host, and the processing unit controls the memory module 10 [second semiconductor]”) comprising a second interface, the second interface comprising circuitry operable to: ([para. 0074] “the memory module ... include ... RCD chip”; [para. 0077] “the RCD chip [second interface] ... receive a command, an address, a clock signal and a control signal from the memory controller 20”; [para. 0041] “The control logic circuit 220 [second interface comprising second circuitry] ... receive a clock signal CLK and the command CMD... generate control signals for controlling ... the memory cell array”)
receive, from a first interface of a first semiconductor, first signaling comprising a first command to activate a row of a memory array of the second semiconductor; ([Kim, para. 0027] “The memory controller 20 [first interface] may control the memory module ... according to a memory request ... The memory controller 20 may control a write operation or a read operation performed on the memory chips 110 to 117 [a row of a memory array of the second semiconductor – see Fig. 2 and para. 0048] ... by providing a command and an address to the memory module [receive first signaling comprising a first command] ... data for a write operation and data read [to activate] may be transmitted/received between the memory controller 20 and the memory module ... These memory access operations are performed through a memory bus 30 [first interface of a first semiconductor])
identify, based on the first signaling, an error ([Kim, para. 0071] “the memory controller 20 is to transmit a particular command to the memory module 100, [based on the first signaling] and is to receive information in the ECC [error correction code] bits [an error – see para. 0054: “the occurrence of an error ... perform error correction”] stored in the first ECC chip 151 during memory processing with the first memory channel 310”) associated with a counter of the second semiconductor ([para. 0048] “the row hammer counter chip 131 [first counter of the second semiconductor – see Fig. 5] ... include ... the data chips 110 to 117”; [para. 0071] “the memory controller 20 detects an error in the [associated with] data of the data chips 110 to 117 [first counter]”) for counting activations of the row of the memory array; and ([para. 0042] “the control logic circuit 220 ... receive the number of times of access [for counting activations] of each of the memory cell rows in the memory cell array 200 of the memory device 110 from the row hammer counter chip 131 [first counter]”)
transmit, to the first interface based on identifying the error, second signaling comprising an indication of the error. ([Kim, para. 0071] “the memory controller 20 ... is to receive [transmit to the first interface] information in the ECC [based on identifying the error] bits [second signaling as it indicates an error – see para. 0054: the occurrence of an error ... perform error correction”]”)
Kim does not clearly teach a first semiconductor die; a second semiconductor die coupled with the first semiconductor die; and receive, from the first interface based on transmitting the second signaling, third signaling comprising a second command to refresh one or more second rows of the memory array different from the row.
However, Hanham teaches a first semiconductor die; and ([Hanham, para. 0038] “SRAM ... includes a shared memory controller [first semiconductor]”; [para. 0038] “the SRAM ... an on-chip SRAM memory [a die]”)
a second semiconductor die coupled with the first semiconductor die. ([Hanham, para. 0029] “Each of the ... memory devices [second semiconductor] ... includes one or more individual ... dies”; [Fig. 1] the two dies are coupled)
It would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to have modified the elements disclosed by Kim with the teachings of Hanham to include a first semiconductor die; and a second semiconductor die coupled with the first semiconductor die. One of ordinary skill in the art would have been motivated to make this modification because such a configuration advantageously reduces the physical footprint of the memory controller and increases the speed of memory operations. (Hanham, para. 0048)
Kim in view of Hanham does not clearly teach receive, from the first interface based on transmitting the second signaling, third signaling comprising a second command to refresh one or more second rows of the memory array different from the row.
However, Agarwal teaches receive, from the first interface ([Agarwal, para. 0035] “the memory controller ... issuing a refresh command indicating the memory address as a predicted aggressor row of a row hammer attack”) based on transmitting the second signaling, ([para. 0072] “the row hammer detection system 110 ... activate the sampling mode by setting an always sampling register (ASR) to an “on” value” [in response to the second signaling as this indicates an error]; [para. 0118] “errors ... result in [indicate] ... the row hammer detection system 110 ... engage the sampling mode [indicating the error]”) third signaling comprising a second command to refresh ([para. 0079] “perform an act 550 of generating a refresh command [third signaling as this occurs after transitioning to sampling mode – see Fig. 5]”) one or more second rows of the memory array different from the row. ([Para. 0081] “the refresh command includes an indication of a blast radius ... For example, the row hammer detection system 110 may generate and issue a refresh command indicating a row that is suspected as an aggressor row in combination with a blast radius of a predetermined number of rows ... two rows ... indicate both the aggressor row and row(s) on either side of the aggressor row [second rows different from the row]... should be refreshed in response to the refresh command”)
It would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to have modified the elements disclosed by Kim in view of Hanham with the teachings of Agarwal to include receive, from the first interface based on transmitting the second signaling, third signaling comprising a second command to refresh one or more second rows of the memory array different from the row. One of ordinary skill in the art would have been motivated to make this modification because such a technique allows minimization of a total number of vulnerable refresh windows, decreasing transitions which reduces the probability that a row hammer attack will successfully corrupt data on the memory hardware. (Agarwal, para. 0025; and para. 0090)
As per claim 28, Kim in view of Hanham and Agarwal teaches claim 27.
Kim in view of Hanham does not clearly teach wherein the circuitry is further operable to: reset a value of the counter based on transmitting the second signaling to the first interface.
However, Agarwal teaches wherein the circuitry is further operable to: reset a value of the counter based on transmitting the second signaling to the first interface. ([Agarwal, para. 0067] “after 32 milliseconds have passed without the spillover count [based on the error associated with the second counter] hitting or exceeding the threshold ... row hammer detection system 110 [the circuitry] ... reset the counts [the counter – see para. 0059 that describes the count is of a corresponding activation count table]”; [para. 0065] “the spillover count ... a metric for determining the counting method is becoming overwhelmed [error/second signaling to the first interface]”)
It would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Kim, Hanham and Agarwal for the same reasons as disclosed above.
As per claim 29, Kim in view of Hanham and Agarwal teaches claim 27.
Kim also teaches a command to refresh the one or more second rows while a value of the counter fails to satisfy a threshold. ([Kim, para. 0044] “The memory controller 20 ... issue a normal refresh command based on row-hammer-risky row information ... The memory device 110 may refresh the one or more memory cell rows physically adjacent to the row-hammer-risky row [the one or more second rows]”; [para. 0042] “the number of times of access of each of the memory cell rows in the memory cell array 200 of the memory device 110 from the row hammer counter chip 131 [a value of the counter] ... identifies a memory cell row for which the number of times of access is equal to or greater than the threshold [fails to satisfy a threshold] as a row-hammer-risky row”)
Kim in view of Hanham does not clearly teach wherein the circuitry is further operable to: receive, based on transmitting the second signaling based on transmitting the second signaling, third signaling comprising a second command to refresh and after receiving the third signaling, fourth signaling comprising a third command to refresh the one or more second rows.
However, Agarwal teaches wherein the circuitry is further operable to: receive, based on transmitting the second signaling based on transmitting the second signaling, ([Agarwal, para. 0072] “the row hammer detection system 110 [circuitry] ... activate [transmit] the sampling mode by setting an always sampling register (ASR) to an “on” value” [based on transmitting the second signaling as this indicates an error]; [para. 0118] “errors ... result in [indicate] ... the row hammer detection system 110 ... engage the sampling mode [indicating the error]”) third signaling comprising a second command to refresh ([para. 0079] “perform an act 550 of generating a refresh command [third signaling as this occurs after/based on transitioning to sampling mode – see Fig. 5]”; [para. 0080] “The refresh command may include any command sent from the memory controller 108 to the memory hardware 122 [circuitry to receive] facilitate refreshing one or more rows of memory corresponding to the suspected row hammer attack”) and after receiving the third signaling, fourth signaling comprising a third command to refresh ([para. 0082] “refresh commands issued ... every 7.8 microseconds [another refresh command after the first, and thus, fourth signaling]”) the one or more second rows ([para. 0081] “the refresh command includes an indication of a blast radius ... For example, the row hammer detection system 110 may generate and issue a refresh command indicating a row that is suspected as an aggressor row in combination with a blast radius of a predetermined number of rows ... two rows ... indicate both the aggressor row and row(s) on either side of the aggressor row [second rows different from the row] ... should be refreshed in response to the refresh command”).
It would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Kim, Hanham and Agarwal for the same reasons as disclosed above.
As per claim 30, Kim in view of Hanham and Agarwal teaches claim 27.
Kim also teaches wherein the circuitry is operable to identify the error ([Kim, para. 0054] “the memory controller 20 recognizes the occurrence of an error in the memory module”) based on one or more parity bits of the counter, one or more error detection bits of the counter, a cyclic redundancy check operation based on an indication of the counter, or any combination thereof. ([Para. 0061] “The error detection ... include a cyclic redundancy check”; [para. 0071] “memory controller 20 detects an error in the data of the data chips 110 to 117 [an indication of the second counter]”; [para. 0091] “The memory controller 20 may store the number of times of access of each word line WL1 to WLm of the data chips 110 to 117 [an indication] ... the counter memory cells C110 to C117 of the row hammer counter chip 131 [of the second counter]”)
As per claim 31, Kim teaches a method comprising:
receiving, from a first interface of a first semiconductor at a second interface of a second semiconductor, first signaling comprising a first command to activate a row of a memory array of the second semiconductor; ([Kim, para. 0027] “The memory controller 20 [first interface] may control the memory module ... according to a memory request ... The memory controller 20 may control a write operation or a read operation performed on the memory chips 110 to 117 [a row of a memory array of the second semiconductor – see Fig. 2 and para. 0048] ... by providing a command and an address to the memory module [receive first signaling comprising a first command] ... data for a write operation and data read [to activate] may be transmitted/received between the memory controller 20 and the memory module ... These memory access operations are performed through a memory bus 30 [first interface of a first semiconductor])
identifying, at the second interface based on the first signaling, an error ([Kim, para. 0071] “the memory controller 20 is to transmit a particular command to the memory module 100, [based on the first signaling] and is to receive information in the ECC [error correction code] bits [an error – see para. 0054: “the occurrence of an error ... perform error correction”] stored in the first ECC chip 151 during memory processing with the first memory channel 310”) associated with a counter of the second semiconductor ([para. 0048] “the row hammer counter chip 131 [first counter of the second semiconductor – see Fig. 5] ... include ... the data chips 110 to 117”; [para. 0071] “the memory controller 20 detects an error in the [associated with] data of the data chips 110 to 117 [first counter]”) for counting activations of the row of the memory array; and ([para. 0042] “the control logic circuit 220 ... receive the number of times of access [for counting activations] of each of the memory cell rows in the memory cell array 200 of the memory device 110 from the row hammer counter chip 131 [first counter]”)
transmitting, from the second interface to the first interface based on identifying the error, second signaling comprising an indication of the error. ([Kim, para. 0071] “the memory controller 20 ... is to receive [transmit to the first interface] information in the ECC [based on identifying the error] bits [second signaling as it indicates an error – see para. 0054: the occurrence of an error ... perform error correction”]”)
Kim does not clearly teach a first semiconductor die; a second semiconductor die coupled with the first semiconductor die; and receiving, from the first interface based on transmitting the second signaling, third signaling comprising a second command to refresh one or more second rows of the memory array different from the row.
However, Hanham teaches a first semiconductor die; and ([Hanham, para. 0038] “SRAM ... includes a shared memory controller [first semiconductor]”; [para. 0038] “the SRAM ... an on-chip SRAM memory [a die]”)
a second semiconductor die coupled with the first semiconductor die. ([Hanham, para. 0029] “Each of the ... memory devices [second semiconductor] ... includes one or more individual ... dies”; [Fig. 1] the two dies are coupled)
It would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to have modified the elements disclosed by Kim with the teachings of Hanham to include a first semiconductor die; and a second semiconductor die coupled with the first semiconductor die. One of ordinary skill in the art would have been motivated to make this modification because such a configuration advantageously reduces the physical footprint of the memory controller and increases the speed of memory operations. (Hanham, para. 0048)
Kim in view of Hanham does not clearly teach receiving, from the first interface based on transmitting the second signaling, third signaling comprising a second command to refresh one or more second rows of the memory array different from the row.
However, Agarwal teaches receiving, from the first interface ([Agarwal, para. 0035] “the memory controller ... issuing a refresh command indicating the memory address as a predicted aggressor row of a row hammer attack”) based on transmitting the second signaling, ([para. 0072] “the row hammer detection system 110 ... activate the sampling mode by setting an always sampling register (ASR) to an “on” value” [in response to the second signaling as this indicates an error]; [para. 0118] “errors ... result in [indicate] ... the row hammer detection system 110 ... engage the sampling mode [indicating the error]”) third signaling comprising a second command to refresh ([para. 0079] “perform an act 550 of generating a refresh command [third signaling as this occurs after transitioning to sampling mode – see Fig. 5]”) one or more second rows of the memory array different from the row. ([Para. 0081] “the refresh command includes an indication of a blast radius ... For example, the row hammer detection system 110 may generate and issue a refresh command indicating a row that is suspected as an aggressor row in combination with a blast radius of a predetermined number of rows ... two rows ... indicate both the aggressor row and row(s) on either side of the aggressor row [second rows different from the row]... should be refreshed in response to the refresh command”)
It would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to have modified the elements disclosed by Kim in view of Hanham with the teachings of Agarwal to include receiving, from the first interface based on transmitting the second signaling, third signaling comprising a second command to refresh one or more second rows of the memory array different from the row. One of ordinary skill in the art would have been motivated to make this modification because such a technique allows minimization of a total number of vulnerable refresh windows, decreasing transitions which reduces the probability that a row hammer attack will successfully corrupt data on the memory hardware. (Agarwal, para. 0025; and para. 0090)
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Hanham as applied to claim 1 above and further in view of Zhang et al. (US Pub. 2020/0090750) (hereinafter “Zhang”)
As per claim 4, Kim in view of Hanham teaches claim 1.
Kim in view of Hanham does not clearly teach wherein the portion of the memory array is operable as a content-addressable memory.
However, Zhang teaches wherein the portion of the memory array is operable as a content-addressable memory. ([Zhang, para. 0094] “the memory device may include one or more memory arrays, [the portion of the memory array] such as one or more content-addressable memory (CAM) arrays ... The one or more memory arrays may include a plurality of CAM cells”)
It would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to have modified the elements disclosed by Kim in view of Hanham with the teachings of Zhang to include wherein the portion of the memory array is operable as a content-addressable memory. One of ordinary skill in the art would have been motivated to make this modification because CAMs are designed to quickly search its memory array in a single operation, and thus CAMS are much faster than equivalent memory based data searches. (Zhang, para. 0026)
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Bernstein et al. (US Pub. 2009/0224388) discloses a semiconductor chip that comprises multiple unit chips providing redundancy in function and improvement in yield and methods of manufacturing.
He et al. (US Pub. 2024/0094921) discloses a testing operation to validate counters of a memory system where the counters are used in a row hammer mitigation scheme.
Sahoo (US Patent No. 6,975,696) discloses testing for a counter system where the testing allows a determination whether the counter matches expected count results.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
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/ZHE LIU/Examiner, Art Unit 2493
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