DETAILED ACTION
1. This office action is in response to communication filed on 04/22/2026. Claims 1 and 11 have been amended. Claims 1-20 are pending on this application.
Response to Arguments
2. Applicant’s arguments with respect to amended claim(s) 1 and 11 “an amplifier configured to multiply the filtered error signal by a gain factor” have been considered but are moot because the new ground of rejection in view of new reference (Ashburn Jr. et al. Pub. No. 2013/0021184) does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
3. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claims 1-3, 6, 7, 9, 11, 12, 13, 16, 17 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. Pub. No. 2007/0018865 in view of Ashburn Jr. et al. Pub. No. 2013/0021184.
Regarding claim 1. Fig. 4 of Chang et al. discloses an apparatus (40), comprising: a comparator (21) configured to receive an input signal (X(z)) and a feedback signal (47) , and to output an error signal (output error of 21) that is a difference (21) between the input signal (X(z)) and the feedback signal (47); a first filter (11 and 22) configured to receive as an input the error signal (output of 21) and output a filtered error signal (output of 22); an amplifier (filter 12; filter 12 having a Gain of A2; Gain is fundamental to an amplifier's function, representing its inherent ability to increase a signal's strength) configured to receive the first filtered error signal (output of 22) and output an amplified filtered error signal (output of 12) ; an adder (23) configured to receive the error signal (46) and the amplified filtered error signal (output of 12) and output a total error signal (output of 23) that is a sum (23) of the error signal (46) and the amplified filtered error signal (output of 12) ; a second filter (13) configured to receive the total error signal (output of 23) and output a filtered total error signal (output of 13) ; and a quantizer (14) configured to receive as an input the filtered total error signal (output of 13) and to output as the feedback signal (47) a quantized value (Y(z)) that is based upon a value of the filtered total error signal (value output signal of 13) .
However, Chang et al. do not disclose the gain circuit (12) includes an amplifier configured to multiply the filtered error signal by a gain factor and the quantizer (14) output quantized value upon receipt of a clock signal.
Fig. 7 of Ashburn Jr. et al. discloses a delta-sigma ADC; comprising: a gain circuit (a13) includes an amplifier (a13) configured to multiply a filtered error signal (X1) by a gain factor (gain factor of a13) and a quantizer (quantization E(n)) output quantized value (Digital output) upon receipt of a clock signal (FCLK).
Chang et al. and Ashburn Jr. et al. are common subject matter of feedforward delta-sigma modulator ADC; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate gain amplifier of Ashburn Jr. et al. into gain circuit of Chang et al. to achieve a specific NTF to obtain optimal noise shaping over frequency, the dynamics of the loop filter composed of the integrators, DAC, feed-forward and feedback paths of the converter are designed to produce the desired response at specific points of time (paragraph 0052 of Ashburn Jr. et al.).
Regarding claim 2. Chang et al. and Ashburn Jr. et al. applied to claim 1 above, Fig. 4 of Chang et al. further discloses: wherein the first filter (11, 22) and the second filter (13) are configured to suppress (suppression by filtering of 11, 12, 13) the error signal (output of 21) in a selected signal band of interest (paragraph 0006 discloses signal to noise plus distortion ratio SNDR for application bandwidth).
Regarding claim 3. Chang et al. and Ashburn Jr. et al. applied to claim 2 above, Fig. 4 of Chang et al. further discloses wherein the first filter (11, 22) and the second filter (13) are band-pass filters (paragraph 0006 discloses signal to noise plus distortion ratio SNDR for application bandwidth; "bandwidth " is essentially a bandpass, as its primary function is to allow a specific range ‘bandwidth’ of frequencies to pass through while blocking others configured to pass frequencies) in the selected signal band of interest (paragraph 0006 discloses application bandwidth).
Regarding claim 6. Chang et al. and Ashburn Jr. et al. applied to claim 2 above, Fig. 4 of Chang et al. further discloses a delta-sigma modulator (406) comprising: the first filter (11, 12, 13) is of an order higher than a first order filter (paragraph 0002).
Regarding claim 7. Chang et al. and Ashburn Jr. et al. applied to claim 6 above, Fig. 7 of and Ashburn Jr. et al. further discloses wherein the first filter (first 1/s) is a fourth order filter (paragraph 0010).
Regarding claim 9. Chang et al. and Ashburn Jr. et al. applied to claim 1 above, Fig. 7 of Ashburn Jr. et al. further disclose wherein the quantizer is configured such that each output (Dout) of the quantizer (Quantization E(z)) comprises a plurality of bits (paragraph 0047).
Regarding claim 11. Fig. 4 of Chang et al. discloses a method of processing an input signal (X(z)), comprising: comparing (21) the input signal (X(z)) and a feedback signal (47) to generate an error signal (error output of 21) that is a difference (21) between the input signal (X(z)) and the feedback signal (47) ; filtering (filtering by 11, 22) the error signal (output of 11) to generate a filtered error signal (output of 22) ; amplifying (Gain A2 of 12; Gain is fundamental to an amplifier's function, representing its inherent ability to increase a signal's strength) the first filtered error signal (output of 12) to generate an amplified filtered error signal (output of 12) ; adding (23) the error signal (46) and the amplified filtered error signal (output of 12) to generate a total error signal (output of 23) that is a sum (23) of the error signal (46) and the amplified filtered error signal (output of 12) ; filtering (filtering by 13) the total error signal (output of 23) to generate a filtered total error signal (output of 13); and quantizing (14) the filtered total error signal (output of 13) to generate the feedback signal (47) based upon a value of the filtered total error signal (signal output value of 13).
However, Chang et al. do not disclose the gain circuit (12) includes an amplifier configured to multiply the filtered error signal by a gain factor.
Fig. 7 of Ashburn Jr. et al. discloses a delta-sigma ADC; comprising: the gain circuit (a13) includes an amplifier (a13) configured to multiply a filtered error signal (X1) by a gain factor (gain factor of a13).
Chang et al. and Ashburn Jr. et al. are common subject matter of feedforward delta-sigma modulator ADC; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate gain amplifier of Ashburn Jr. et al. into gain circuit of Chang et al. to achieve a specific NTF to obtain optimal noise shaping over frequency, the dynamics of the loop filter composed of the integrators, DAC, feed-forward and feedback paths of the converter are designed to produce the desired response at specific points of time (paragraph 0052 of Ashburn Jr. et al.).
Regarding claim 12. Chang et al. and Ashburn Jr. et al. applied to claim 11 above, Fig. 4 of Chang et al. further discloses: wherein filtering the error signal (filtering of 11 and 12) and filtering the total error signal (output signal of 13) suppress (suppression of filtering 11, 12, 13) the error signal (output of 21) in a selected signal band of interest (paragraph 0006 discloses signal to noise plus distortion ratio SNDR for application bandwidth).
Regarding claim 13. Chang et al. and Ashburn Jr. et al. applied to claim 12 above, Fig. 4 of Chang et al. further discloses wherein filtering (filtering 11, 12) the error signal (output of 21) and filtering the total error signal (output of filter 13) comprise band-pass filtering that passes frequencies (paragraph 0006 discloses signal to noise plus distortion ratio SNDR for application bandwidth; "bandwidth " is essentially a bandpass, as its primary function is to allow a specific range ‘bandwidth’ of frequencies to pass through while blocking others configured to pass frequencies) in the selected signal band of interest (paragraph 0006 discloses application bandwidth).
Regarding claim 16. Chang et al. and Ashburn Jr. et al. applied to claim 12 above, Fig. 4 of Chang et al. further discloses wherein filtering the error signal (output of 22) comprises applying a filter (11, 12, 13) having an order higher than a first order filter (paragraph 0002).
Regarding claim 17. Chang et al. and Ashburn Jr. et al. applied to claim1 6 above, Fig. 7 of and Ashburn Jr. et al. further discloses wherein the first filter (first 1/s) is a fourth order filter (paragraph 0010).
Regarding claim 19. Chang et al.and Ashburn Jr. et al. applied to claim 11 above, Fig. 7 of Ashburn Jr. et al. further discloses wherein the quantizer (Quantization E(z)) is quantizing to a value (Dout) comprising a plurality of bits (paragraph 0047).
5. Claims 4 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. and Ashburn Jr. et al. applied to claims 3 and 13 above, respectively, in further view of Bach et al. Pub. No. 2018/0063644.
Chang et al. and Ashburn Jr. et al. applied to claims 3 and 13 above, respectively, do not disclose wherein the first filter (11, 22) and the second filter (13) are low-pass filters configured to pass frequencies from approximately 20 hertz (Hz) to 20 kilohertz (kHz).
Fig. 2 of Bach et al. discloses a delta-sigma modulator (paragraph 0008) comprising a low pass filter (151) configured to pass frequencies from approximately 20 Hz to 20 kHz (paragraph 0038).
Chang et al., Ashburn Jr. et al. and Bach et al. are common subject matter of feedforward delta-sigma modulator; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate low pass filter of Bach et al. into filters of Chang et al./ Ashburn Jr. et al. for the purpose of processing frequencies of interest such as between about 20 Hz and about 20 kHz for delta-sigma modulator (paragraph 0038 of Bach et al.).
6. Claims 5 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al., Ashburn Jr. et al. and Bach et al. applied to claims 4 and 14 above, respectively, in further view of Buhmann Pub. No. 2013/0110441.
Chang et al., Ashburn Jr. et al. and Bach et al. applied to claims 4 and 14 above, respectively, do not disclose wherein the quantizer is configured to receive clock signals and generate output signal at a rate of 400 kHz.
Fig. 1 of Buhmann discloses a delta-sigma modulator (paragraph 0030) comprising: a quantizer 135 (paragraph 0026) is configured to receive clock signal and generate output signals at a rate of 400 kHz (paragraph 0003 discloses “quantized with 10 bit, the sub-clock would need to be approximately 400 MHz given a sampling rate of 400 kHz”).
Chang et al., Ashburn Jr. et al. Bach et al. and Buhmann are common subject matter of quantizer for delta-sigma modulator; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate Buhmann into Chang et al./ Ashburn Jr. et al. Bach et al. for the purpose of processing sampling rate of interest to reduce noise performances (paragraph 0003 of Bhumann).
7. Claims 8 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. and Ashburn Jr. et al. applied to claims 1 and 11 above, respectively, in further view of Paton Alvarez et al. U.S. patent 9,577,663.
Chang et al. and Ashburn Jr. et al. applied to claims 1 and 11, respectively, above do not disclose wherein the amplifier (A2) is configured to amplify the filtered error signal (output of 22) by approximately 20 times.
Fig. 3 of Paton Alvarez et al. discloses the amplifier (c1, c2, c3, b2) is configured to amplify a filter error output of 318) by approximately 20 times (Col. 12 lines 29-30).
Chang et al., Ashburn Jr. et al. and Alvarez et al. are common subject matter of filter for delta-sigma modulator; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate Paton Alvarez et al. into Chang et al./ Ashburn Jr. et al. for the purpose of extending the bandwidth of analog-to-digital converters by means of gain boosting (Col. 1 lines 8-10 of Alvarez et al.).
8. Claims 10 and 20 is rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. and Ashburn Jr. et al. applied to claims 9 and 19 above, respectively, in further view Linder et al. U.S. patent No. 5,990,815.
Chang et al. and Ashburn Jr. et al. applied to claims 9 and 19 above, respectively, do not disclose quantizing the filtered total error signal to a value comprising 7 bits representing values from -63 to 63, inclusive.
Fig. 1 of Linder et al. discloses an analog to digital converter comprising a quantizer (26) is configured such that each output of the quantizer (26) is quantizing to a value comprising 7 bits (Col. 5 lines 11-12 of Linder et al. discloses “7- bit quantizer 26”) representing values from -63 to 63, inclusive (Col. 5 lines 11-12 of Linder et al. discloses “sign magnitude of 7-bit”. Thus, in A 7-bit system with a range that hits 63 usually refers to signed numbers in Sign-Magnitude, giving -63 represented 7 bits formation [1111111] where the left most bit is 1 represented negative and the last 6 bits 111111 equals 63; giving 63 represented 7 bits formation [0111111] where the most left bit is 0 represented positive and the last 6 bits 111111 equal 63).
Chang et al., Ashburn Jr. et al. and Linder et al. are common subject matter of quantizer for analog to digital converter; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate Linder et al. into Chang et al. for the purpose of obtain 7 bits resolution of interest from quantizer represent -63 to 63 values (Col. 5 lines 11-12 of Linder et al. discloses “7- bit quantizer 26” of Linder et al.).
Conclusion
9. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Contact Information
10. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Linh Van Nguyen whose telephone number is (571) 272-1810. The examiner can normally be reached from 8:30 – 5:00 Monday-Friday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mr. Dameon E. Levi can be reached at (571) 272-2105. The fax phone numbers for the organization where this application or proceeding is assigned are (571-273-8300) for regular communications and (571-273-8300) for After Final communications.
05/13/2026
/LINH V NGUYEN/Primary Examiner, Art Unit 2845
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