DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 4-5, 7, 10-11, 15-16, and 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over US Patent Application Publication Number 2020/0150733 to Gutierrez et al. (”Gutierrez”), US Patent Application Publication Number 2009/0306914 to Cohen (“Cohen”), and US Patent Application Publication Number 2025/0334906 to Miyamoto et al. (“Miyamoto”).
In reference to Claim 1 Gutierrez discloses an electronic device (See Figures 1 and 3 Number 114) for communicating with a host (See Figure 1 Number 150, Figure 3 Number 330 and Paragraphs 25 and 58 [Numbers 150 and 330 can be a computer system, which itself can be a server, and thus is a host in accordance with the broadest reasonable interpretation of the term as set forth in Paragraph 21 of Applicant’s disclosure]), comprising: a plurality of functional circuits (See Figure 3 Numbers 314 and Paragraph 74); a plurality of power sensors, wherein each of the power sensors is configured to sense power of one of the functional circuits to provide a power sensing signal (See Figure 3 Numbers 315 and Paragraphs 76-77); a processor, coupled to the power sensors, and configured to collect a plurality of power sensing signals from the power sensors and generate a plurality of power values corresponding to the functional circuits based on the power sensing signals (See Figure 3 Number 318 and Paragraphs 25, 71, and 77); a first communication port (See Figure 1 Numbers 151 and 152, Figure 3 Number 332, Figure 5 Number 542, Figure 12 Number 1270, and Paragraphs 57, 74, 93, and 180 [Ethernet networks require a physical communication port]); and a network communication interface, coupled to the processor and the first communication port (See Figure 5 Number 542, Figure 12 Number 1240, and Paragraphs 57, 74, 93-94, and Paragraphs 179-180 [Ethernet networks require a network communication interface to communicate with the network via the physical port]), and configured to provide the power values (See Paragraph 58) and a total input power (See Paragraphs 31-32 and 64 [power data indicating the total power input to a set of multiple functional circuits]) to the host through the first communication port (See Paragraphs 58, 77, and 93). However, Gutierrez does not explicitly disclose that the processor obtains a current load value of the electronic device based on a total output power of the electronic device, obtains a current efficiency value of the electronic device based on the current load value and an efficiency lookup table, and calculates a total input power of the electronic device based on the current efficiency value and the total output power, wherein the total output power of the electronic device is calculated based on a sum of the power values corresponding to the functional circuits. Cohen discloses a processor that obtains a current load value of an electronic device based on a total output power of the electronic device (See Figure 2 Numbers 218 and 222 and Paragraphs 22-23), obtains a current efficiency value of the electronic device based on the current load value and an efficiency lookup table (See Figure 2 Number 222 and Paragraphs 23-24), and calculates a total input power of the electronic device based on the current efficiency value and the total output power (See Figure 4 Number 418 and Paragraphs 24 and 31). Miyamoto discloses calculating the total output power of an electronic based on a sum of the power values corresponding to the functional circuits (See Paragraph 125)
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to construct the device of Gutierrez using the efficiency lookup table for determining total input power of Cohen, and using the summing of individual functional circuit power values to determine the total output power of Miyamoto, resulting in the invention of Claim 1, in order to yield the predictable result of determining the total input power to the electronic device without needing to directly measure it (See Paragraph 24 of Cohen); and because the simple substitution of the summing of individual functional circuit power values to determine the total output power of Miyamoto in place of the direct measurement of the total output power of Cohan would have yielded the predictable result of obtaining the total output power more accurately (See Paragraph 125 of Miyamoto).
In reference to Claim 2, Gutierrez, Cohen, and Miyamoto disclose the limitations as applied to Claim 1 above. Gutierrez further discloses that the processor accumulates a first power sensing signal among the power sensing signals over time to generate a first power value among the power values (See Paragraphs 34, 77, 97, 115, and 166-167).
In reference to Claim 4, Gutierrez, Cohen, and Miyamoto disclose the limitations as applied to Claim 1 above. Cohen further discloses that the efficiency lookup table records a plurality of efficiency values corresponding to a plurality of load values (See Paragraph 23), and the processor establishes an efficiency value fitting function corresponding to the load values based on the efficiency lookup table (See Figure 4 Number 418 and Paragraphs 23-24 and 31), and calculates the total input power of the electronic device based on the efficiency value fitting function, the current load value, and the total output power (See Figure 4 Number 418 and Paragraphs 23-24, 27, and 31).
In reference to Claim 5, Gutierrez, Cohen, and Miyamoto disclose the limitations as applied to Claim 1 above. Gutierrez further discloses a routing circuit, coupled to the first communication port and the network communication interface, wherein the routing circuit comprises: an expansion interface, coupled to the network communication interface, and configured to receive a media access control address of the network communication interface; and a port physical layer circuit, coupled to the first communication port (See Paragraph 180 [Ethernet networks require an interface, coupled to a network communication interface, and configured to receive a media access control address of the network communication interface, and a port physical layer circuit, coupled to a communication port]).
In reference to Claim 7, Gutierrez, Cohen, and Miyamoto disclose the limitations as applied to Claim 1 above. Gutierrez further discloses that each of the functional circuits is one of a display panel (See Paragraph 25), a panel control circuit (See Paragraph 25), a connector (See Paragraph 74 [functional circuit is coupled to the backplane, and thus must comprise at least a connector]), and a speaker.
In reference to Claim 10, Gutierrez, Cohen, and Miyamoto disclose the limitations as applied to Claim 1 above. Gutierrez further discloses that the electronic device provides an operating interface (See Paragraph 25 [mouse, keyboard, and monitor]), and the electronic device enters one of a first mode and a second mode based on an operating result of the operating interface (See Paragraph 25 [when receiving signals from a mouse, the electronic device is in a mouse input mode, and when receiving signals from a keyboard, the electronic device is in a keyboard input mode]).
In reference to Claim 11, Gutierrez, Cohen, and Miyamoto disclose the limitations as applied to Claim 10 above. Gutierrez further discloses that in the first mode, the processor controls the electronic device to receive an address of the host (See Paragraph 180 [Ethernet network communications require an address of a destination to be included with every Ethernet frame]).
Claim 15 recites limitations which are substantially equivalent to those of Claim 1 and is rejected under similar reasoning.
Claim 16 recites limitations which are substantially equivalent to those of Claim 2 and is rejected under similar reasoning.
Claim 18 recites limitations which are substantially equivalent to those of Claim 4 and is rejected under similar reasoning.
In reference to Claim 19, Gutierrez, Cohen, and Miyamoto disclose the limitations as applied to Claim 15 above. Gutierrez further discloses receiving a media access control address of a network communication interface (See Paragraph 180 [Ethernet network communications require a MAC address of a source and destination to be included with every Ethernet frame]), and entering one of a first mode and a second mode based on an operating result of an operating interface (See Paragraph 25 [when receiving signals from a mouse of an operating interface, the electronic device is in a mouse input mode, and when receiving signals from a keyboard of an operating interface, the electronic device is in a keyboard input mode]).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gutierrez, Cohen, and Miyamoto as applied to Claim 5 above, and further in view of knowledge commonly known in the art, as evidenced by US Patent Application Publication Number 2022/0417054 to Yamada et al. (“Yamada”) and admitted by Applicant to be prior art.
In reference to Claim 6, Gutierrez, Cohen, and Miyamoto disclose the limitations as applied to Claim 5 above. Gutierrez further discloses that connection may be made to multiple networks (See Figure 12 Number 1270), and thus must necessarily include at least one second communication port; and that the routing circuit transmits the power values to the first communication port (See Paragraphs 76-77). However, Gutierrez does not explicitly disclose and a hub circuit, coupled to the at least one second communication port and the routing circuit, wherein the routing circuit transmits one of a signal from the at least one second communication port and a signal from the first communication port to the network communication interface. Official Notice is taken that the use of network hub circuits, in which multiple communication ports can be connected to a network routing circuit, is well known in the art, as evidenced by Yamada (See Figures 1-5 and Paragraphs 1 and 7-9). This has been admitted by Applicant to be prior art.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to construct the device of Gutierrez, Cohen, and Miyamoto using a well-known network hub, resulting in the invention of Claim 6, in order to yield the predictable result of providing a simple connection between the multiple communication ports and the network router (See Paragraph 7 of Yamada).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gutierrez, Cohen, and Miyamoto as applied to Claim 1 above, and further in view of US Patent Application Publication Number 2021/0367642 to Roy et al. (“Roy”).
In reference to Claim 8, Gutierrez, Cohen, and Miyamoto disclose the limitations as applied to Claim 1 above. Gutierrez does not explicitly disclose a power supply circuit, coupled to the processor, and configured to supply power to an external device connected to the electronic device, wherein the processor obtains a power value of the power supply circuit based on a power supply requirement of the external device. Roy discloses an electronic device (See Figure 3B Number 115A) having a power supply circuit (See Figure 3B Number 132C), coupled to a processor (See Figure 3B Number 124), and configured to supply power to an external device connected to the electronic device (See Figure 3B Number 130 and Paragraphs 31-33 and 57), wherein the processor obtains a power value of the power supply circuit based on a power supply requirement of the external device (See Paragraph 59).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to construct the device of Gutierrez, Cohen, and Miyamoto using external device power controller of Roy, resulting in the invention of Claim 8, in order to yield the predictable result of allowing for the connection and powering of additional external devices outside of the electronic device without a limit on the number of devise or constraint on the interconnection topology (See Paragraphs 5, 27-28, and 31 of Roy).
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gutierrez, Cohen, and Miyamoto as applied to Claim 1 above, and further in view of US Patent Application Publication Number 2008/0094001 to Yoo et al. (“Yoo”).
In reference to Claim 9, Gutierrez, Cohen, and Miyamoto disclose the limitations as applied to Claim 1 above. Gutierrez is not limited as to the type of functional circuits that are used, and discloses that the functional circuit may be a display monitor (See Paragraphs 18, 25, and 183-184). Gutierrez further discloses that the processor obtains a power value of the functional circuit based on a driving signal used by the functional circuit (See Paragraphs 76-77). However, Gutierrez and Cohen do not explicitly disclose a backlight source, coupled to the processor, and configured to provide a display light source for a display panel of the electronic device. Yoo discloses a backlight source, coupled to a processor, and configured to provide a display light source for a display panel of an electronic device, wherein the processor obtains a power value of the functional circuit based on a driving signal used by the functional circuit (See Paragraphs 1-3, 26, and 34-35).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to construct the device of Gutierrez, Cohen, and Miyamoto using a display panel and backlight source as the functional circuit, resulting in the invention of Claim 9, because Gutierrez is not limited as to the type of functional circuits that are used, and discloses that the functional circuit may be a display monitor (See Paragraphs 18, 25, and 183-184), and the simple substitution of the display panel and backlight source of Yoo as the functional circuit of Gutierrez would have yielded the predictable result of providing a display with high luminance, high efficiency, uniform luminance, long lifetime, thin thickness, light weight, and low cost (See Paragraphs 2-3 of Yoo).
Alternatively, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to construct the device of Yoo using power monitoring and reporting of Gutierrez, Cohen, and Miyamoto, resulting in the invention of Claim 9, in order to yield the predictable result of allowing for monitoring of power consumption at a higher level of granularity that would be possible by simply measuring total power consumption (See Paragraph 33 of Gutierrez) while allowing such monitoring to occur remotely and for multiple separate systems (See Paragraphs 71 and 80 of Gutierrez).
Claim(s) 12-14 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gutierrez, Cohen, and Miyamoto as applied to Claims 10, 11, and 19 above, and further in view of US Patent Application Publication Number 2018/0351401 to Binder et al. (“Binder”).
In reference to Claim 12, Gutierrez, Cohen, and Miyamoto disclose the limitations as applied to Claim 11 above. Gutierrez further discloses the use of an Ethernet network, which necessarily requires knowing the destination address for a communication (See Paragraph 180). However, Gutierrez and Cohen do not explicitly disclose that in the first mode, the processor controls the electronic device to provide a configuration menu for inputting or selecting the address of the host based on a specific operating method. Binder discloses that in a first mode, a processor allows an electronic device to be configured; wherein in the first mode, the processor controls the electronic device to provide a configuration menu for inputting or selecting configuration information based on a specific operating method (See Paragraphs 7, 42, 56, and 59-60).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to construct the device of Gutierrez, Cohen, and Miyamoto using the user interface for configuration of Binder to configure the host address, resulting in the invention of Claim 12, because Gutierrez is silent as to how the host address is input, and the simple substitution of the user interface for configuration of Binder to input the host address would have yielded the predictable result of allowing for easy configuration of the host address by the user using a GUI (See Paragraph 7 of Binder).
In reference to Claim 13, Gutierrez, Cohen, and Miyamoto disclose the limitations as applied to Claim 10 above. Gutierrez further discloses that in the second mode, the processor controls the network communication interface to receive historical data of the power values of the electronic device (See Paragraphs 77 and 79). However, Gutierrez, Cohen, and Miyamoto do not explicitly disclose that the processor controls the electronic device to display the historical data. Binder discloses in a second mode, a processor controls the network communication interface to receive historical data of the power values of an electronic device, and controls the electronic device to display the historical data (See Paragraphs 7 and 60).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to construct the device of Gutierrez, Cohen, and Miyamoto using the user interface for displaying historical data of power values of Binder, resulting in the invention of Claim 13, in order to yield the predictable result of allowing for easy review of load demand history by the user using a GUI (See Paragraph 7 of Binder).
In reference to Claim 14, Gutierrez, Cohen, Miyamoto, and Binder disclose the limitations as applied to Claim 13 above. Binder further discloses that in the second mode, at least one of an application program of the processor and an application program of a network communication interface is updated (See Paragraphs 7 and 46).
In reference to Claim 20, Gutierrez, Cohen, and Miyamoto disclose the limitations as applied to Claim 19 above. Gutierrez further discloses the use of an Ethernet network, which necessarily requires knowing the destination address for a communication (See Paragraph 180); and that historical data of the power values is received (See Paragraphs 77 and 79). However, Gutierrez, Cohen, and Miyamoto do not explicitly disclose that in the first mode, providing a configuration menu for inputting or selecting an address of the host, wherein in the second mode, and the historical data is displayed. Binder discloses that in a first mode, providing a configuration menu for inputting or selecting configuration information (See Paragraphs 7, 42, 56, and 59-60), wherein in a second mode, historical data of power values is received and the historical data is displayed (See Paragraphs 7 and 60).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to construct the device of Gutierrez, Cohen, and Miyamoto using the user interface for configuration for displaying historical data of power values of Binder to configure the host address, and using the user interface for displaying historical data of power values of Binder, resulting in the invention of Claim 20, because Gutierrez is silent as to how the host address is input, and the simple substitution of the user interface for configuration of Binder to input the host address would have yielded the predictable result of allowing for easy configuration of the host address by the user using a GUI (See Paragraph 7 of Binder); and in order to yield the predictable result of allowing for easy review of load demand history by the user using a GUI (See Paragraph 7 of Binder).
Response to Arguments
Applicant's arguments filed 18 June 2026 have been fully considered but they are not persuasive.
Applicant has argued that Gutierrez and Cohen do not disclose that the network communication interface is configured to provide the total input power of the electronic device to the host (See Pages 9-10). In response, the Examiner notes that Gutierrez discloses that the network communication interface is configured to provide power data indicating the total power input to a set of multiple functional circuits to the host (See Paragraphs 31-32 and 64). When the set of multiple functional circuits includes all of the functional circuits of the electronic device, the total input power of the electronic device is provided to the host.
Applicant has argued that Gutierrez and Cohen do not disclose that the total output power of the electronic device is calculated based on a sum of the power values corresponding to the functional circuits (See Pages 9-10 and 11-12). In response, the Examiner notes that, as indicated in the above rejections, Miyamoto discloses such a feature.
Applicant has argued that Cohen discloses calculating the input power of the PFC converter, and not the input power of the entire electronic device (See Pages 10-11). In response, the Examiner notes that Cohen discloses that all of the power provided to the electronic device and the functional units thereof passes through the PFC converter (See Figure 2 and Paragraph 22) and that the calculated input power represents the input power to the rectifier 210 which is the input power to the power supply 200 (See Paragraph 24). Thus, the calculated total input power of the power supply and PFC is equivalent to the total input power of the entire electronic device including the functional units thereof.
Conclusion
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/THOMAS J. CLEARY/Primary Examiner, Art Unit 2175
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