CTFR 18/764,097 CTFR 86049 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Response to Arguments filed 03/16/2026 Applicant’s arguments are noted, but are directed towards limitations that are addressed by the new reference below. Claim Rejections - 35 USC § 101 07-04-01 AIA 07-04 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. Claim 20 is rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claim(s) does/do not fall within at least one of the four categories of patent eligible subject matter because they’re directed towards subject matter that isn’t patent eligible. As per the specification: See ¶23, “Accordingly, in one or more examples described herein, the functions described may be implemented in hardware, software, or any combination thereof. If implemented in software, the functions may be stored on or encoded as one or more instructions or code on a computer-readable medium. Computer-readable media includes computer storage media. Storage media may be any available media that may be accessed by a computer. By way of example, and not limitation, such computer-readable media may comprise a random access memory (RAM), a read-only memory (ROM), an electrically erasable programmable ROM (EEPROM), optical disk storage, magnetic disk storage, other magnetic storage devices, combinations of the aforementioned types of computer-readable media, or any other medium that may be used to store computer executable code in the form of instructions or data structures that may be accessed by a computer.” See ¶121, “In one or more examples, the functions described herein may be implemented in hardware, software, firmware, or any combination thereof. For example, although the term “processing unit” has been used throughout this disclosure, such processing units may be implemented in hardware, software, firmware, or any combination thereof. If any function, processing unit, technique described herein, or other module is implemented in software, the function, processing unit, technique described herein, or other module may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media may include computer data storage media or communication media including any medium that facilitates transfer of a computer program from one place to another. In this manner, computer-readable media generally may correspond to (1) tangible computer-readable storage media, which is non-transitory or (2) a communication medium such as a signal or carrier wave. Data storage media may be any available media that may be accessed by one or more computers or one or more processors to retrieve instructions, code and/or data structures for implementation of the techniques described in this disclosure. By way of example, and not limitation, such computer-readable media may comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices. Disk and disc, as used herein, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media. A computer program product may include a computer-readable medium.” The above discuss various forms of CRM. However nowhere in the specification does the specification provide a limit on a computer readable medium being a propagating signal. See MPEP 2106.03: Non-limiting examples of claims that are not directed to any of the statutory categories include: • Transitory forms of signal transmission (often referred to as “signals per se”), such as a propagating electrical or electromagnetic signal or carrier wave; and Therefore the claim is not directed towards patent eligible subject matter. Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 3 -7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 1,2, 8-18 are rejected under 35 U.S.C. 103 as being unpatentable over Heinrich et al. (US 9,595,075 B2) in view of Ma et al. , Location and 3-D Visual Awareness-Based Dynamic Texture Updating for Indoor 3-D Model in further view of Akeley (US Patent No. 5,933,155) . Regarding claim 1, Heinrich teaches an apparatus (See title, “Load/store Operations In Texture Hardware ” Hardware is considered to be a device.) for graphics processing (See title, “ Load/store Operations In Texture Hardware” The load or storing operations of texture are graphic processing), comprising: a first memory (See Fig. 1, col. 3 lines 6 – 14, “FIG. 1 is a block diagram illustrating a computer system 100 configured to implement one or more aspects of the present invention. As shown, computer system 100 includes, without limitation, a central processing unit (CPU) 102 and a system memory 104 coupled to a parallel processing subsystem 112 via a memory bridge 105 and a communication path 113. Memory bridge 105 is further coupled to an I/O (input/output) bridge 107 via a communication path 106, and I/O bridge 107 is, in tum, coupled to a switch 116.”); and a processor coupled to the first memory (See Fig. 1, col. 3 line 6 – 14, “FIG. 1 is a block diagram illustrating a computer system 100 configured to implement one or more aspects of the present invention. As shown, computer system 100 includes, without limitation, a central processing unit (CPU) 102 and a system memory 104 coupled to a parallel processing subsystem 112 via a memory bridge 105 and a communication path 113. Memory bridge 105 is further coupled to an I/O (input/output) bridge 107 via a communication path 106, and I/O bridge 107 is, in tum, coupled to a switch 116.”) and, […], the processor is configured to (See Fig. 1, col. 3 line 6 – 14,): obtain an indication of a set of graphics workloads associated with the graphics processing (See col. 9 lines 66 – col. 10 lines 25, “The TEXIN unit 402 includes a command and data conditioning unit (not shown) that reroutes global, local, or surface store data to bypass the main processing path in the texture processing pipeline 400 . The command and data conditioning unit also performs various checks to determine whether incoming the texture and non-texture load/store operations are legal. For example, certain memory access operations related to textures and surfaces could be associated with a texture header, where a texture header stores information describing characteristics of the given texture surface, including, without limitation, the type, format, dimensions, storage structure, and base address of the memory allocated to the texture or surface. If the incoming memory access operation is associated with a texture header, then the command and data conditioning unit determines whether the received memory access operation is consistent with the associated texture header, according to the type of memory access operation. If the received memory access operation is inconsistent with the texture header, then the command and data conditioning unit corrects such inconsistencies. In some embodiments, other units within the texture processing pipeline 400 may also include command and data conditioning logic.” The previous citation shows several types of indications of a graphic workload(s). See Fig. 2-4. See col. 3 lines 45- col. 6 lines 58, for general explanation of Fig. 2. See col. 6 lines 59-col 8 lines 6, for general explanation of Fig. 3. See col. 9 lines 4 – col. 19 lines 57, for general explanation of Fig. 4. The examiner notes each pipeline (GPC) may be considered to be a numbered set, so therefore the first pipeline would be the work load and within the pipeline each of the various elements would keep the number naming conservation, on to as many pipelines as necessary, which for the sake of applying art will be considered at least 4 but could be more.); execute a first graphics workload in the set of graphics workloads, wherein the first graphics workload is associated with first data (See col. 9 lines 66 – col. 10 lines 25, “The TEXIN unit 402 includes a command and data conditioning unit (not shown) that reroutes global, local, or surface store data to bypass the main processing path in the texture processing pipeline 400 . The command and data conditioning unit also performs various checks to determine whether incoming the texture and non-texture load/store operations are legal. For example, certain memory access operations related to textures and surfaces could be associated with a texture header, where a texture header stores information describing characteristics of the given texture surface, including, without limitation, the type, format, dimensions, storage structure, and base address of the memory allocated to the texture or surface. If the incoming memory access operation is associated with a texture header, then the command and data conditioning unit determines whether the received memory access operation is consistent with the associated texture header, according to the type of memory access operation. If the received memory access operation is inconsistent with the texture header, then the command and data conditioning unit corrects such inconsistencies. In some embodiments, other units within the texture processing pipeline 400 may also include command and data conditioning logic.” The previous citation shows several types of indications of a graphic workload(s).); and store, […]on the execution of the first graphics workload, second data that is associated with a second graphics workload in the set of graphics workloads (See col. 9 lines 66 – col. 10 lines 25, “The TEXIN unit 402 includes a command and data conditioning unit (not shown) that reroutes global, local, or surface store data to bypass the main processing path in the texture processing pipeline 400 . The command and data conditioning unit also performs various checks to determine whether incoming the texture and non-texture load/store operations are legal. For example, certain memory access operations related to textures and surfaces could be associated with a texture header, where a texture header stores information describing characteristics of the given texture surface, including, without limitation, the type, format, dimensions, storage structure, and base address of the memory allocated to the texture or surface. If the incoming memory access operation is associated with a texture header, then the command and data conditioning unit determines whether the received memory access operation is consistent with the associated texture header, according to the type of memory access operation. If the received memory access operation is inconsistent with the texture header, then the command and data conditioning unit corrects such inconsistencies. In some embodiments, other units within the texture processing pipeline 400 may also include command and data conditioning logic.” The previous citation shows several types of indications of a graphic workload(s). See col. 6 lines 8 – 23, “A given GPCs 208 may process data to be written to any of the DRAMs 220 within PP memory 204. Crossbar unit 210 is configured to route the output of each GPC 208 to the input of any partition unit 215 or to any other GPC 208 for further processing. GPCs 208 communicate with memory interface 214 via crossbar unit 210 to read from or write to various DRAMs 220. In one embodiment, crossbar unit 210 has a connection to I/0 unit 205, in addition to a connection to PP memory 204 via memory interface 214, thereby enabling the processing cores within the different GPCs 208 to communicate with system memory 104 or other memory not local to PPU 202. In the embodiment of FIG. 2, crossbar 20 unit 210 is directly connected with I/0 unit 205. In various embodiments, crossbar unit 210 may use virtual channels to separate traffic streams between the GPCs 208 and partition units 215.”) but doesn’t explicitly disclose based at least in part on information stored in the first memory; store, during the execution […]. Ma teaches processing […] based at least in part on information (See title, “Location and 3-D Visual Awareness-Based Dynamic Texture Updating for Indoor 3-D Model” and abstract). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Heinrich in view of Ma as the technologies of Ma yields a predictable, improved result: seamless, realistic texture updates that adapt to the location, thus creating a more realistic virtual world. Heinrich in view of Ma doesn’t explicitly disclose store, during the execution […]. Akeley teaches store, during on the execution of the first graphics workload, second data that is associated with a second graphics workload in the set of graphics workloads ( See abstract, “A system and method for managing multiple frame buffers . The system includes multiple frame buffers, and thus reduces the risk of dropped frames. The system controls and bounds render-to-display latency, and provides an application friendly and effective interface to the frame buffers. The system operates by estimating a latency of a frame that is yet to be rendered. The system determines whether the latency is greater than a target latency. If the latency is greater than the target latency, then the system blocks the application that is responsible for rendering the frame before rendering of the frame commences. As a result, render-to-display latency is bounded to the target latency. The system addresses the naming issue by providing the application with access to only the front buffer and the back buffer. In particular, the present system maintains a queue of one or more frame buffers. The newest frame buffer appended to the queue is considered to be the front buffer. The oldest frame buffer in the queue is displayed. A frame buffer not in the queue is considered to be the back buffer. Rendering is enabled to the back buffer. Once rendering to the back buffer is complete, the back buffer is appended to the queue and becomes the new front buffer”). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Heinrich in view of Ma in further view of Akeley as the double buffering of Akeley would allow storing the back buffer while the front buffer is being written to, thus increasing the flexibility and provide smoother rendering. PNG media_image1.png 832 742 media_image1.png Greyscale Figure 1 of Heinrich: Annotations explaining the different components of Figure 1. PNG media_image2.png 894 576 media_image2.png Greyscale PNG media_image3.png 634 622 media_image3.png Greyscale PNG media_image4.png 794 702 media_image4.png Greyscale Fig. 2-4 Regarding claim 2, Heinrich in view of Ma teaches the apparatus of claim 1, wherein to store the second graphics workload, the processor is configured to: store the second graphics workload in a memory at a graphics processor, and wherein the processor is further configured to: determine whether a storage capacity of the memory at the graphics processor is less than or equal to a storage threshold (See col. 7 lines 64 – col. 8 line 26: The examiner notes L1 has a storage threshold being smaller than L1.5, L2 The processor has determined the storage capacity to be less than the storage capacity of L1.5 and L.2 thus why those caches are used.). Regarding claim 8, Heinrich in view of Ma teaches the apparatus of claim 2, wherein the memory at the graphics processor is a graphics memory (GMEM) or a persistent GMEM (PGMEM) (See col. 24 lines 55 – col. 25 line 3. A PGMEM may be a CDROM or any other permanently storage. The other storage types may be a GMEM). Regarding claim 9, Heinrich in view of Ma teaches the apparatus of claim 1, wherein the processor is further configured to: store the first data associated with the first graphics workload in the set of graphics workloads; and retrieve, prior to the execution of the first graphics workload, the first data associated with the first graphics workload (See Fig. 2-4. See col. 3 lines 45- col. 6 lines 58, for general explanation of Fig. 2. See col. 6 lines 59-col 8 lines 6, for general explanation of Fig. 3. See col. 9 lines 4 – col. 19 lines 57, for general explanation of Fig. 4. The first workload is going to be stored along with any of the data associated prior to it being executed at various stages of the pipeline) Regarding claim 10, Heinrich in view of Ma teaches the apparatus of claim 1, wherein the processor is further configured to: output, prior to storage of the second data, an indication to store the second data that is associated with the second graphics workload (See Fig. 2-4. See col. 3 lines 45- col. 6 lines 58, for general explanation of Fig. 2. See col. 6 lines 59-col 8 lines 6, for general explanation of Fig. 3. See col. 9 lines 4 – col. 19 lines 57, for general explanation of Fig. 4.). Regarding claim 11, Heinrich in view of Ma teaches the apparatus of claim 10, wherein to output the indication to store the second data, the processor is configured to: output, by a graphics driver at a graphics processor, the indication to store the second data (See col. 3 line 45 – 67, col. 4 lines 51 - 67). Regarding claim 12, Heinrich in view of Ma teaches the apparatus of claim 1, wherein to store the second data that is associated with the second graphics workload, the processor is configured to: store the second data that is associated with the second graphics workload simultaneously as the execution of the first graphics workload (See Fig. 2-4. See col. 3 lines 45- col. 6 lines 58, for general explanation of Fig. 2. See col. 6 lines 59-col 8 lines 6, for general explanation of Fig. 3. See col. 9 lines 4 – col. 19 lines 57, for general explanation of Fig. 4.). Regarding claim 13, Heinrich in view of Ma teaches the apparatus of claim 1, wherein the first data includes at least one of first texture data, a first texture, or a first texture resource, and wherein the second data includes at least one of second texture data, a second texture, or a second texture resource (See col. 9 lines 66 – col. 10 line 36). Regarding claim 14, Heinrich in view of Ma teaches the apparatus of claim 1, wherein the second graphics workload is subsequent to the first graphics workload in a workload order of a graphics pipeline at a graphics processor (See Fig. 2-4. See col. 3 lines 45- col. 6 lines 58, for general explanation of Fig. 2. See col. 6 lines 59-col 8 lines 6, for general explanation of Fig. 3. See col. 9 lines 4 – col. 19 lines 57, for general explanation of Fig. 4. See col. 14 line 72 – 51, the process may occur serially when conflicts occur.). Regarding claim 15, Heinrich in view of Ma teaches the apparatus of claim 1, wherein the processor is further configured to: retrieve, after storage of the second data, the second data that is associated with the second graphics workload; and output, based on the retrieval, the second data that is associated with the second graphics workload (See Fig. 2-4. See col. 3 lines 45- col. 6 lines 58, for general explanation of Fig. 2. See col. 6 lines 59-col 8 lines 6, for general explanation of Fig. 3. See col. 9 lines 4 – col. 19 lines 57, for general explanation of Fig. 4.). Regarding claim 16, Heinrich in view of Ma teaches the apparatus of claim 15, wherein to output the second data that is associated with the second graphics workload, the processor is configured to: output, to a shader processor (SP) at a graphics processor, the second data that is associated with the second graphics workload (See col. 6 lines 24 – col. 6 lines 40). Regarding claim 17, Heinrich in view of Ma teaches the apparatus of claim 1, wherein the processor is further configured to: output an indication of storage of the second data that is associated with the second graphics workload (See Fig. 2-4. See col. 3 lines 45- col. 6 lines 58, for general explanation of Fig. 2. See col. 6 lines 59-col 8 lines 6, for general explanation of Fig. 3. See col. 9 lines 4 – col. 19 lines 57, for general explanation of Fig. 4). Regarding claim 18, Heinrich in view of Ma teaches the apparatus of claim 17, wherein to output the indication of the storage of the second data that is associated with the second graphics workload, the processor is configured to: transmit the indication of the storage of the second data that is associated with the second graphics workload; or store the indication of the storage of the second data that is associated with the second graphics workload (See Fig. 2-4. See col. 3 lines 45- col. 6 lines 58, for general explanation of Fig. 2. See col. 6 lines 59-col 8 lines 6, for general explanation of Fig. 3. See col. 9 lines 4 – col. 19 lines 57, for general explanation of Fig. 4) . 07-21-aia AIA Claim (s) 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Heinrich et al. (US 9,595,075 B2) in view of Akeley (US Patent No. 5,933,155) . Claim 19 recites similar limitations to that of claim 20 and thus is rejected under similar rationale as detailed below. Claim 20 doesn’t recite, a method of graphics processing: comprising: Heinrich a method of graphics processing: comprising: (See col. 1 lines 62 – col. 2 line 20, recites a method of graphic processing). Therefore claim 19 is rejected under similar rationale as claim 20 as detailed below. Regarding claim 20, Heinrich teaches a computer-readable medium […] computer executable code (See Heinrich col. 2 line 12 – 20, “Other embodiments include, without limitation, a computer-readable medium that includes instructions that enable a processing unit to implement one or more aspects of the disclosed methods.”) for graphics processing (See title, “ Load/store Operations In Texture Hardware” The load or storing operations of texture are graphic processing), the code when executed by a processor causes the processor to (See Heinrich col. 2 line 12 – 20, “Other embodiments include, without limitation, a computer-readable medium that includes instructions that enable a processing unit to implement one or more aspects of the disclosed methods.”): obtain an indication of a set of graphics workloads associated with the graphics processing (See col. 9 lines 66 – col. 10 lines 25, “The TEXIN unit 402 includes a command and data conditioning unit (not shown) that reroutes global, local, or surface store data to bypass the main processing path in the texture processing pipeline 400 . The command and data conditioning unit also performs various checks to determine whether incoming the texture and non-texture load/store operations are legal. For example, certain memory access operations related to textures and surfaces could be associated with a texture header, where a texture header stores information describing characteristics of the given texture surface, including, without limitation, the type, format, dimensions, storage structure, and base address of the memory allocated to the texture or surface. If the incoming memory access operation is associated with a texture header, then the command and data conditioning unit determines whether the received memory access operation is consistent with the associated texture header, according to the type of memory access operation. If the received memory access operation is inconsistent with the texture header, then the command and data conditioning unit corrects such inconsistencies. In some embodiments, other units within the texture processing pipeline 400 may also include command and data conditioning logic.” The previous citation shows several types of indications of a graphic workload(s). See Fig. 2-4. See col. 3 lines 45- col. 6 lines 58, for general explanation of Fig. 2. See col. 6 lines 59-col 8 lines 6, for general explanation of Fig. 3. See col. 9 lines 4 – col. 19 lines 57, for general explanation of Fig. 4. ); execute a first graphics workload in the set of graphics workloads, wherein the first graphics workload is associated with first data (See col. 9 lines 66 – col. 10 lines 25, “The TEXIN unit 402 includes a command and data conditioning unit (not shown) that reroutes global, local, or surface store data to bypass the main processing path in the texture processing pipeline 400 . The command and data conditioning unit also performs various checks to determine whether incoming the texture and non-texture load/store operations are legal. For example, certain memory access operations related to textures and surfaces could be associated with a texture header, where a texture header stores information describing characteristics of the given texture surface, including, without limitation, the type, format, dimensions, storage structure, and base address of the memory allocated to the texture or surface. If the incoming memory access operation is associated with a texture header, then the command and data conditioning unit determines whether the received memory access operation is consistent with the associated texture header, according to the type of memory access operation. If the received memory access operation is inconsistent with the texture header, then the command and data conditioning unit corrects such inconsistencies. In some embodiments, other units within the texture processing pipeline 400 may also include command and data conditioning logic.” The previous citation shows several types of indications of a graphic workload(s).); and store, […] on the execution of the first graphics workload, second data that is associated with a second graphics workload in the set of graphics workloads (See col. 9 lines 66 – col. 10 lines 25, “The TEXIN unit 402 includes a command and data conditioning unit (not shown) that reroutes global, local, or surface store data to bypass the main processing path in the texture processing pipeline 400 . The command and data conditioning unit also performs various checks to determine whether incoming the texture and non-texture load/store operations are legal. For example, certain memory access operations related to textures and surfaces could be associated with a texture header, where a texture header stores information describing characteristics of the given texture surface, including, without limitation, the type, format, dimensions, storage structure, and base address of the memory allocated to the texture or surface. If the incoming memory access operation is associated with a texture header, then the command and data conditioning unit determines whether the received memory access operation is consistent with the associated texture header, according to the type of memory access operation. If the received memory access operation is inconsistent with the texture header, then the command and data conditioning unit corrects such inconsistencies. In some embodiments, other units within the texture processing pipeline 400 may also include command and data conditioning logic.” The previous citation shows several types of indications of a graphic workload(s). See col. 6 lines 8 – 23, “A given GPCs 208 may process data to be written to any of the DRAMs 220 within PP memory 204. Crossbar unit 210 is configured to route the output of each GPC 208 to the input of any partition unit 215 or to any other GPC 208 for further processing. GPCs 208 communicate with memory interface 214 via crossbar unit 210 to read from or write to various DRAMs 220. In one embodiment, crossbar unit 210 has a connection to I/0 unit 205, in addition to a connection to PP memory 204 via memory interface 214, thereby enabling the processing cores within the different GPCs 208 to communicate with system memory 104 or other memory not local to PPU 202. In the embodiment of FIG. 2, crossbar 20 unit 210 is directly connected with I/0 unit 205. In various embodiments, crossbar unit 210 may use virtual channels to separate traffic streams between the GPCs 208 and partition units 215.”) but the primary embodiment doesn’t explicitly disclose storing computer executable code; store, during the execution […] Heinrich teaches storing computer executable code (See col. 2 lines 21 – 26, “One advantage of the disclosed approach is that the same processing and cache memory may be used for both texture operations and load/store operations to various other address spaces . As a result, surface area decreases and power consumption is reduced as compared with a system with separate texture and Ll caches.” The examiner notes the cache memory can be interpreted to a be a medium and is storing instructions. Instructions can be considered executable code.) Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaches of Heinrich primary embodiment in view of the teachings of Heinrich because “As a result, surface area decreases and power consumption is reduced as compared with a system with separate texture and Ll caches.” (See Heinrich col. 2 line 25 – 26). Heinrich doesn’t explicitly disclose store, during the execution […]. Akeley teaches store, during on the execution of the first graphics workload, second data that is associated with a second graphics workload in the set of graphics workloads ( See abstract, “A system and method for managing multiple frame buffers . The system includes multiple frame buffers, and thus reduces the risk of dropped frames. The system controls and bounds render-to-display latency, and provides an application friendly and effective interface to the frame buffers. The system operates by estimating a latency of a frame that is yet to be rendered. The system determines whether the latency is greater than a target latency. If the latency is greater than the target latency, then the system blocks the application that is responsible for rendering the frame before rendering of the frame commences. As a result, render-to-display latency is bounded to the target latency. The system addresses the naming issue by providing the application with access to only the front buffer and the back buffer. In particular, the present system maintains a queue of one or more frame buffers. The newest frame buffer appended to the queue is considered to be the front buffer. The oldest frame buffer in the queue is displayed. A frame buffer not in the queue is considered to be the back buffer. Rendering is enabled to the back buffer. Once rendering to the back buffer is complete, the back buffer is appended to the queue and becomes the new front buffer”). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Heinrich in view of Akeley as the double buffering of Akeley would allow storing the back buffer while the front buffer is being written to, thus increasing the flexibility and provide smoother rendering. PNG media_image2.png 894 576 media_image2.png Greyscale PNG media_image3.png 634 622 media_image3.png Greyscale PNG media_image4.png 794 702 media_image4.png Greyscale Fig. 2-4 Conclusion 07-40 AIA Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL . See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROBERT J CRADDOCK whose telephone number is (571)270-7502. The examiner can normally be reached Monday - Friday 10:00 AM - 6 PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Devona E Faulk can be reached at 571-272-7515. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ROBERT J CRADDOCK/Primary Examiner, Art Unit 2618 Application/Control Number: 18/764,097 Page 2 Art Unit: 2618 Application/Control Number: 18/764,097 Page 3 Art Unit: 2618 Application/Control Number: 18/764,097 Page 4 Art Unit: 2618 Application/Control Number: 18/764,097 Page 5 Art Unit: 2618 Application/Control Number: 18/764,097 Page 6 Art Unit: 2618 Application/Control Number: 18/764,097 Page 7 Art Unit: 2618 Application/Control Number: 18/764,097 Page 8 Art Unit: 2618 Application/Control Number: 18/764,097 Page 9 Art Unit: 2618 Application/Control Number: 18/764,097 Page 10 Art Unit: 2618 Application/Control Number: 18/764,097 Page 11 Art Unit: 2618 Application/Control Number: 18/764,097 Page 12 Art Unit: 2618 Application/Control Number: 18/764,097 Page 13 Art Unit: 2618 Application/Control Number: 18/764,097 Page 14 Art Unit: 2618 Application/Control Number: 18/764,097 Page 15 Art Unit: 2618 Application/Control Number: 18/764,097 Page 16 Art Unit: 2618 Application/Control Number: 18/764,097 Page 17 Art Unit: 2618 Application/Control Number: 18/764,097 Page 18 Art Unit: 2618 Application/Control Number: 18/764,097 Page 19 Art Unit: 2618 Application/Control Number: 18/764,097 Page 20 Art Unit: 2618 Application/Control Number: 18/764,097 Page 21 Art Unit: 2618 Application/Control Number: 18/764,097 Page 22 Art Unit: 2618 Application/Control Number: 18/764,097 Page 23 Art Unit: 2618
Prosecution Insights