DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a response to the amendment filed 1/23/2026. Claims 1-10 are pending and are under examination.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US 2010/0244935).
Regarding claim 1, Kim et al.’s figure 7 shows A level shifting circuit based on low power source (VDD), comprising low power source (VDD), inverter (inverters coupled to IN, and IN1) and voltage conversion circuit (600), the low power source is connected to the power terminal of the inverter, wherein a boosting capacitor circuit (400, 500) is provided between the inverter and the voltage conversion circuit, the boosting capacitor circuit controls the current flow from the low power source to the voltage conversion circuit, generating a converted high voltage that is twice the voltage value (IN1’ and IN2 are at 2VDD) of the low power source, and outputs the converted high voltage through the voltage conversion circuit as called for in claim 1.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 5, 6, 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over LeChevalier (US 2003/0137341) in view of Kim et al. (US 2010/0244935).
Regarding claim 1, LeChevalier’s figure 2 shows A level shifting circuit based on low power source (102), comprising low power source (102), inverter (inverters 204, 206, 208 are low power source inverters) and voltage conversion circuit (108), the low power source is connected to the power terminal of the inverter (inverters 204, 206, 208 are low power source inverters, thus, it inherently receives the power supply from the low power source, see paragraph 0052, lines 1-4, paragraph 0059, lines 4-8), wherein a boosting capacitor circuit (106) is provided between the inverter and the voltage conversion circuit, the boosting capacitor circuit controls the current flow from the low power source to the voltage conversion circuit, generating a converted high voltage that is three times the voltage value of the low power source, and outputs the converted high voltage through the voltage conversion circuit.
The difference seen between LeChevalier reference and the present invention is that LeChevalier’s boosting capacitor circuit generates a converted high voltage that is three times the voltage value of the low power source instead of being twice the voltage value of the low power source as called for in claim 1. However, one skilled in the art would have been readily recognized that the generated high voltage can be at any multiple levels of the low power source dependent upon a particular application. Kim et al.’s figure 7, in particular, illustrates that an output of a boosting capacitor circuit (400) can be at twice the low power source (2VDD). Therefore, it would have been obvious to person skilled in the art before the effective filing date of the invention to reduce LeChavlier’s boosting circuit to one stage boosting circuit for providing an output voltage at twice the low power source as taught by Kim reference.
Regarding claim 2, the combination of LeChevalier and Kim et al. reference, as noted above, shows the boosting capacitor circuit comprises a first unidirectional conducting tube (202B), a second unidirectional conducting tube (202C) and a boosting capacitor (211), the first unidirectional conducting tube and the second unidirectional conducting tube are connected to control current flow from the low power source to the voltage conversion circuit, the lower plate of the boosting capacitor is connected to the output end of the inverter (210), and the upper plate of the boosting capacitor is connected to the connection ends of the first unidirectional conducting tube and the second unidirectional conducting tube, and a converted high voltage that is twice the voltage value of the low power source is generated at the connection end.
Regarding claim 5, the combination of LeChevalier and Kim et al. reference, as noted above, shows the boosting capacitor circuit further comprises a voltage holding capacitor (212), the upper plate of the voltage holding capacitor is connected to one end of the voltage conversion circuit, and the lower plate of the voltage holding capacitor is grounded.
Regarding claim 6, the combination of LeChevalier and Kim et al. reference, as noted above, shows wherein the inverter includes a first inverter (208) and a second inverter (210); wherein the first inverter includes a first PMOS transistor and a first NMOS transistor (the inverter 208 inherently has PMOS transistor and NMOS transistor), the gate of the first PMOS transistor and the gate of the first NMOS transistor are connected as the input terminal of the first inverter and connected to the input voltage, the drain of the first PMOS transistor and the drain of the first NMOS transistor are connected as the output terminal of the first inverter, the output terminal of the first inverter is connected to the input terminal of the second inverter, the source of the first PMOS transistor is connected to the low power source, the source of the first NMOS transistor is grounded; wherein the second inverter includes a second PMOS transistor and a second NMOS transistor (the inverter 210 inherently has PMOS transistor and NMOS transistor), the gate of the second PMOS transistor and the gate of the second NMOS transistor are connected as the input terminal of the second inverter, the drain of the second PMOS transistor and the drain of the second NMOS transistor are connected as the output terminal of the second inverter, the output end of the second inverter is connected to the lower plate of the boosting capacitor, the source of the second PMOS transistor is connected to the low power source, the source of the second NMOS transistor is grounded.
Regarding claim 10, the combination of LeChevalier and Kim et al. reference, as noted above in the rejection of claim shows a circuit comprising a method: providing a boosting capacitor circuit between the inverter and the voltage conversion circuit, the boosting capacitor circuit comprises a first unidirectional pass tube, a second unidirectional pass tube and a boosting capacitor, the first unidirectional conducting tube and the second unidirectional conducting tube are connected, the lower plate of the boosting capacitor is connected to the output end of the inverter, and the upper plate of the boosting capacitor is connected to the connection ends of the first unidirectional conducting tube and the second unidirectional conducting tube; controlling current flow from the low power source to the voltage conversion circuit through the first unidirectional conducting tube and the second unidirectional conducting tube; generating a converted high voltage that is twice the voltage value of the low power source by the boosting capacitor circuit, and outputs the converted high voltage through the voltage conversion circuit.
Claim(s) 3, 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over LeChevalier (US 2003/0137341) in view of Kim et al. (US 2010/0244935) and further in view of Soga (US2021/0013841).
Regarding claim 4, the combination of LeChevalier and Kim et al. reference, as noted above, shows wherein the first unidirectional conducting tube and the second unidirectional conducting tube are bipolar transistors instead of being NMOS transistors as called for in claim 4.
Soga teaches that FET usually operates at a lower threshold voltage than a bipolar transistor, thus, enabling a reduction in power consumption (paragraph 0070). Therefore, it would have been obvious to person skilled in the art before the effective filing date of the invention to replace LeChavalier’s bipolar unidirectional conducting tubes with NMOSFETs transistors for the purpose of preserving a battery life as taught by Soga reference.
Regarding claim 3, the combination of LeChevalier , Kim et al. (US 2010/0244935) and Soga (US2021/0013841), as noted above, resulted in the first unidirectional conducting tube and the second unidirectional conducting tube are NMOS transistors instead of being PMOS transistors as called for in claim 3. However, it is notoriously well known in the art that NMOS transistors and PMOS transistors are complementary transistors. A substitution of one for the other, circuit operation remains unchanged. Therefore, outside of any non-obvious results, the obvious of using PMOS transistors over NMOS transistors will not be patentable under 35USC 103.
Claim(s) 7-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over LeChevalier (US 2003/0137341) in view of Kim et al. (US 2010/0244935) and further in view of applicant’s cited prior art figure 1 and Storms (US2011/0050310).
Regarding claims 7-8, the combination of LeChevalier and Kim et al. reference, as noted above, shows a level shifting circuit comprising all aspects of the present invention as noted above except for the voltage conversion circuit as called for in claim 7.
Applicant’s cited prior art figure 1 shows a voltage conversion circuit having 6 transistors that is capable of level shifting an input signal to a desired output signal (Vout). Thus, it would have been obvious to person skilled in the art before the effective filing date of the invention to replace LeChevalier’s voltage conversion circuit (108) with Applicant’s cited prior art voltage conversion for the purpose of level shifting an input signal to a desired output signal as taught by applicant’s cited prior art figure 1.
Regarding claim 9, the combination of LeChevalier, Kim et al. and applicant’s cited prior art figure 1, as noted above, does not show the body of the fifth PMOS transistor connected to the body of the sixth PMOS transistor and connected to the output end of the second unidirectional conducting tube as called for in claim 9. However, it is known in the art that a PMOS transistor is built on an n-type substrate. The drain and source are p-type regions within this n-type substrate. This forms parasitic p-n junctions (diodes) between the source and the substrate, and the drain and the substrate. Connecting the substrate to the highest voltage ensures these diodes are always reverse-biased or at zero bias, preventing unwanted current flow from the drain or source into the substrate. If these junctions were to become forward-biased, it could lead to significant leakage currents or even device malfunction and damage (see Storm (US2011/0050310). Therefore, it would have been obvious to person skilled in the art before the effective filing date to have the body of the fifth PMOS transistor connected to the body of the sixth PMOS transistor and connected to the output end of the second unidirectional conducting tube (highest potential) to prevent leakage current.
Response to Arguments
Applicant's arguments filed 1/23/2026 have been fully considered but they are not persuasive. Regarding the rejection of claim 1 as being anticipated by Kim et al. (US 2010/0244935), applicant argues that The Examiner's assessment does not fully consider the substantial differences in the specific circuit structure, device composition, and boost implementation method of Kim's technical solution found not persuasive. Kim et al. reference, as noted above, is fully anticipated all the claimed limitations. The differences in the specific circuit structure, device composition, and boost implementation method as argued by the applicant are not claimed. Thus, the rejection is deemed proper.
Regarding the rejection of claim 1-2, 5, 6, 10 as being unpatentable over LeChevalier (US 2003/0137341) in view of Kim et al. (US 2010/0244935), applicant also argues that the combined references is fundamentally different from the technical problem of the present invention found not persuasive. The combination of LeChevalier and Kim et al. references, as noted above, fully meets all the claimed limitations. The “fundamentally different” as argued by the applicant is not presented in the claims. Thus, the rejection is deemed proper. Claims 1-2, 5, 6 and 10 remain rejected.
Claims 3, 4 remain rejected as being unpatentable over LeChevalier (US 2003/0137341) in view of Kim et al. (US 2010/0244935) and further in view of Soga (US2021/0013841) since the claimed limitations of all base claims are fully met by the combined references as noted above. Thus, the rejection is deemed proper.
Claims 7-9 indirectly depend from claim 1, and incorporates all the elements of claim 1. As discussed above, the combined teaching of LeChevalier and Kim teach or teach all the elements of claim 1. Thus, the rejection is deemed proper. Claims 7-9 remain rejected.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/TUAN T LAM/Primary Examiner, Art Unit 2843
3/4/2026