DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 5-9, 14, 16, 19 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liao (US 2021/0328029 A1).
Regarding claim 1, Liao discloses a semiconductor device (Figure 1) comprising: a channel layer (Figure 1, reference 181), a barrier layer (Figure 1, reference 182) positioned above the channel layer (Figure 1, reference 181) and including a material (AlGaN) having a different energy band gap from an energy band gap of the channel layer (InAlGaN, GaN; paragraph 0028), a gate electrode (Figure 1, reference 13) positioned above the barrier layer (Figure 1, reference 182), a gate semiconductor layer (Figure 1, reference 16) positioned between the barrier layer (Figure 1, reference 182) and the gate electrode (Figure 1, reference 13), a first source electrode (Figure 1, reference 15) positioned on a first side of the gate electrode (Figure 1, reference 13), and a first drain electrode (Figure 1, reference 11) positioned on a second, opposite side of the gate electrode (Figure 1, reference 13), the first source electrode (Figure 1, reference 15) and the first drain electrode (Figure 1, reference 11) each connected to (thru Figure 1, reference 182) the channel layer (Figure 1, reference 181), a lower protection layer (Figure 1, reference 141) covering the barrier layer (Figure 1, reference 182) and the gate electrode (Figure 1, reference 13), a first field dispersion plate (Figure 1, reference 12) connected to the first source electrode (Figure 1, reference 15) and positioned above the lower protection layer (Figure 1, reference 141), and a first interlayer insulating layer (Figure 1, reference 17) positioned above the first field dispersion plate (Figure 1, reference 12) and the lower protection layer (Figure 1, reference 141) and including a first element of a first content (at%) in relation to (paragraph 0041) the entire first interlayer insulating layer (Figure 1, reference 17), wherein the lower protection layer (Figure 1, reference 141) includes the first element of which a second content (at%) in relation to the entire lower protection layer is less than the first content (at%) (paragraphs 0034-0036).
Regarding claim 2, Liao discloses wherein: the first content (at%) is not constant throughout a thickness of the entire first interlayer insulating layer, and increases as a distance away from the bottom surface of the lower protection layer increases (paragraph 0049).
Regarding claim 3, Liao discloses wherein: the second content (at%) is not constant throughout a thickness of the entire lower protection layer, and increases, at least for a portion of the lower protection layer, as a distance away from the bottom surface of the lower protection layer increases (paragraph 0049).
Regarding claim 5, Liao discloses wherein: the first element is nitrogen (paragraph 0033; Si3N4).
Regarding claim 6, Liao discloses wherein: the first interlayer insulating layer (Figure 1, reference 141) and the lower protection layer (Figure 1, reference 17) each include silicon oxynitride, silicon carbon nitride, silicon oxycarbonitride, silicon nitride, or a combination thereof (paragraphs 0033 and 0038; silicon nitride).
Regarding claim 7, Liao discloses wherein: the first interlayer insulating layer (Figure 1, reference 17) includes silicon oxynitride, silicon carbon nitride, silicon oxycarbonitride, silicon nitride, or a combination thereof (paragraph 0038; silicon nitride), and the lower protection layer (Figure 1, reference 141) includes silicon oxide, silicon carbon oxide, or a combination thereof (paragraph 0033; silicon oxide).
Regarding claim 8, Liao discloses wherein: the second content (at%) of the first element of the lower protection layer is greater than 0 at% and less than 1 at% (Figure 1, reference 141; paragraph 0033).
Regarding claim 9, Liao discloses wherein: the first content (at%) of the first element of the first interlayer insulating layer is equal to or greater than 3 at% and less than 30 at% (Figure 1, reference 17; paragraph 0038).
Regarding claim 14, Liao discloses wherein: the lower protection layer (Figure 1, reference 141) includes: a first lower protection layer (Figure 1, reference 141) positioned on the barrier layer (Figure 1, reference 182) and including the first element of a third content (at%) in relation to the entire first lower protection layer (141), and a second lower protection layer (Figure 1, reference 142) positioned between the first lower protection layer (Figure 1, reference 141) and the first field dispersion plate (Figure 1, reference 12) and including the first element of a fourth content (at%) in relation to the entire second lower protection layer (Figure 1, reference 142), the fourth content (at%) different from the third content (at%), and the third content (at%) and the fourth content (at%) are smaller than the first content (at%) of the first element of the first interlayer insulating layer (Figure 1, reference 17; paragraphs 0033-0036 and 0041).
Regarding claim 16, Liao discloses a semiconductor device (Figure 1) comprising: a channel layer (Figure 1, reference 181), a barrier layer (Figure 1, reference 182) positioned above the channel layer (Figure 1, reference 181) and including a material having a different energy band gap from an energy band gap of the channel layer (Figure 1, reference 181), a gate electrode (Figure 1, reference 13) positioned above the barrier layer (Figure 1, reference 182), a gate semiconductor layer (Figure 1, reference 16) positioned between the barrier layer (Figure 1, reference 182) and the gate electrode (Figure 1, reference 13), a first source electrode (Figure 1, reference 15) positioned on a first side of the gate electrode (Figure 1, reference 13), and a first drain electrode (Figure 1, reference 11) positioned on a second, opposite side of the gate electrode (Figure 1, reference 13), the first source electrode (Figure 1, reference 15) and the first drain electrode (Figure 1, reference 11) each connected to the channel layer (Figure 1, reference 181), a lower protection layer (Figure 1, reference 141) covering the barrier layer (Figure 1, reference 182) and the gate electrode (Figure 1, reference 13), a field dispersion plate (Figure 1, reference 12) connected to the source electrode (Figure 1, reference 15) and positioned above the lower protection layer (Figure 1, reference 141), and an interlayer insulating layer (Figure 1, reference 17) positioned above the field dispersion plate (Figure 1, reference 12) and the lower protection layer (Figure 1, reference 141) and including nitrogen (paragraph 0033), wherein the lower protection layer (Figure 1, reference 141) includes a content (at%) of nitrogen in relation to the entire lower protection layer (paragraph 0033-0036) less than the content (at%) of nitrogen of the interlayer insulating layer (Figure 1, reference 17) in relation to the entire interlayer insulating layer (paragraph 0041).
Regarding claim 19, Liao discloses a semiconductor device (Figure 1) comprising: a substrate (Figure 1, reference 19), a channel layer including GaN (Figure 1, reference 181; paragraph 0028) on the substrate (Figure 1, reference 19), a barrier layer (Figure 1, reference 182) positioned above the channel layer (Figure 1, reference 181) and including AlGaN (paragraph 0028) , a gate electrode (Figure 1, reference 13) positioned above the barrier layer (Figure 1, reference 182) and including a metal material (paragraph 0031), a gate semiconductor layer (Figure 1, reference 16) positioned between the barrier layer (Figure 1, reference 182) and the gate electrode (Figure 1, reference 13) and including GaN doped with a P-type impurity (paragraph 0030), a first source electrode (Figure 1, reference 15) positioned on a first side of the gate electrode (Figure 1, reference 13), and a first drain electrode (Figure 1, reference 11) positioned on a second, opposite side of the gate electrode (Figure 1, reference 13), the first source electrode (Figure 1, reference 15) and the first drain electrode (Figure 1, reference 11) each connected to the channel layer (Figure 1, reference 181), a lower protection layer (Figure 1, reference 141) covering the barrier layer (Figure 1, reference 182) and the gate electrode (Figure 1, reference 13), a first field dispersion plate (Figure 1, reference 12) connected to the first source electrode (Figure 1, reference 15), integrated with the first source electrode (Figure 1, reference 15), and positioned above the lower protection layer (Figure 1, reference 141), and a first interlayer insulating layer (Figure 1, reference 17) positioned above the first field dispersion plate (Figure 1, reference 12) and the lower protection layer (Figure 1, reference 141) and including a first element and a second element different from the first element (paragraph 0041), wherein the lower protection layer (Figure 1, reference 141) includes the second element, or the second element and the first element, and the content (at%) of the first element of the lower protection layer in relation to the entire lower protection layer (paragraphs 0033-0036)is smaller than the content (at%) of the first element of the interlayer insulating layer in relation to the entire first interlayer insulating layer (Figure 1, reference 17; paragraph 0041).
Regarding claim 20, Liao discloses wherein: the first element is nitrogen, and the second element is silicon (paragraphs 0033-0036 and 0041).
Allowable Subject Matter
Claims 4, 10-13, 15, 17 and 18 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior are does not disclose nor fairly suggest semiconductor devices comprising: wherein: a maximum value of the second content (at%) in any vertical-level slice of the lower protection layer is less than a minimum value of the first content (at%) in any vertical-level slice of the first interlayer insulating layer (claim 4), further comprising: a second source electrode positioned above the first source electrode, a second drain electrode positioned above the first drain electrode, a second field dispersion plate connected to the second source electrode and positioned above the first interlayer insulating layer, and a second interlayer insulating layer positioned above the second field dispersion plate and the first interlayer insulating layer and including the first element of a third content (at%) in relation to the entire second interlayer insulating layer different from the first content (at%) and the second content (at%) (claim 13), wherein: the first interlayer insulating layer includes: a first sub-interlayer insulating layer positioned above the first field dispersion plate and including the first element of a fifth content (at%) in relation to the entire first sub-interlayer insulating layer, and a second sub-interlayer insulating layer positioned between the lower protection layer and the first field dispersion plate including the first element of a sixth content (at%) in relation to the entire second sub-interlayer insulating layer, the sixth content (at%) different from the fifth content (at%), and the fifth content (at%) and the sixth content (at%) are greater than the second content (at%) of the first element of the lower protection layer (claim 15), incorporated into the claims from which they depend from, further incorporated into independent claim 1 and in the context of its recited apparatus, along with its depending claims and wherein: the field dispersion plate includes: a first field dispersion plate connected to the source electrode and positioned above the lower protection layer, and a second field dispersion plate positioned on the first field dispersion plate, the interlayer insulating layer includes: a first interlayer insulating layer positioned between the first field dispersion plate and the second field dispersion plate and including a first content (at%) of nitrogen in relation to the entire first interlayer insulating layer, and a second interlayer insulating layer positioned on the second field dispersion plate and the first interlayer insulating layer, and the lower protection layer includes nitrogen in a second content (at%) in relation to the entire lower protection layer less than the first content (at%) (claim 17), further incorporated into independent claim 16 and in the context of its recited apparatus, along with its depending claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Hata (11,652,145 B2) discloses a nitride semiconductor device comprising layered structure of active region and method for manufacturing the same (Figure 8).
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/MONICA D HARRISON/ Primary Examiner, Art Unit 2815
mdh
September 1, 2026
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