Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The instant application having application No. 18/764,565 of CURIEL for “NEAR-FIELD COMMUNICATION SYSTEMS AND METHODS FOR REDUCING BEAT FREQUENCY SIGNALS IN THE NEAR-FIELD COMMUNICATION SYSTEMS” filed July 05, 2024 has been examined.
Drawings
Drawings Figures 1-6 submitted on July 05, 2024 are in compliance with the provisions of 37 CFR 1.121(d).
Information Disclosure Statements
The information disclosure statements (IDSs) submitted July 05, 2024 and October 22, 2025 are being considered by the examiner.
Claim Rejections - 35 USC § 102/103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained through the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under pre-AIA 35 U.S.C. 103(a) are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over by the Applicant Submitted Prior Art of DIORIO et al. (U.S. Patent No. 7,304,579 B2) hereinafter “Diorio” in view of the Prior Art of PALEY et al. (U.S. Publication No. 2007/0206701 A1) hereinafter “Paley”.
As to claim 1, Diorio discloses a reader of a communication system (shown in Figure 1 item 12) comprising: an antenna to receive an incoming signal (shown in Figure 1, response data [i.e. an incoming signal],The RFID system 10 includes an RFID reader 12 that transmits information, via a wireless air interface 13, to one or more RFID tags 14. The air interface 13 enables the RFID reader 12, as shown, to provide power, query data and timing information to an RFID tag 14, responsive to which the RFID tag 14 may provide response data, described in Column 4, lines 6-12 and RFID reader 12, ... and a front end 20, coupled to an antenna,... received via the air interface 13 by the antenna, described in Column 4, lines 24-32, meet the claimed [i.e. an antenna to receive an incoming signal]), wherein the incoming signal includes a beat frequency signal due to a magnetic coupling of the reader with another reader (interference may arise (e.g., within the channel 60 illustrated, shown in Figure 6, where multiple RFID readers are co-located within a particular environment. Further, as the backscatter signal frequency is close to the frequency of the reader transmission signal, interference between multiple readers and a tag population may be more acute when utilizing baseband modulation, described in Column 6, lines 46-52 and The RFID reader 12 may also, via the antenna 152, receive a signal from a co-located RFID reader or a co-channel RFID reader, operating within the relevant environment, described in Column 13, lines 38-41, meet the claimed [i.e. wherein the incoming signal includes a beat frequency signal due to a magnetic coupling of the reader with another reader]); a sinusoidal estimator operably connected to the antenna, the sinusoidal estimator being configured to estimate at least one parameter of the beat frequency signal based on the incoming signal (a subcarrier modulation format, FSK modulation utilizes two tones to represent a digital one and digital zero, respectively. Collision detection is performed by observing the relevant two tones that are utilized by the FSK modulation format. For example, where a 2.2 MHz tone is utilized to represent a digital zero and a 3.3 MHz tone is utilized to represent a digital one, the simultaneous transmission of backscatter signals utilizing these tones registers a collision. FSK-modulated backscatter is advantageous in that it facilitates increased reader sensitivity relative to FMO modulation formats, and accordingly may be better suited to a dense reader environment , described in Column 6, line 63 - Column 7, line 5 and the second reader, transmitting the reader-to-tag signal 74, ... have detected that the first reader was already transmitting the reader-to-tag signal 72 within that channel (e.g., utilizing collision detection), and accordingly have hopped to the second half channel."; the estimated parameter is the channel i.e. frequency of other readers, described in Column 7, lines 57-63, meet the claimed [i.e. a sinusoidal estimator operably connected to the antenna, the sinusoidal estimator being configured to estimate at least one parameter of the beat frequency signal based on the incoming signal]); at least one signal synthesizer coupled to the sinusoidal estimator, the at least one signal synthesizer being configured to synthesize a control signal using the at least one parameter of the beat frequency signal (the second reader, transmitting the reader-to-tag signal 74, ... have detected that the first reader was already transmitting the reader-to-tag signal 72 within that channel (e.g., utilizing collision detection), and accordingly have hopped to the second half channel (meaning that the FSK generated are in a different channel), described in Column 7, lines 57-63 and should the selector 176, based on received inputs, determine that the RFID reader 12 is operating in a high-density and noisy RF environment, it may operatively select the non-baseband modulation code module to configure the controller 160 appropriately, described in Column 11, lines 60-64 See also, [count, DEMOD CLK], Item 167 of Figure 17 and described in Column 11, lines 28-34, meet the claimed [i.e. at least one signal synthesizer coupled to the sinusoidal estimator, the at least one signal synthesizer being configured to synthesize a control signal using the at least one parameter of the beat frequency signal]); and at least one circuit operably connected to the antenna and the at least one signal synthesizer to subtract a signal portion from the incoming signal based on the control signal to cancel the beat frequency signal of the incoming signal (implicitly disclosed as shown in Figure 15 by the filter 132; and described in Column 9, lines 22-25 and also Figure 15 illustrates how a filter 132 may be utilized to filter out half-channel transmissions from co-located RFID readers 12, corroborated with Column 16, lines 15-19, (e.g. generating (during tag-to-reader communications) the demodulator clock signal 161 to appropriately demodulate a backscatter signal that is modulated utilizing the selected non-baseband modulation format, meet the claimed [i.e. at least one circuit operably connected to the antenna and the at least one signal synthesizer to subtract a signal portion from the incoming signal based on the control signal to cancel the beat frequency signal of the incoming signal]).
Diorio does not expressly disclose an adder. However, Diorio discloses the use of a filter instead of adder to provide subtraction of a signal portion.
Paley discloses an RFID reader comprising: at least one adder circuit operably connected to the antenna and to subtract a signal portion from the incoming signal based on the control signal to cancel (described in Paragraphs 0116-0117 and 0124).
Thus, given the system of Diorio and having the teaching of Paley disclosing a system at least one adder circuit operably connected to antenna/s and to subtract a signal portion from the incoming signal based on the control signal to cancel that is also well-known and conventional in the art, it would have been obvious to one of ordinary skill in the art at the time of effective filing date of the claimed invention to modify the system of Diorio by incorporating the teaching of Paley such that the system of Diorio to provide a reader of a communication system comprising: an antenna to receive an incoming signal, wherein the incoming signal includes a beat frequency signal due to a magnetic coupling of the reader with another reader; a sinusoidal estimator operably connected to the antenna, the sinusoidal estimator being configured to estimate at least one parameter of the beat frequency signal based on the incoming signal; at least one signal synthesizer coupled to the sinusoidal estimator, the at least one signal synthesizer being configured to synthesize a control signal using the at least one parameter of the beat frequency signal; and at least one adder circuit operably connected to the antenna and the at least one signal synthesizer to subtract a signal portion from the incoming signal based on the control signal to cancel the beat frequency signal of the incoming signal, for the obvious advantage of providing a substitution of one conventional circuit by another conventional circuit in an RFID reader to replace a filter by an adder to achieve the same or similar result, which is providing a commonly employed circuit design option that may be achieved by simple substitution and routine trial without involving an inventive step.
As to claim 8, the claim recites a method that parallels the system claim 1. Therefore, the analysis discussed above with respect to claim 1 also applies to claim 8. Accordingly, claim 8 is rejected by the combination of Diorio and Paley under the same rationale as set forth above with respect to claim 1.
Claims 2, 9 and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over by the Applicant Submitted Prior Art of DIORIO et al. (U.S. Patent No. 7,304,579 B2) hereinafter “Diorio” in view of the Prior Art of PALEY et al. (U.S. Publication No. 2007/0206701 A1) hereinafter “Paley” and further in view of the Prior Art of KARANDIKAR et al. (U.S. Publication No. 2021/0067163 A1) hereinafter “Karandikar”.
As to claim 2, the combination of Diorio and Paley as set forth above in claim 1, but the combination does not expressly disclose further comprising at least one analog-to-digital converter operably coupled to the antenna, wherein the at least one analog-to-digital converter is configured to convert the incoming signal to a digital signal and wherein the sinusoidal estimator is configured to estimate a phase of the beat frequency signal based on the digital signal.
However, Diorio discloses various manner of transmitting data by using FSK symbols thereby implicitly disclosing an analog-to-digital converter (shown in Figure 7). Diorio further discloses detection of collision by edge detector and the usage of biphase modulation ((e.g. Collision detection is performed utilizing edge detection), thereby indicating the detection of others readers by using the phase of a digital signal shown in Figure 4 and described in Column 6, lines 16-18).
Further, Karandikar discloses a system comprising: at least one analog-to-digital converter (ADCS 394 of Receiver Circuit 320, shown in Figures 3A, 3E and described in Paragraphs 0068 and 0075) that is operably coupled to the antenna (ADCS 394 of Receiver Circuit 320 that is operably coupled to the Antenna Array 330, shown in Figures 3A and described in Paragraphs 0068 and 0075), wherein the at least one analog-to-digital converter is configured to convert the incoming signal to a digital signal and wherein the sinusoidal estimator is configured to estimate a phase of the beat frequency signal based on the digital signal (IF down-conversion circuitry 386 may convert received RF signals to IF. IF processing circuitry 388 may process the IF signals, e.g., via filtering and amplification. Baseband down-conversion circuitry 390 may convert the signals from IF processing circuitry 388 to baseband. Baseband processing circuitry 392 may process the baseband signals, e.g., via filtering and amplification. ADC circuitry 394 may convert the processed analog baseband signals to digital signals, meet the claimed [i.e. wherein the at least one analog-to-digital converter is configured to convert the incoming signal to a digital signal and wherein the sinusoidal estimator is configured to estimate a phase of the beat frequency signal based on the digital signal], described in Paragraph 0075).
Thus, given the system of Diorio as modified by Paley and having the teaching of Karandikar disclosing a system having analog-to-digital converter that is operably coupled to the antenna, wherein the at least one analog-to-digital converter is configured to convert the incoming signal to a digital signal that is also well-known and conventional in the art, it would have been obvious to one of ordinary skill in the art at the time of effective filing date of the claimed invention to modify the combination of Diorio and Paley that at least one analog-to-digital converter is configured to convert the incoming signal to a digital signal and wherein the sinusoidal estimator is configured to estimate a phase of the beat frequency signal based on the digital signal by incorporating the teaching of Karandikar such that the system further comprising at least one analog-to-digital converter that is operably coupled to the antenna, wherein the at least one analog-to-digital converter is configured to convert the incoming signal to a digital signal and wherein the sinusoidal estimator is configured to estimate a phase of the beat frequency signal based on the digital signal, for the obvious advantages as suggested by Karandikar (Paragraph 0001).
As to claim 9, the claim recites a method that parallels the system claim 2. Therefore, the analysis discussed above with respect to claim 2 also applies to claim 9. Accordingly, claim 9 is rejected by the combination of Diorio, Paley and Karandikar under the same rationale as set forth above with respect to claim 2.
As to claim 15, the claim recites a system that parallels the system claims 1 and 2. Therefore, the analysis discussed above with respect to claims 1 and 2 also applies to claim 15. Accordingly, claim 15 is rejected by the combination of Diorio, Paley and Karandikar under the same rationale as set forth above with respect to claims 1 and 2.
As to claim 16, the claim recites a system that parallels the system claim 2. Therefore, the analysis discussed above with respect to claim 2 also applies to claim 16. Accordingly, claim 15 is rejected by the combination of Diorio, Paley and Karandikar under the same rationale as set forth above with respect to claim 2.
Claims 3, 10 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over by the Applicant Submitted Prior Art of DIORIO et al. (U.S. Patent No. 7,304,579 B2) hereinafter “Diorio” in view of the Prior Art of PALEY et al. (U.S. Publication No. 2007/0206701 A1) hereinafter “Paley” and further in view of the Prior Art of KARANDIKAR et al. (U.S. Publication No. 2021/0067163 A1) hereinafter “Karandikar” and further in view of the Prior Art of COOK et al. (U.S. Publication No. 2010/0190436 A1) hereinafter “Cook”.
As to claim 3, the combination of Diorio, Paley and Karandikar as set forth above in claim 1, but the combination does not expressly disclose further comprising a rectifier operably coupled to the antenna, wherein the rectifier is configured to rectify the incoming signal into a rectified signal, wherein the sinusoidal estimator is configured to estimate amplitude and frequency of the beat frequency signal based on the rectified signal.
However, Diorio discloses various manner of transmitting data by using FSK symbols thereby implicitly disclosing an analog-to-digital converter (shown in Figure 7). Diorio further discloses detection of collision by edge detector and the usage of biphase modulation ((e.g. Collision detection is performed utilizing edge detection), thereby indicating the detection of others readers by using the phase of a digital signal shown in Figure 4 and described in Column 6, lines 16-18).
Further, Cook discloses a system comprising: a rectifier operably coupled to the antenna, wherein the rectifier is configured to rectify the incoming signal into a rectified signal, wherein the sinusoidal estimator is configured to estimate amplitude and frequency of the beat frequency signal based on the rectified signal (electronic device 120 includes the receiver 108 may include a matching circuit 132 and a rectifier and switching circuit 134 to generate a DC power output to charge a battery 136 as shown in FIG. 2, meet the claimed [i.e. a rectifier operably coupled to the antenna, wherein the rectifier is configured to rectify the incoming signal into a rectified signal], described in Paragraphs 0024, 0035, 0038 and 0041).
Thus, given the system of Diorio as modified by Paley and Karandikar and having the teaching of Cook disclosing a system having analog-to-digital converter that is operably coupled to the antenna, a rectifier operably coupled to the antenna, wherein the rectifier is configured to rectify the incoming signal into a rectified signal that is also well-known and conventional in the art, it would have been obvious to one of ordinary skill in the art at the time of effective filing date of the claimed invention to modify the combination of Diorio, Paley and Karandikar that the sinusoidal estimator is configured to estimate amplitude and frequency of the beat frequency signal based on the rectified signal by incorporating the teaching of Cook such that the system further comprising a rectifier operably coupled to the antenna, wherein the rectifier is configured to rectify the incoming signal into a rectified signal, wherein the sinusoidal estimator is configured to estimate amplitude and frequency of the beat frequency signal based on the rectified signal, for the obvious advantages as suggested by Cook (Paragraph 0001).
As to claim 4, the combination of Diorio, Paley, Karandikar and Cook as set forth above in claim 1, but the combination does not expressly disclose further comprising at least one low-pass filter between the rectifier and the sinusoidal estimator.
However, Diorio discloses a filter that may be utilized to filter out half-channel transmissions from co-located RFID readers (shown in Figures 10, 15 and described in Column 7, lines 43-63 and Column 9, lines 22-25).
Further, Zakarauskas discloses a system comprising: a low-pass filter between a rectifier and an estimator (rectifier module 204, low pass filtering stage 205 and estimator 208, shown in Figure 2 and described in Paragraphs 0036-0045).
Thus, given the system of Diorio as modified by Paley, Karandikar and Cook and having the teaching of Zakarauskas disclosing a system having a low-pass filter between a rectifier and an estimator that is also well-known and conventional in the art, it would have been obvious to one of ordinary skill in the art at the time of effective filing date of the claimed invention to modify the combination of Diorio, Paley, Karandikar and Cook by incorporating the teaching of Zakarauskas such that the system further comprising at least one low-pass filter between the rectifier and the sinusoidal estimator, for the obvious advantages of signal enhancing as suggested by Zakarauskas (Paragraph 0002).
As to claim 10, the claim recites a method that parallels the system claim 3. Therefore, the analysis discussed above with respect to claim 3 also applies to claim 10. Accordingly, claim 10 is rejected by the combination of Diorio, Paley, Karandikar and Cook under the same rationale as set forth above with respect to claim 3.
As to claim 17, the claim recites a system that parallels the system claim 3. Therefore, the analysis discussed above with respect to claim 3 also applies to claim 17. Accordingly, claim 17 is rejected by the combination of Diorio, Paley, Karandikar and Cook under the same rationale as set forth above with respect to claim 3.
Claims 4, 11 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over by the Applicant Submitted Prior Art of DIORIO et al. (U.S. Patent No. 7,304,579 B2) hereinafter “Diorio” in view of the Prior Art of PALEY et al. (U.S. Publication No. 2007/0206701 A1) hereinafter “Paley” and further in view of the Prior Art of KARANDIKAR et al. (U.S. Publication No. 2021/0067163 A1) hereinafter “Karandikar” and further in view of the Prior Art of COOK et al. (U.S. Publication No. 2010/0190436 A1) hereinafter “Cook” and further in view of the Prior Art of ZAKARAUSKAS et al. (U.S. Publication No. 2013/0231923 A1) hereinafter “Zakarauskas”.
As to claim 4, the combination of Diorio, Paley, Karandikar and Cook as set forth above in claim 1, but the combination does not expressly disclose further comprising at least one low-pass filter between the rectifier and the sinusoidal estimator.
However, Diorio discloses a filter that may be utilized to filter out half-channel transmissions from co-located RFID readers (shown in Figures 10, 15 and described in Column 7, lines 43-63 and Column 9, lines 22-25).
Further, Zakarauskas discloses a system comprising: a low-pass filter between a rectifier and an estimator (rectifier module 204, low pass filtering stage 205 and estimator 208, shown in Figure 2 and described in Paragraphs 0036-0045).
Thus, given the system of Diorio as modified by Paley, Karandikar and Cook and having the teaching of Zakarauskas disclosing a system having a low-pass filter between a rectifier and an estimator that is also well-known and conventional in the art, it would have been obvious to one of ordinary skill in the art at the time of effective filing date of the claimed invention to modify the combination of Diorio, Paley, Karandikar and Cook by incorporating the teaching of Zakarauskas such that the system further comprising at least one low-pass filter between the rectifier and the sinusoidal estimator, for the obvious advantages of signal enhancing as suggested by Zakarauskas (Paragraph 0002).
As to claim 11, the claim recites a method that parallels the system claim 4. Therefore, the analysis discussed above with respect to claim 4 also applies to claim 11. Accordingly, claim 11 is rejected by the combination of Diorio, Paley, Karandikar, Cook and Zakarauskas under the same rationale as set forth above with respect to claim 4.
As to claim 18, the claim recites a system that parallels the system claim 4. Therefore, the analysis discussed above with respect to claim 4 also applies to claim 18. Accordingly, claim 18 is rejected by the combination of Diorio, Paley, Karandikar, Cook and Zakarauskas under the same rationale as set forth above with respect to claim 4.
Claims 5-7, 12-14 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over by the Applicant Submitted Prior Art of DIORIO et al. (U.S. Patent No. 7,304,579 B2) hereinafter “Diorio” in view of the Prior Art of PALEY et al. (U.S. Publication No. 2007/0206701 A1) hereinafter “Paley” and further in view of the Prior Art of KARANDIKAR et al. (U.S. Publication No. 2021/0067163 A1) hereinafter “Karandikar” and further in view of the Prior Art of ROFOUGARAN et al. (U.S. Publication No. 2008/0238622 A1) hereinafter “Rofougaran”.
As to claim 5, the combination of Diorio and Paley as set forth above in claim 1, but the combination does not expressly disclose further comprising at least one second adder circuit connected to the at least one signal synthesizer to add the control signal with one or more outputs from an operation point tracking module.
However, Diorio discloses synthesizer being configured to synthesize a control signal (described in Column 7, lines 57-63 and Column 11, lines 28-34). Also, Paley discloses an adder circuit connected an RFID reader comprising: an adder circuit operably connected to the antenna (described in Paragraphs 0116-0117 and 0124).
Further, Rofougaran, in a same field of endeavor, discloses system that provide two variable gain amplifiers that provide input to limiter/buffer which is as well controlled by the DC offset cancellation module (shown in Figure 6 and described in Paragraphs 0050-0051).
Thus, given the system of Diorio as modified by Paley and Karandikar and having the teaching of Rofougaran disclosing a system having two variable gain amplifiers that provide input to limiter/buffer which is as well controlled by the DC offset cancellation module that is also well-known and conventional in the art, it would have been obvious to one of ordinary skill in the art at the time of effective filing date of the claimed invention to modify the combination of Diorio, Paley and Karandikar by incorporating the teaching of Rofougaran such that the system further comprising at least one second adder circuit connected to the at least one signal synthesizer to add the control signal with one or more outputs from an operation point tracking module, for the obvious advantages of signal enhancing as suggested by Rofougaran (Paragraph 0002).
As to claim 6, , the combination of Diorio, Paley, Karandikar and Rofougaran as set forth above in claim 5, and further the combination discloses (signal is fed into the adder 242 where it is added to the incoming signal, thereby cancelling carrier leakage and its associated phase noise, antenna to antenna coupling, environment-reflected noise, etc., adder 242, shown in Figure 2 and described Paragraphs 0116 of Paley), it would have been obvious to one of ordinary skill in the art at the time of effective filing date of the claimed invention to further modify the combination of Diorio, Paley and Rofougaran such that the system further comprising at least one digital-to-analog converter operably connected to the at least one second adder circuit to convert a signal from the at least one second adder circuit to an analog signal, wherein the at least one digital-to-analog converter is connected to the at least one adder circuit to provide the analog signal to the at least one adder circuit, for the obvious advantages of signal enhancing as suggested by Rofougaran (Paragraph 0002).
As to claim 7, the combination of Diorio and Paley as set forth above in claim 1, further Diorio discloses wherein the at least one signal synthesizer includes a single signal synthesizer that is used for both in-phase (I) and quadrature (Q) channels.
However, Diorio discloses synthesizer being configured to synthesize a control signal (described in Column 7, lines 57-63 and Column 11, lines 28-34). Also, Paley discloses an adder circuit connected an RFID reader comprising: an adder circuit operably connected to the antenna (described in Paragraphs 0116-0117 and 0124). And, Zakarauskas discloses a system comprising: a low-pass filter between a rectifier and an estimator (rectifier module 204, low pass filtering stage 205 and estimator 208, shown in Figure 2 and described in Paragraphs 0036-0045).
Further, Rofougaran, in a same field of endeavor, discloses system that provide a signal synthesizer includes that is used for both in-phase (I) and quadrature (Q) channels (shown in Figure 5 and described in Paragraphs 0042 and 0047).
Thus, given the system of Diorio as modified by Paley and Karandikar and having the teaching of Rofougaran disclosing a system having a signal synthesizer used for both in-phase (I) and quadrature (Q) channels that is also well-known and conventional in the art, it would have been obvious to one of ordinary skill in the art at the time of effective filing date of the claimed invention to modify the combination of Diorio, Paley and Karandikar by incorporating the teaching of Rofougaran such that the system wherein the at least one signal synthesizer includes a single signal synthesizer that is used for both in-phase (I) and quadrature (Q) channels, for the obvious advantages of signal enhancing as suggested by Rofougaran (Paragraph 0002).
As to claim 12, the claim recites a method that parallels the system claim 5. Therefore, the analysis discussed above with respect to claim 5 also applies to claim 12. Accordingly, claim 12 is rejected by the combination of Diorio, Paley, Karandikar and Zakarauskas under the same rationale as set forth above with respect to claim 5.
As to claim 13, the claim recites a method that parallels the system claim 6. Therefore, the analysis discussed above with respect to claim 6 also applies to claim 13. Accordingly, claim 13 is rejected by the combination of Diorio, Paley, Karandikar and Zakarauskas under the same rationale as set forth above with respect to claim 6.
As to claim 14, the claim recites a method that parallels the system claim 7. Therefore, the analysis discussed above with respect to claim 7 also applies to claim 14. Accordingly, claim 14 is rejected by the combination of Diorio, Paley, Karandikar and Zakarauskas under the same rationale as set forth above with respect to claim 7.
As to claim 19, the claim recites a system that parallels the system claim 5. Therefore, the analysis discussed above with respect to claim 5 also applies to claim 19. Accordingly, claim 19 is rejected by the combination of Diorio, Paley, Karandikar and Zakarauskas under the same rationale as set forth above with respect to claim 5.
As to claim 20, the claim recites a system that parallels the system claim 6. Therefore, the analysis discussed above with respect to claim 6 also applies to claim 20. Accordingly, claim 20 is rejected by the combination of Diorio, Paley, Karandikar and Zakarauskas under the same rationale as set forth above with respect to claim 6.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The following cited arts are further to show the state of related art.
U.S. Publication No. 2022/0399640 A1 of JAMIN et al, discloses an RFID device, comprising: a transmitter, a matching device, and a receiver. The transmitter is hereby coupled via the matching device to the receiver. The transmitter is configured to transmit a transmitter signal through the matching device, thereby obtaining a calibration signal. The receiver is configured to receive the calibration signal and estimate a phase shift of the calibration signal. Further, the RFID device is configured to adjust at least one of a transmitter phase shift and a receiver phase shift in order to compensate for the estimated phase shift. Further, a method of calibrating a phase shift in an RFID device
Correspondence
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/SISAY YACOB/ February 9, 2026 Primary Examiner, Art Unit 2686