Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6 and 11-18 are rejected under 35 U.S.C. 102(a1) as being anticipated by Kaulio et al. (Pub NO. US 2006/0043412 A1; hereinafter Kaulio).
Regarding Claim 1, Kaulio teaches an electric circuit (electronic circuit in Fig. 2 and Fig. below; See [0016]-[0033]) comprising:
a plurality of electrically connected thyristors (plurality of Thyristor TW, TV and TU in Fig. 2 and fig. below; See [0016]-[0017]),
each thyristor having a gate terminal (See [0020]) electrically connected to a respective gate drive unit adapted to generate gate pulses for triggering the thyristor (gate of each thyristor TW, TV and TU is connected to gate drive W1, V1 and U1 by gate current circuit 25 in Fig. 2 and Fig. below; See [0016]-[0017], [0023], [0029]);
wherein at least one of the plurality of gate drive units is adapted to measure the gate voltage of the respective thyristor (controller 27 measure gate voltages by 28 in Fig. 2 and Fig. blow; See [0019]) after one or more gate pulses have been applied to the gate terminal of the respective thyristor (27 measures gate voltage through 28 all time, therefore after pulse has been applied in Fig. 2 and Fig. blow; See [0019]-[0020]).
PNG
media_image1.png
854
812
media_image1.png
Greyscale
Regarding Claim 2, Kaulio teaches an electric circuit according to claim 1, wherein the thyristors are electrically connected in parallel (each thyristor TW, TV and TU are connected in parallel in Fig. 2; See [0016]-[0017]).
Regarding Claim 3, Kaulio teaches an electric circuit according to claim 1, wherein each gate drive unit is adapted to measure the gate voltage of the respective thyristor after one or more gate pulses have been applied to the respective thyristor (operating voltage is shown by LED, therefore this voltage is visual before and after gate pulses has been applied to thyristors in Fig. 2 and Fig. blow; See [0016]-[0020]).
Regarding Claim 4, Kaulio teaches an electric circuit according to claim 1, wherein the at least one gate drive unit is adapted to measure the gate voltage of the respective thyristor after a period of time has elapsed following the end of an applied gate pulse, wherein the period of time is at least 1 µs (operating voltage is shown by LED, therefore this voltage is visual before and after gate pulses has been applied to thyristors in Fig. 2 and Fig. blow; See [0016]-[0020]).
Regarding Claim 5, Kaulio teaches an electric circuit according to claim 1, wherein the at least one gate drive unit is adapted to measure the gate voltage of the respective thyristor using a filter (filter comprises diode, resistor and inductor in Fig. 2; See [0016]-[0025]).
Regarding Claim 6, Kaulio teaches an electric circuit according to claim 1, wherein each gate drive unit takes two or more measurements of the gate voltage of the respective thyristor after one or more gate pulses have been applied to the respective thyristor (operating voltage is shown by LED, therefore this voltage is visual before and after gate pulses has been applied to thyristors in Fig. 2 and Fig. blow; See [0016]-[0020]).
Regarding Claim 11, Kaulio teaches an electric circuit according to claim 1, further comprising a controller that receives the measured gate voltage from each gate drive unit (See [0027]-[0029]), wherein the controller is adapted to shift the start of each gate pulse applied to a thyristor based on the measured gate voltage of the thyristor (shift is change of phase applied to thyristor; See [0027]-[0028]).
Regarding Claim 12, Kaulio teaches a triggering detection method for an electric circuit comprising
a plurality of electrically connected thyristors (plurality of Thyristor TW, TV and TU in Fig. 2 and fig. below; See [0016]-[0017]), the method comprising:
applying one or more gate pulses to a gate terminal of each thyristor (controller 25 applies voltage of each thyristor TW, TV and TU in Fig. 2 and Fig. below; See [0016]-[0017]); and
measuring the gate voltage of at least one thyristor (controller 27 measure gate voltages by 28 in Fig. 2 and Fig. blow; See [0019]).
PNG
media_image1.png
854
812
media_image1.png
Greyscale
Regarding Claim 13, Kaulio teaches a method according to claim 12, wherein the gate voltage of the at least one thyristor is measured after a period of time has elapsed following the end of an applied gate pulse (controller 27 measure gate voltages by 28 all time in Fig. 2 and Fig. blow; See [0019]).
Regarding Claim 14, Kaulio teaches a method according to claim 12, wherein the gate voltage of the at least one thyristor is measured using a filter (filter comprises diode, resistor and inductor in Fig. 2; See [0016]-[0025]).
Regarding Claim 15, Kaulio teaches a method according to claim 12, further comprising measuring the gate voltage of each thyristor after one or more gates pulse have been applied (controller 27 measure gate voltages by 28 all time in Fig. 2 and Fig. blow; See [0019]).
Regarding Claim 16, Kaulio teaches a method according to claim 15, further comprising using the measured gate voltage of each thyristor to estimate (controller 27 measure gate voltages by 28 all time in Fig. 2 and Fig. blow; See [0019]) or determine the instantaneous current flowing through the respective thyristor.
Regarding Claim 17, Kaulio teaches a method according to claim 12, further comprising determining that a thyristor has not been triggered if the measured gate voltage is below a voltage threshold (determine triggered by comparing with threshold; See [0027]-[0028]), and applying one or more further pulses to the non-triggered thyristor (See [0027]-[0028]).
Regarding Claim 18, Kaulio teaches a method according to claim 12, further comprising shifting the start of each gate pulse applied to a thyristor based on the measured gate voltage of the thyristor (shift is change of phase applied to thyristor; See [0027]-[0028]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Kaulio.
Regarding Claim 7, Kaulio teaches an electric circuit according to claim 1, further comprising a controller that receives the measured gate voltage from each gate drive unit (See [0016]-[0024]), wherein the controller is adapted to determine that a thyristor has not been triggered (determine triggered by comparing with threshold; See [0027]-[0028]) if the measured gate voltage of the thyristor is below a voltage threshold (See [0027]-[0028]), wherein the voltage threshold is optionally (See threshold in Fig. 3; See [0030]), but Kaulio is silent about in the range of about 0.5 to about 1.5 volts.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to use the range of about 0.5 to about 1.5 volts, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding Claim 8, Kaulio teaches an electric circuit according to claim 7, wherein the controller is adapted to control the respective gate drive unit to apply one or more further gate pulses to a thyristor that has been determined not to have been triggered (See [0027]-[0028]).
Claim(s) 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Kaulio in view of Morgan et al. (Pub NO. US 2018/0241199 A1; hereinafter Morgan).
Regarding Claim 9, Kaulio teaches an electric circuit according to claim 7, wherein the controller is configured to determine that there is a triggering fault with a thyristor (above threshold or lower threshold id triggering fault; See [0027]-[0028]).
Kaulio is silent about if the controller determines that the thyristor has not been triggered a pre-defined number of times.
Morgan teaches if the controller determines that the thyristor has not been triggered a pre-defined number of times (thyristor is breaker; See [0003]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the system of Kaulio by using if the controller determines that the thyristor has not been triggered a pre-defined number of times, as taught by Morgan in order for the centralized controller commands and coordinates operation of the various circuit protection devices (Morgan ; [0009]).
Regarding Claim 10, Kaulio in view of Morgan teaches an electric circuit according to claim 9. Morgan further teaches wherein the controller is adapted to stop operation of the electric circuit if it determines that there is a triggering fault with a pre-defined number of thyristors of the electric circuit (thyristor is breaker; See [0003]), wherein the pre-defined number of thyristors optionally corresponds to a pre-defined redundancy level (pre-define hierarchy level is pre-defined redundancy level; See [0003]-[0007]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
GONTHIER et al. (Pub NO. US 2020/0395866 A1) discloses Thyristor Control.
Yamada et al. (Patent NO. US 8,902,621 B2) discloses Thyristor Control.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZANNATUL FERDOUS whose telephone number is (571)270-0399. The examiner can normally be reached Monday through Friday 8am to 5pm (PST).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Rodak Lee can be reached at 571-270-5628. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ZANNATUL FERDOUS/Examiner, Art Unit 2858
/LEE E RODAK/Supervisory Patent Examiner, Art Unit 2858