Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Amendment
The amendments filed on 06/18/2026 have been fully considered and are made of record.
Claims 1, 3-18 have been amended.
Claim 2 has been cancelled.
Response to Arguments
Applicant’s arguments filed on 06/18/2026 with respect to claim(s) 1 and 12 have been considered but are moot because the new ground of rejection has been applied to amended limitations.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3-6, 11-18 are rejected under 35 U.S.C. 102(a1) as being anticipated by SHIGETA et al. (Pub NO. US 2020/0186147 A1; hereinafter Shigeta).
Regarding Claim 1, Shigeta teaches an electric circuit (circuit in Fig. 1; See [0023]-[0039]) comprising:
a plurality of electrically connected thyristors (plurality of electrically connected Thyristors T1-T4 in Fig. 1; See [0023]-[0039]),
each thyristor having a gate terminal electrically connected to a respective gate drive unit adapted to generate gate pulses for triggering its respective thyristor (each of T1-T4 are connected to respective gate drive G1-G4 to generate gate pulses to trigger T1-T4 in Fig. 1-Fig. 3; See [0023]-[0039]);
wherein at least one of the plurality of gate drive units is adapted t to measure the gate voltage of its respective thyristor after one or more gate pulses have been applied to the gate terminal of the respective thyristor (controller 6 measures gate voltage G1-G4 of each thyristor T1-T4 in fig. 2-Fig. 3; see [0040]-[0060]); and
wherein the plurality of thyristors are electrically connected in parallel for one switch position (T1 and T3 are connected in parallel; and T2 and T4 are connected in parallel for one switch position on controller 6 in Fig. 1; See [0037]).
Regarding Claim 3, Shigeta teaches an electric circuit according to claim 1, wherein each gate drive unit is adapted to measure the gate voltage of the respective thyristor after one or more gate pulses have been applied to the respective thyristor (controller 6 measures gate voltage of each thyristor T1-T4 in fig. 2-Fig. 3; see [0040]-[0060]).
Regarding Claim 4, Shigeta teaches an electric circuit according to claim 1, wherein the at least one gate drive unit is adapted to measure the gate voltage of the respective thyristor after a period of time has elapsed following the end of an applied gate pulse, wherein the period of time is at least 1 µs (See the time period in Fig. 2-Fig. 3 of gate voltages G1-G4; See [0040]-[0060]).
Regarding Claim 5, Shigeta teaches an electric circuit according to claim 1, wherein the at least one gate drive unit is adapted to measure the gate voltage of the respective thyristor using a filter (See [0130]).
Regarding Claim 6, Shigeta teaches an electric circuit according to claim 1, wherein each gate drive unit takes two or more measurements of the gate voltage of the respective thyristor after one or more gate pulses have been applied to the respective thyristor (See more than two measurement of gate voltages G1-G4 in Fig. 2-Fig. 3; See [0040]-[0060]).
Regarding Claim 11, Shigeta teaches an electric circuit according to claim 1, further comprising a controller that receives the measured gate voltage from each gate drive unit (See [0040]-[0060]), wherein the controller is adapted to shift the start of each gate pulse applied to a thyristor based on the measured gate voltage of the thyristor (shifting of gate pulse G2 and G4 in Fig. 7; See [0099]-[0102]).
Regarding Claim 12, Shigeta teaches a triggering detection method for an electric circuit comprising a plurality of electrically connected thyristors (method in Fig. 1; See [0023]-[0039]), the method comprising:
applying one or more gate pulses to a gate terminal of each respective thyristor (each of T1-T4 are connected to respective gate drive G1-G4 to generate gate pulses to trigger T1-T4 in Fig. 1; See [0023]-[0039]); and
measuring a gate voltage of at least one respective thyristor (controller 6 measures gate voltage G1-G4 of each thyristor T1-T4 in fig. 2-Fig. 3; see [0040]-[0060]);
wherein the plurality of thyristors are electrically connected in parallel for one switch position (T1 and T3 are connected in parallel and T2 and T4 are connected in parallel for one switch position on controller 6 in Fig. 1; See [0037]).
Regarding Claim 13, Shigeta teaches a method according to claim 12, wherein the gate voltage of the at least one thyristor is measured after a period of time has elapsed following the end of an applied gate pulse (See the time period in Fig. 2-Fig. 3 of gate voltages G1-G4; See [0040]-[0060]).
Regarding Claim 14, Shigeta teaches a method according to claim 12, wherein the gate voltage of the at least one thyristor is measured using a filter (See [0130]).
Regarding Claim 15, Shigeta teaches a method according to claim 12, further comprising measuring the gate voltage of each thyristor after one or more gates pulse have been applied (See more than two measurement of gate voltages G1-G4 in Fig. 2-Fig. 3; See [0040]-[0060]).
Regarding Claim 16, Shigeta teaches a method according to claim 15, further comprising using the measured gate voltage of each thyristor to estimate (controller 6 measures gate voltage G1-G4 of each thyristor T1-T4 in fig. 2-Fig. 3; see [0040]-[0060]) or determine the instantaneous current flowing through the respective thyristor.
Regarding Claim 17, Shigeta teaches a method according to claim 12, further comprising determining that a thyristor has not been triggered if the measured gate voltage is below a voltage threshold (load current depends on gate voltage, therefore comparing load current with threshold is comparing gate voltage wit threshold; See [0041]-[0066]), and applying one or more further pulses to the non-triggered thyristor (See [0041]-[0066]).
Regarding Claim 18, Shigeta teaches a method according to claim 12, further comprising shifting the start of each gate pulse applied to a thyristor based on the measured gate voltage of the thyristor (shifting of gate pulse G2 and G4 in Fig. 7; See [0099]-[0102]).
Claim(s) 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Shigeta.
Regarding Claim 7, Shigeta teaches an electric circuit according to claim 1, further comprising a controller that receives the measured gate voltage from each gate drive unit (See measured gate voltage G1-G4 in Fig. 2-Fig. 3), wherein the controller is adapted to determine that a thyristor has not been triggered (determine triggered by comparing with threshold; See [0041]-[0066]) if the measured gate voltage of the thyristor is below a voltage threshold (load current depends on gate voltage, therefore comparing load current with threshold is comparing gate voltage wit threshold; See [0041]-[0066]), wherein the voltage threshold is optionally (See threshold; See [0041]-[0066]), but Shigeta is silent about in the range of about 0.5 to about 1.5 volts.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to use the range of about 0.5 to about 1.5 volts, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233, in order to achieve equal sharing of current (Shigeta; [0005]).
Regarding Claim 8, Shigeta teaches an electric circuit according to claim 7, wherein the controller is adapted to control the respective gate drive unit to apply one or more further gate pulses to a thyristor that has been determined not to have been triggered (comparing with below threshold is not to have been triggered; See [0041]-[0066]).
Claim(s) 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Shigeta in view of Morgan et al. (Pub NO. US 2018/0241199 A1; hereinafter Morgan).
Regarding Claim 9, Shigeta teaches an electric circuit according to claim 7, wherein the controller is configured to determine that there is a triggering fault with a thyristor (above threshold or lower threshold id triggering fault; See [0044]-[0061]).
Shigeta is silent about if the controller determines that the thyristor has not been triggered a pre-defined number of times.
Morgan teaches if the controller determines that the thyristor has not been triggered a pre-defined number of times (thyristor is breaker; See [0003]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the system of Shigeta by using if the controller determines that the thyristor has not been triggered a pre-defined number of times, as taught by Morgan in order for the centralized controller commands and coordinates operation of the various circuit protection devices (Morgan; [0009]).
Regarding Claim 10, Shigeta in view of Morgan teaches an electric circuit according to claim 9. Morgan further teaches wherein the controller is adapted to stop operation of the electric circuit if it determines that there is a triggering fault with a pre-defined number of thyristors of the electric circuit (thyristor is breaker; See [0003]), wherein the pre-defined number of thyristors optionally corresponds to a pre-defined redundancy level (pre-define hierarchy level is pre-defined redundancy level; See [0003]-[0007]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZANNATUL FERDOUS whose telephone number is (571)270-0399. The examiner can normally be reached Monday through Friday 8am to 5pm (PST).
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/ZANNATUL FERDOUS/Examiner, Art Unit 2858
/LEE E RODAK/ Supervisory Patent Examiner, Art Unit 2858
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