DETAILED ACTION
This action is in response to communications: Preliminary-Amendment filed December 11, 2024.
Claims 21-40 are pending in this case. Claims 1-20 have been newly cancelled. No claims have been newly added or amended. This action is made Non-Final.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on October 7, 2024, November 19, 2025, and November 28, 2025 were filed after the filing date of the application on July 5, 2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Drawings
The drawings were received on July 5, 2024. These drawings are accepted.
Double Patenting
The non-statutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A non-statutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on non-statutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a non-statutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 21, 22, 26-29, 33-35, and 38 are rejected on the ground of non-statutory double patenting as being unpatentable over claims 1, 3, 4, 6, 8, 10, 11, 13, and 15 of U.S. Patent No. 12,033,238. Although the claims at issue are not identical, they are not patentably distinct from each other as outlined in the tables below.
Present Application #18/764,603
21
22
26
27
28
29
33
34
35
38
U.S. Patent #12,033,238
1
3
4
6
8
10
11
13
15 & 17
15
Present Application #18/764,603 Claim 21
U.S. Patent #12,033,238 Claim 1
A processor comprising:
A processor comprising:
a plurality of registers; and
a plurality of registers; and
a control unit configured to:
a control unit comprising circuitry configured to:
allocate a first set of registers to a first wavefront being launched on one of a plurality of compute circuits; and
assign a given set of registers of the plurality of registers for exclusive use by a first wavefront;
release one or more registers of the first set of registers while one or more threads of the first wavefront remain active, responsive to a determination that the one or more registers are no longer needed by the first wavefront.
responsive to one or more registers from the given set of registers no longer being needed by the first wavefront: move one or more register values from the one or more registers to one or more different locations in the given set of registers; deallocate the one or more registers from the first wavefront; and assign at least one of the one or more registers for exclusive use by a second wavefront while both the first wavefront and the second wavefront remain active.
Claim 21 of the present application differs from claim 1 of the patent application in that claim 21 of the present application is broader in scope than claim 1 of the patent application, thus encompasses that of the patent application. Additionally, claim 21 of the present application recites its wavefront, “…launched on one of a plurality of compute circuits…” which is not recited by claim 1 of the patent application. However, it is well known in the art that wavefronts execute on compute units, e.g. cores, streaming multi-processors, etc. of a processing unit, such as a graphics processing unit (GPU), which typically operate in parallel. Therefore, it would have been obvious to one of ordinary skill in the art at the time of the invention to modify the processor of the patent application to comprise a plurality of compute circuits to launch wavefronts to be executed, providing parallel processing, thus enhancing the performance of in the system.
Present Application #18/764,603 Claim 22
U.S. Patent #12,033,238 Claim 3
The processor as recited in claim 21, wherein the control circuit is configured to
The processor as recited in claim 1, wherein the control unit is configured to
release the one or more registers in further response to a determination that instructions of the first wavefront that remain to be completed including only instruction that are waiting for an acknowledgment from a memory.
deallocate the one or more registers responsive to receipt of an indication from the first wavefront generated in response to: one or more instructions of the first wavefront having not yet completed execution; and the one or more instructions remaining to be completed only include instructions waiting for an acknowledgment from a memory.
Present Application #18/764,603 Claim 26
U.S. Patent #12,033,238 Claim 4
The processor as recited in claim 25, wherein the control circuit is configured to
The processor as recited in claim 1, wherein
compact the one or more registers of the first set of registers into one or more contiguous blocks of registers by the first wavefront prior to being released.
the one or more registers of the given set of registers are compacted into one or more contiguous blocks of registers prior to reassignment of the one or more registers for exclusive use by the second wavefront.
Present Application #18/764,603 Claim 27
U.S. Patent #12,033,238 Claim 6
The processor as recited in claim 21, wherein the control circuit is configured to
The processor as recited in claim 1, wherein
deallocate the one or more registers responsive to receiving a message from the first wavefront, and wherein the message includes a register base address, a size, and an identifier (ID) of the first wavefront.
the one or more registers are deallocated responsive to receiving a message from the first wavefront, and wherein the message includes a register base address, a size, and an identifier (ID) of the first wavefront.
Present Application #18/764,603 Claim 28
U.S. Patent #12,033,238 Claim 8
A method, comprising:
A method comprising:
allocating, by a control circuit, a first set of registers to a first wavefront being launched on one of a plurality of compute circuits; and
assigning, by circuitry of a control unit, a given set of registers for exclusive use by a first wavefront;
releasing, by the control circuit, one or more registers of the first set of registers while one or more threads of the first wavefront remain active, responsive to a determination that the one or more registers are no longer needed by the first wavefront.
responsive to one or more registers from the given set of registers no longer being needed by the first wavefront: moving, by the control unit, one or more register values from the one or more registers to one or more different locations in the given set of registers; deallocating, by the control unit, the one or more registers from the first wavefront; and assigning, by the control unit, at least one of the one or more registers for exclusive use to a second wavefront, while both the first wavefront and the second wavefront remain active.
Claim 28 of the present application differs from claim 8 of the patent application in that claim 28 of the present application is broader in scope than claim 8 of the patent application, thus encompasses that of the patent application. Additionally, claim 28 of the present application recites its wavefront, “…being launched on one of a plurality of compute circuits…” which is not recited by claim 8 of the patent application. However, it is well known in the art that wavefronts execute on compute units, e.g. cores, streaming multi-processors, etc. of a processing unit, such as a graphics processing unit (GPU), which typically operate in parallel. Therefore, it would have been obvious to one of ordinary skill in the art at the time of the invention to modify the processor of the patent application to comprise a plurality of compute circuits to launch wavefronts to be executed, providing parallel processing, thus enhancing the performance of in the system.
Present Application #18/764,603 Claim 29
U.S. Patent #12,033,238 Claim 10
The method as recited in claim 28, comprising
The method as recited in claim 8, further comprising
releasing the one or more registers in further response to determining that instructions of the first wavefront that remain to be completed including only instruction that are waiting for an acknowledgment from a memory.
deallocating the one or more registers responsive to receipt of an indication from the first wavefront generated in response to: one or more instructions of the first wavefront having not yet completed execution; and the one or more instructions remaining to be completed only including instructions waiting for an acknowledgment from a memory.
Present Application #18/764,603 Claim 33
U.S. Patent #12,033,238 Claim 11
The method as recited in claim 32, further comprising
The method as recited in claim 8, further comprising
compacting, by the control circuit, the one or more registers of the first set of registers into one or more contiguous blocks of registers by the first wavefront prior to being released.
compacting the one or more registers of the given set of registers into one or more contiguous blocks of registers, prior to assigning the one or more registers of the given set of registers for exclusive use by the second wavefront.
Present Application #18/764,603 Claim 34
U.S. Patent #12,033,238 Claim 13
The method as recited in claim 28, further comprising
The method as recited in claim 8, wherein
deallocating, by the control circuit, the one or more registers responsive to receiving a message from the first wavefront, and wherein the message includes a register base address, a size, and an identifier (ID) of the first wavefront.
the one or more registers are deallocated responsive to receiving a message from the first wavefront, and wherein the message includes a register base address, a size, and an identifier (ID) of the first wavefront.
Present Application #18/764,603 Claim 35
U.S. Patent #12,033,238 Claims 15 and 17
A system comprising:
A system comprising:
a memory comprising circuitry configured to store an application; and
a memory; and
a processor coupled to the memory;
a processor coupled to the memory;
wherein the processor comprises circuitry configured to:
wherein the processor comprises circuitry configured to:
execute the application as a plurality of wavefronts;
Limitation A, e.g. first and second wavefront are active, e.g. being executed
allocate a first set of registers to a first wavefront of the plurality of wavefronts being launched on one of a plurality of compute circuits; and
assign a given set of registers for exclusive use by a first wavefront being launched on a first compute unit of a plurality of compute units;
responsive to one or more registers of the given set of registers no longer being needed by the first wavefront: move one or more register values from the one or more registers to one or more different locations in the given set of registers; deallocate the one or more registers from the first wavefront; and assign at least one of the one or more registers for exclusive use by a second wavefront while both the first wavefront and the second wavefront remain active (Limitation A).
release one or more registers of the first set of registers, based at least in part on a determination that only instructions waiting for an acknowledgment from the memory remain to be completed.
…deallocate the one or more registers responsive to receipt of an indication from the first wavefront generated in response to: one or more instructions of the first wavefront having not yet completed execution; and the one or more instructions remaining to be completed only include instructions waiting for an acknowledgment from a memory (claim 17).
Claim 35 of the present application differs from claims 15 and 17 of the patent application in that claim 35 of the present application is broader in scope than claims 15 and 17 of the patent application, thus encompasses that of the patent application. Additionally, claim 35 of the present application recites its memory stores an application and processor to execute the application, where it is well known in the art that an application is software that includes programs that is executed by a processor to perform the operations of a computer system, thus an essential component of the computer system. It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the patent application to store and execute such application in order to perform the operations of the system as described, thus yielding predictable results, without changing the scope of the invention.
Present Application #18/764,603 Claim 38
U.S. Patent #12,033,238 Claim 15
The system as recited in claim 37, wherein the circuitry is configured to
A system comprising…
allocate the one or more registers of the first set of registers marked as being available to the second wavefront being launched on one of the plurality of compute circuits while threads of the first wavefront remain active.
…responsive to one or more registers from the given set of registers no longer being needed by the first wavefront: move one or more register values from the one or more registers to one or more different locations in the given set of registers; deallocate the one or more registers from the first wavefront; and assign at least one of the one or more registers for exclusive use by a second wavefront while both the first wavefront and the second wavefront remain active.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 21-25, 27-32, and 34-39 is/are rejected under 35 U.S.C. 103 as being unpatentable over Eckert et al. (US 2017/0278213) in view of RAWSON, III et al. (US 2011/0296428).
As to claim 21, Eckert et al. disclose a processor (Figure 1, processor 101) comprising: a plurality of registers (register file 115 comprising a plurality of registers); and a control circuit (register file control module 105, further illustrated in Figure 3) configured to: allocate a first set of registers to a first wavefront being launched on one of a plurality of compute circuits ([0015] notes graphics processing unit (GPU) includes a plurality of compute units (CUs) for executing all or a subset of threads of a wavefront concurrently or executing threads for multiple wavefronts concurrently)([0018] notes in order to execute properly, each in-flight wavefront must be assigned a set of registers in register file, and register file control module 105 manages the execution data for each in-flight wavefront based on their corresponding status); and release one or more registers of the first set of registers ([0019] notes register file control module 105 monitors the status of in-flight wavefronts at the GPU 102 and, based on the monitored statuses transfers execution data between register file 115 and register file 116, e.g. register file 105 places execution data for active wavefronts at the register file 115 and execution data for inactive wavefronts at the register file 116, e.g. active wavefronts that becomes inactive no longer need registers of register file 115, thus now available to be utilized by predicted-active wavefronts and/or inactive wavefronts that are now active).
Eckert differ from the invention defined in claim 21 in that Eckert et al. disclose releasing registers when a wavefront becomes inactive, but do not disclose to “…release one or more registers of the first set of registers while one or more threads of the first wavefront remain active, responsive to a determination that the one or more registers are no longer needed by the first wavefront…”
RAWSON, III et al. disclose allocate a first set of registers to a first wavefront (e.g. Figure 5, thread 502 may read and write to some or all of physical registers in subset 512 of physical registers 508; and thread 504 may read and write to some or all of physical registers in subset 518 of physical registers 508, where it may be considered a wavefront encompasses threads)…and release one or more registers of the first set of registers while one or more threads of the first wavefront remain active, responsive to a determination that the one or more registers are no longer needed by the first wavefront (Figure 5, [0069] notes during execution of an application, application may be determine that thread 502 is using only register 514 and not fully utilizing all physical registers 512, e.g. thread 502 may not be utilizing subset 516 of physical register 508, and application may also recognize that another thread, e.g. thread 504, may be able to use more physical registers than subset 518 currently allocated to that thread, [0070] notes reallocating physical registers 516 from thread 502 to thread 504, where thread 502 is not affected because thread 502 was not utilizing physical registers 516 prior to the reallocation, e.g. thus no longer needed, [0071] notes reallocation of registers may occur any number of times during execution of relevant threads).
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify Eckert et al.’s system and method of releasing one or more registers with RAWSON, III et al.’s method of releasing one or more registers while one or more threads of a wavefront remain active such that registers that are not being used may be utilized by other threads, thus improving efficiency in register utilization (see [0067] thru [0071] of RAWSON, III et al.).
As to claim 22, Eckert et al. modified with RAWSON, III et al. disclose the control circuit (Eckert, register file control module 105) is configured to release the one or more registers (Eckert, release registers of register file 115, e.g. by placing execution data at register file 116 for inactive wavefronts, e.g. the active wavefront that becomes inactive) in further response to a determination that instructions of the first wavefront that remain to be completed including only instruction that are waiting for an acknowledgment from a memory (Eckert, [0016] notes an active wavefront can be become inactive as it awaits results of a transaction with system memory, e.g. for a load operation to be sent to system memory or for the results of the load operation to be received at a load/store unit ([0021]), and once the results of the transaction have been returned to the CU (or otherwise reached a designated point at processor 101), the inactive wavefront can be returned to active status, where [0020] notes status of wavefronts identified and decision to place execution data in register file 116 performed by register file control module 105).
As to claim 23, Eckert et al. modified with RAWSON, III et al. disclose the control circuit (Eckert, register file control module 105) is configured to mark the one or more registers of the first set of registers as being available to at least a second wavefront (modified with RAWSON, III, Figure 5, [0069] notes logical registers 510 available to thread 502 may be mapped to subset 512 of physical registers 508, which includes used subset 514 and unused subset 516, where the Figure further illustrates upon reallocation, logical registers are mapped to subset 516 of physical registers 508 that now available to thread 504, where [0055] notes a thread may read and write using some or all of the physical registers in a subset according to a given register mapping).
As to claim 24, Eckert et al. modified with RAWSON, III et al. disclose the instructions of the first wavefront that remain to be completed comprise memory write operations (Eckert, as noted in claim 22, [0021] notes awaiting results of a transaction with system memory, e.g. for a load operation to be sent to system memory or for the results of the load operation to be received at a load/store unit).
As to claim 25, Eckert et al. modified with RAWSON, III et al. disclose the one or more registers of the first set of registers comprise inactive registers that are allocated to the one or more threads of the first wavefront remaining active but that are not being used to store values that will be used by the one or more threads of the first wavefront remaining active (modified with RAWSON, III, as noted in claim 21, subset 516 of physical registers 508 are not be utilized by thread 502, thus “…inactive registers…not being used to store values…” and are reallocated to thread 504 while threads 502 and 504 are executing, thus to “one or more threads of the wavefront remaining active”).
As to claim 27, Eckert et al. modified with RAWSON, III et al. disclose the control circuit (Eckert, register file control module 105) is configured to deallocate the one or more registers (Eckert, deallocate registers of register file 115, e.g. by placing execution data at register file 116 for inactive wavefronts, e.g. the active wavefront that becomes inactive) responsive to receiving a message from the first wavefront (Eckert, e.g. receiving high-latency instructions data 333 and/or signal from an execution stage of the GPU that the instruction has completed, where [0026] notes high-latency instruction data 333 identifies instructions that have been marked by the compiler, or via other characterization and analysis, as requiring a relatively long amount of time to complete execution at the GPU 102, the inactive wavefront detector 332 monitors a fetch stage, dispatch stage, or other stage of the GPU 102 to identify the instructions to be executed by each active wavefront, and in response to identifying an instruction that is listed in the high-latency instruction data 333, the inactive wavefront detector 332 indicates that the corresponding wavefront has transitioned to the inactive state, e.g. thus should place execution data at register file 116, [0027] further notes the inactive wavefront detector 332 awaits a signal from an execution stage or other stage of the GPU 102 for an indication that the instruction has been completed to reset one or more corresponding timers 334, and in response to one or more timers 334 reaching a threshold value, the inactive wavefront detector 332 indicates that the corresponding wavefront has transitioned to the inactive state, e.g. thus should place execution data at register file 116), and wherein the message includes a register base address, a size, and an identifier (ID) of the first wavefront (modified with RAWSON, III, [0060] notes a subset of registers is identifiable by the subset’s “base and bound,” where a base is the address, location, or another identifier of the first register in the subset, e.g. base address and identifier, and a bound is a count or another measure of the number of registers in the subset measured from and including the base register, e.g. size).
As to claim 28, Eckert et al. modified with RAWSON, III et al. disclose a method, comprising the method as performed by the processor of claim 1. Please see the rejection and rationale of claim 1.
Claims 29-32 and 34 are similar in scope to claims 22-25 and 27, respectively, and are therefore rejected under similar rationale.
As to claim 35, Eckert et al. disclose a system (Figure 1, system 100) comprising: a memory (e.g. DRAM 110) comprising circuitry configured to store an application ([0013] notes DRAM 110 store and retrieve data in response to requests from processor 101); and a processor coupled to the memory (e.g. processor 101 with graphics processing unit (GPU) 102 coupled to DRAM 110); wherein the processor (processor 101) comprises circuitry configured to: execute the application as a plurality of wavefronts; allocate a first set of registers to a first wavefront of the plurality of wavefronts being launched on one of a plurality of compute circuits ([0015] notes graphics processing unit (GPU) includes a plurality of compute units (CUs) for executing all or a subset of threads of a wavefront concurrently or executing threads for multiple wavefronts concurrently)([0018] notes in order to execute properly, each in-flight wavefront must be assigned a set of registers in register file, and register file control module 105 manages the execution data for each in-flight wavefront based on their corresponding status); and release one or more registers of the first set of registers ([0019] notes register file control module 105 monitors the status of in-flight wavefronts at the GPU 102 and, based on the monitored statuses transfers execution data between register file 115 and register file 116, e.g. register file 105 places execution data for active wavefronts at the register file 115 and execution data for inactive wavefronts at the register file 116, e.g. active wavefronts that becomes inactive no longer need registers of register file 115, thus now available to be utilized by predicted-active wavefronts and/or inactive wavefronts that are now active), based at least in part on a determination that only instructions waiting for an acknowledgment from the memory remain to be completed ([0016] notes an active wavefront can be become inactive as it awaits results of a transaction with system memory, e.g. for a load operation to be sent to system memory or for the results of the load operation to be received at a load/store unit ([0021]), and once the results of the transaction have been returned to the CU (or otherwise reached a designated point at processor 101), the inactive wavefront can be returned to active status, where [0020] notes status of wavefronts identified and decision to place execution data in register file 116 performed by register file control module 105).
As noted above, Eckert et al. disclose its memory, e.g. DRAM, for storing data for execution by a processor, but do not explicitly disclose its memory “…configured to store an application…” and its processor “…configured to: execute the application…” However, it is well known in the art that an application is software that includes programs that is executed by a processor to perform the operations of a computer system.
For explicit teaching, RAWSON, III et al. disclose a system (Figure 2, data processing system 200) comprising: a memory (e.g. main memory 208 and hard disk drive 226) comprising circuitry configured to store an application (e.g. applications or programs); and a processor coupled to the memory (e.g. processing unit 206 coupled to main memory via North bridge and memory controller (NB/MCH) 202 and coupled to hard disk drive 226 via South bridge and input/output hub (SB/ICH) 204), wherein the processor (processing unit 206) comprises circuitry configured to: execute the application as a plurality of wavefronts ([0047] notes applications or programs are located on storage devices, such as hard disk drive 226, and may be loaded into main memory 208 for execution by processing unit 206, where Figure 3 illustrates threads spawned by an application, where it may be considered a wavefront encompasses threads)… RAWSON, III et al. further disclose allocate a first set of registers to a first wavefront (e.g. similar to Figure 3, Figure 5, thread 502 may read and write to some or all of physical registers in subset 512 of physical registers 508; and thread 504 may read and write to some or all of physical registers in subset 518 of physical registers 508)…and release one or more registers of the first set of registers (Figure 5, [0069] notes during execution of an application, application may be determine that thread 502 is using only register 514 and not fully utilizing all physical registers 512, e.g. thread 502 may not be utilizing subset 516 of physical register 508, and application may also recognize that another thread, e.g. thread 504, may be able to use more physical registers than subset 518 currently allocated to that thread, [0070] notes reallocating physical registers 516 from thread 502 to thread 504, where thread 502 is not affected because thread 502 was not utilizing physical registers 516 prior to the reallocation).
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the Eckert et al.’s system to store and execute an application as described in RAWSON, III et al. such that the operations of the system may be performed as described, thus yielding predictable results, without changing the scope of the invention. It would have been further obvious to one of ordinary skill in the art at the time of the invention to modify Eckert et al.’s system and method of releasing one or more registers with RAWSON, III et al.’s method of releasing one or more registers while one or more threads of a wavefront remain active such that registers that are not being used may be utilized by other threads, thus improving efficiency in register utilization (see [0067] thru [0071] of RAWSON, III et al.).
Claim 36 is similar in scope to claim 24 and is therefore rejected under similar rationale.
Claim 37 is similar in scope to claim 23 and is therefore rejected under similar rationale.
As to claim 38, Eckert et al. modified with RAWSON, III et al. disclose the circuitry is configured to allocate the one or more registers of the first set of registers marked as being available to the second wavefront being launched on one of the plurality of compute circuits (modified with RAWSON, III, see claim 37 (claim 23)) while threads of the first wavefront remain active (modified with RAWSON, III, [0071] notes reallocation of registers may occur any number of times during execution of relevant threads, thus “while threads…remain active”).
Claim 39 is similar in scope to claim 25 and is therefore rejected under similar rationale.
Claim(s) 26, 33, and 40 is/are rejected under 35 U.S.C. 103 as being unpatentable over Eckert et al. (US 2017/0278213) in view of RAWSON, III et al. (US 2011/0296428) as applied to claims 25, 32, and 39 above, and further in view of Du et al. (US 2018/0165092).
As to claim 26, Eckert et al. modified with RAWSON, III et al. do not disclose, but Du et al. disclose the control circuit is configured to compact the one or more registers of the first set of registers into one or more contiguous blocks of registers by the first wavefront prior to being released ([0045] GPRs may be allocated, e.g. assigned and de-assigned, according to allocation information, the allocation information may indicate a contiguous logical block of registers in the GPR to be assigned as pGPRs, and a contiguous logical block of registers in the GPR to be assigned as vGPRs).
It would have been obvious to one of ordinary skill in the art at the time of the invention to further modify Eckert et al. modified with RAWSON, III et al.’s system and method of releasing one or more registers with Du et al.’s method of compacting registers prior to being released to optimize computer architecture by storing narrow-width operands in smaller spaces, reducing register file pressure, and enhancing performance (see [0045] of Du et al.).
Claims 33 and 40 are similar in scope to claim 26, and are therefore rejected under similar rationale.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACINTA M CRAWFORD whose telephone number is (571)270-1539. The examiner can normally be reached 8:30a.m. to 4:30p.m.
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/JACINTA M CRAWFORD/Primary Examiner, Art Unit 2617