DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 4-5 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Passerini et al. (US 20210287747).
PNG
media_image1.png
471
442
media_image1.png
Greyscale
PNG
media_image2.png
760
471
media_image2.png
Greyscale
PNG
media_image3.png
278
250
media_image3.png
Greyscale
PNG
media_image4.png
250
259
media_image4.png
Greyscale
PNG
media_image5.png
266
253
media_image5.png
Greyscale
PNG
media_image6.png
151
138
media_image6.png
Greyscale
With respect to claim 1, figs. 7A-7E, 8b of Passerini discloses a switch circuit, comprising: a first input node (at VSUPPLY_P) configured to receive a first input voltage (VSUPPLY_P); a second input node (at VSUPPLY_N) configured to receive a second input voltage (VSUPPLY_N), the second input voltage being lower than the first input voltage; an output node ( at OUT) configured to produce an output voltage switchable between the first input voltage and the second input voltage; a first transistor (MND2) having a first conductive terminal coupled to the first input node; a second transistor (at INT/ MP1) having a first conductive terminal coupled to a second conductive terminal of the first transistor (MND2), a second conductive terminal of the second transistor coupled to the output node (at OUT); a third transistor (MN1) having a first conductive terminal coupled to the second input node (at VSUPPLY_N); a fourth transistor (MCASC) having a first conductive terminal coupled to a second conductive terminal of the third transistor (MN1), a second conductive terminal of the fourth transistor coupled to the output node (at OUT); a first elevator (fig. 7B element 730 part producing EN_LS1) circuit configured to generate, at an output terminal of the first elevator circuit (at EN_LS1), a first shifted control signal based on a first low-voltage control signal (EN), the output terminal of the first elevator circuit coupled to a control terminal of the first transistor, the first elevator circuit biased between the first input voltage (HV) and a shifted ground voltage (GND); a second elevator circuit (fig. 7B element 730 part producing EN_LS1b) configured to generate, at an output terminal (at EN_LS1b) of the second elevator circuit, a second shifted control signal ( EN_LS1b) based on a second low-voltage control signal (EN_b), the output terminal of the second elevator circuit coupled to a control terminal of the second transistor (INT); a third elevator circuit (fig. 7B element 740 part producing EN_LS2) configured to generate, at an output terminal (at EN_LS2) of the third elevator circuit, a third shifted control signal (EN_LS2) based on a third low-voltage control signal (EN), the output terminal of the third elevator circuit coupled to a control terminal of the third transistor (MN1); and a fourth elevator circuit (fig. 7B element 740 part producing EN_LS2b) configured to generate, at an output terminal of the fourth elevator circuit (at EN_LS2b), a fourth shifted control signal (EN_B) based on a fourth low-voltage control signal (EN_LS2b), the output terminal of the fourth elevator circuit coupled to a control terminal of the fourth transistor, but fails to disclose the second elevator circuit biased between the output voltage (HV) and an elevated ground voltage (GND), the third elevator circuit biased between the second input voltage (VCC) and a ground voltage (VSUPPLY_N) and the fourth elevator circuit biased between the output voltage (VCC) and the elevated ground voltage (VSUPPLY_N).
PNG
media_image7.png
412
437
media_image7.png
Greyscale
Figure 5 of Passerini discloses a switching architecture that includes a switching block that receives positive and negative voltages used as bias selected word lines that provide output bias to the selection circuit such that the bias values are selectable. It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to make the bias lines of the “elevator” circuits of Passerini selectable as taught by Passerini for the purpose of reducing the area occupied by the switching architecture as a whole.
PNG
media_image1.png
471
442
media_image1.png
Greyscale
With respect to claim 4, the circuit above produces the switch circuit of claim 1, further comprising a precharge circuit (820) , coupled between the output node (OUT) and the ground voltage (GND), wherein the precharge circuit is activated in response to the output voltage being switched from the first input voltage to the second input voltage.
With respect to claim 5, the circuit above produces the switch circuit of claim 4, wherein the precharge circuit comprises: a transistor (MNDIODE) controllable by a precharge signal; and a cascode device (810) coupled in series between the transistor and the output node (at OUT).
With respect to claim 12, figs. 7A-7E, 8b of Passerini method of operating a switch circuit, the method comprising: receiving, at a first input node (at VSUPPLY_P) of the switch circuit, a first input voltage (VSUPPLY_P), wherein a first transistor (MND2) of the switch circuit includes a first conductive terminal coupled to the first input node; receiving, at a second input node (at VSUPPLY_N) of the switch circuit, a second input voltage (VSUPPLY_N), the second input voltage being lower than the first input voltage; producing, at an output node (at OUT) of the switch circuit, an output voltage switchable between the first input voltage and the second input voltage, wherein a second transistor (at INT/MP1) of the switch circuit includes a first conductive terminal coupled to a second conductive terminal of the first transistor (MND2), a second conductive terminal of the second transistor (at OUT) coupled to the output node, wherein a third transistor (MN1) of the switch circuit includes a first conductive terminal coupled to the second input node (at VSUPPLY_N), wherein a fourth transistor (MCASC) of the switch circuit includes a first conductive terminal coupled to a second conductive terminal of the third transistor (MN1), a second conductive terminal of the fourth transistor (MCSAC) coupled to the output node (at OUT); generating, at an output terminal (at EN_LS1), of a first elevator circuit (fig. 7B element 730 part producing EN_LS1), a first shifted control signal based on a first low-voltage control signal (EN), the output terminal of the first elevator circuit coupled to a control terminal of the first transistor, the first elevator circuit biased between the first input voltage (HV) and a shifted ground voltage (GND); generating, at an output terminal (at EN_LS1b) of a second elevator circuit (fig. 7B element 730 part producing EN_LS1b), a second shifted control signal based on a second low-voltage control signal, the output terminal (at EN_LS1b) of the second elevator circuit coupled to a control terminal of the second transistor (EN_LS1b), generating, at an output terminal of a third elevator circuit (fig. 7B element 740 part producing EN_LS2), a third shifted control signal (EN_LS2) based on a third low-voltage control signal (EN), the output terminal (at EN_LS2) of the third elevator circuit coupled to a control terminal of the third transistor, and generating, at an output terminal of a fourth elevator circuit (fig. 7B element 740 part producing EN_LS2b), a fourth shifted control signal (EN_B) based on a fourth low-voltage control signal (EN_LS2b), the output terminal of the fourth elevator circuit coupled to a control terminal of the fourth transistor (at EN_LS2b), but fails to disclose the second elevator circuit biased between the output voltage and an elevated ground voltage; the third elevator circuit biased between the second input voltage and a ground voltage; the fourth elevator circuit biased between the output voltage and the elevated ground voltage.
PNG
media_image7.png
412
437
media_image7.png
Greyscale
Figure 5 of Passerini discloses a switching architecture that includes a switching block that receives positive and negative voltages used as bias selected word lines that provide output bias to the selection circuit such that the bias values are selectable. It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to make the bias lines of the “elevator” circuits of Passerini selectable as taught by Passerini for the purpose of reducing the area occupied by the switching architecture as a whole.
Response to Arguments
Applicant's arguments filed 12/10/2025 have been fully considered but they are not persuasive.
With respect to Applicant’s argument that Passerini provides no teaching that these power supply rails (i.e. HV and GND and VCC and VSUPPLY_N) should be variable, selectable or dependent on output voltage, the Examiner disagrees.
Here, the teaching in Passserini is designed to reduce the area occupied by the switching architecture. Although applicant’s argue they are different, the fixed voltage lines as need not be switched. Examiner points out as the voltage lines are does not teach that it would not beneficial in [0100]-[0123] merely the values are assigned within certain parameters. This does not preclude the lines from being variable.
Applicant argues, the Applicant’s biasing scheme is set to maintain values within a margin. Similarly, as pointed out in ,Passerini the level shifters are held between specific values but does not preclude the values from toggling between the specific values and thus variability is included in the operation.
Applicant further argues, the rejection uses the term “bias” without establishing that they represent analogous technical concepts or that one skilled in the art would reasonably apply teaching from one context to another. The Examiner disagrees. Bias is a term of art generally known to mean “biasing is the setting of DC (direct current) operating conditions (current and voltage) of an electronic component that processes time-varying signals.” As this is taught in the cited paragraphs by the Applicant in Passerini [0100]-[0123] also establish that Passerini is looking to keep the circuits operating at certain levels but also includes the levels varying within the established parameters. This is not exclusive of Passerini as the Applicant suggest. Varying a voltage source to power to select different values to power different parts of a circuit is what the combination teaches for the purpose of reducing areas. This is not hindsight and indeed is taught within the same reference.
Allowable Subject Matter
Claims 2-3, 6-11 and 13-20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
With respect to claim 2, the prior art of record fails to suggest or disclose the wherein the shifted ground voltage is a fixed voltage, and wherein a difference between the first input voltage and the shifted ground voltage is between 2 and 2.5V, inclusive.
Here, the specific voltage range is not disclosed.
With respect to claim 3, the prior art of record fails to suggest or disclose wherein the elevated ground voltage is switched to: the shifted ground voltage, in response to the output voltage being switched to the first input voltage and the ground voltage, in response to the output voltage being switched to the second input voltage. With respect to claim 6, the prior art of record fails to suggest or disclose being configured to switch the output voltage from the first input voltage to the second input voltage by sequentially: deactivating the first transistor and the second transistor, setting the elevated ground voltage to ground voltage, and activating the third transistor and the fourth transistor; and switch the output voltage from the second input voltage to the first input voltage by sequentially: deactivating the third transistor and the fourth transistor, setting the elevated ground voltage to the shifted ground voltage, and activating the first transistor and the second transistor.
With respect to claim 8, the prior art of record fails to suggest or disclose wherein the first input voltage is between 4.5 and 5 V inclusive, and wherein the second input voltage is between 2 and 2.5 V inclusive.
Here, the specific voltage range is not disclosed.
With respect to claim 9, the prior art of record fails to suggest or disclose wherein the first transistor, the second transistor, the third transistor, and the fourth transistor are p-channel metal-oxide-semiconductor (MOS) transistors.
With respect to claim 10, the prior art of record fails to suggest or disclose an inverter coupled between the input node and a further node and configured to produce, at the further node, a complement signal of the low-voltage control signal; a fifth transistor having a source terminal coupled to the input node to receive the respective low-voltage control signal and a drain terminal coupled to the second latch node; and a sixth transistor having a source terminal coupled to the further node to receive the complement signal of the low-voltage control signal and a drain terminal coupled to the first latch node.
With respect to claim 14, the prior art of record fails to suggest or disclose switching the elevated ground voltage to the shifted ground voltage in response to the output voltage being switched to the first input voltage; and switching the elevated ground voltage to the ground voltage in response to the output voltage being switched to the second input voltage.
With respect to claim 15, the prior art of record fails to suggest or disclose the output voltage from the first input voltage to the second input voltage by sequentially: deactivating the first transistor and the second transistor, setting the elevated ground voltage to ground voltage, and activating the third transistor and the fourth transistor; and switching, by the control circuit, the output voltage from the second input voltage to the first input voltage by sequentially: deactivating the third transistor and the fourth transistor, setting the elevated ground voltage to the shifted ground voltage, and activating the first transistor and the second transistor.
Claims 16-20 are allowed.
With respect to claim 16, the prior art of record fails to suggest or disclose a first transistor having a source terminal couplable to the first input voltage; a second transistor having a source terminal coupled to a drain terminal of the first transistor, a drain terminal of the second transistor coupled to the output terminal of the switch circuit; a third transistor having a drain terminal couplable to the second input voltage; a fourth transistor having a drain terminal coupled to a source terminal of the third transistor, a source terminal of the fourth transistor coupled to the output terminal of the switch circuit; and a plurality of elevator circuits, each elevator circuit configured to generate, at its output terminal, a shifted control signal based on a low-voltage control signal, wherein a first elevator circuit is biased between the first input voltage and a shifted ground voltage and configured to provide a first shifted control signal to a gate terminal of the first transistor, wherein a second elevator circuit is biased between the output voltage and an elevated ground voltage and configured to provide a second shifted control signal to a gate terminal of the second transistor, wherein a third elevator circuit is biased between the second input voltage and a ground voltage and configured to provide a third shifted control signal to a gate terminal of the third transistor, and wherein a fourth elevator circuit is biased between the output voltage and the elevated ground voltage and configured to provide a fourth shifted control signal to a gate terminal of the fourth transistor.
Here, the source and the drains of the first, second, third and fourth transistors are not connected as disclosed with the associated results.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAREEM E ALMO whose telephone number is (571)272-5524. The examiner can normally be reached M-F (8:00am-4:00pm).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at M-F (8:00am-4:00pm). The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/KHAREEM E ALMO/Examiner, Art Unit 2849
/Menatoallah Youssef/SPE, Art Unit 2849